JPH07202164A - Manufacture of semiconductor micro-structure - Google Patents
Manufacture of semiconductor micro-structureInfo
- Publication number
- JPH07202164A JPH07202164A JP35045293A JP35045293A JPH07202164A JP H07202164 A JPH07202164 A JP H07202164A JP 35045293 A JP35045293 A JP 35045293A JP 35045293 A JP35045293 A JP 35045293A JP H07202164 A JPH07202164 A JP H07202164A
- Authority
- JP
- Japan
- Prior art keywords
- mask
- oxide film
- anodic oxide
- film
- porous anodic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Lasers (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Drying Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、量子井戸箱などの半導
体微細構造の製作方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor fine structure such as a quantum well box.
【0002】[0002]
【従来技術】最近、量子細線、量子井戸箱などの半導体
微細構造を伝導デバイス、半導体レーザの活性層に利用
することが注目されている。特に、量子井戸箱を半導体
レーザ素子の活性層に用いると、最大利得が増すと共
に、温度上昇に伴う利得の低下を防止することができ
る。従って、このような半導体レーザ素子では、しきい
値電流を著しく低減できると共に、その温度依存性を殆
ど零にできることが予測されている。このような利点を
得るには、量子井戸箱のサイズが10nm程度以下であ
り、かつ、その不均一性が十分に小さくなければならな
い。従来、量子井戸箱は電子ビームリソグラフィとイオ
ンミリングを用いる方法、あるいは光干渉露光と化学エ
ッチングを用いるなどの方法で製作され、数10nm程
度のサイズが実現している。2. Description of the Related Art Recently, attention has been paid to the use of semiconductor fine structures such as quantum wires and quantum well boxes in conductive devices and active layers of semiconductor lasers. In particular, when the quantum well box is used for the active layer of the semiconductor laser device, the maximum gain can be increased and the decrease of the gain due to the temperature rise can be prevented. Therefore, in such a semiconductor laser device, it is predicted that the threshold current can be remarkably reduced and its temperature dependence can be almost zero. In order to obtain such an advantage, the size of the quantum well box must be about 10 nm or less, and its nonuniformity must be sufficiently small. Conventionally, the quantum well box is manufactured by a method using electron beam lithography and ion milling, or a method using optical interference exposure and chemical etching, and a size of about several tens nm is realized.
【0003】[0003]
【発明が解決しようとする課題】しかしながら、従来の
量子井戸箱の製作方法には以下のような問題があり、1
0nm程度以下の均一なサイズの量子井戸箱は実現して
いない。即ち、 1)電子ビームリソグラフィに用いるマスクに、10n
m程度以下の微細な窓を開けることが困難である。ま
た、電子ビームリソグラフィには2次電子による加工限
界がある。 2)従来の方法では、ビーム掃引によりマスクの窓開け
を行っていたため、マスクのスループットに問題があ
り、マスクの量産が困難であった。However, the conventional method of manufacturing a quantum well box has the following problems.
A quantum well box with a uniform size of about 0 nm or less has not been realized. That is, 1) For a mask used for electron beam lithography, 10n
It is difficult to open a fine window of about m or less. Further, electron beam lithography has a processing limit due to secondary electrons. 2) In the conventional method, since the window of the mask is opened by beam sweep, there is a problem in the throughput of the mask and it is difficult to mass-produce the mask.
【0004】[0004]
【課題を解決するための手段】本発明は上記問題点を解
決した半導体微細構造の製作方法を提供するもので、半
導体基板面上にマスクを形成する工程と、該マスクを用
いて選択成長を行う工程と、該選択成長後に前記マスク
を除去する工程と、前記マスクを除去した後埋め込み成
長を行う工程を有する半導体微細構造の製作方法におい
て、マスクは多孔質陽極酸化膜からなることを第1発明
とし、半導体基板面上にマスクを形成する工程と、該マ
スクを用いてエッチングを行う工程と、該エッチング後
に前記マスクを除去する工程と、前記マスクを除去した
後埋め込み成長を行う工程を有する半導体微細構造の製
作方法において、マスクは多孔質陽極酸化膜からなるこ
とを第2発明とするものである。The present invention provides a method for manufacturing a semiconductor fine structure which solves the above-mentioned problems, and comprises a step of forming a mask on the surface of a semiconductor substrate and a selective growth using the mask. In the method of manufacturing a semiconductor fine structure, which comprises the steps of: performing the selective growth, removing the mask after the selective growth, and performing the buried growth after removing the mask, the mask comprises a porous anodic oxide film. The present invention includes the steps of forming a mask on a semiconductor substrate surface, performing etching using the mask, removing the mask after the etching, and performing embedded growth after removing the mask. In the method of manufacturing a semiconductor fine structure, the second invention is that the mask is made of a porous anodic oxide film.
【0005】[0005]
【作用】アルミニウムなどの陽極酸化膜は、電解液によ
る溶解作用の程度により、緻密な部分と多孔質部分から
なる。多孔質部分は、それを構成する単位組織であるセ
ルが蜂の巣状集積したものである。セル内の孔の内径と
間隔はともに、電解液の種類、陽極酸化の条件を変える
ことにより、〜10nmのオーダで任意に、かつ、精度
良く制御することができる。本発明は、このような多孔
質陽極酸化膜を選択成長やエッチングのマスクに用たも
ので、そうすることにより、半導体微細構造を所望の大
きさと間隔で精度よく形成することができる。The anodic oxide film of aluminum or the like is composed of a dense portion and a porous portion depending on the degree of dissolution by the electrolytic solution. The porous portion is a honeycomb-shaped accumulation of cells, which are the unit tissues constituting the porous portion. Both the inner diameter and the interval of the holes in the cell can be arbitrarily and accurately controlled on the order of -10 nm by changing the type of electrolyte and the conditions of anodic oxidation. The present invention uses such a porous anodic oxide film as a mask for selective growth or etching, and by doing so, a semiconductor fine structure can be formed with a desired size and interval with high precision.
【0006】[0006]
【実施例】以下、図面に示した実施例に基づいて本発明
を詳細に説明する。 実施例1 図1は、本発明にかかる半導体微細構造の製作方法の一
実施例の製作工程説明図である。その工程は以下の通り
である。即ち、 1)InP基板1上にAl膜2を形成する(図1
(a))。 2)Al膜2を陽極酸化法により表面を酸化し、多孔質
陽極酸化膜3を形成する(図1(b))。 3)多孔質陽極酸化膜3をマスクとして、アルゴンスパ
ッタ法によりAl膜2にInP基板1に達する窓4を開
ける(図1(c))。 4)次いで、Al膜2、多孔質陽極酸化膜3をマスクと
して有機金属分子線エピタキシ法によりGaInAsP
層5の選択成長を行う(図1(d))。 5)選択成長後、Al膜2、多孔質陽極酸化膜3からな
るマスクを除去し、GaInAsP層5をInP層6に
より埋め込む(図1(e))。 上記の工程により、GaInAsPからなる量子井戸箱
をInP中に形成することができる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the embodiments shown in the drawings. Example 1 FIG. 1 is a manufacturing process explanatory view of an example of a method for manufacturing a semiconductor fine structure according to the present invention. The process is as follows. That is, 1) forming an Al film 2 on the InP substrate 1 (see FIG. 1).
(A)). 2) The surface of the Al film 2 is oxidized by an anodic oxidation method to form a porous anodic oxide film 3 (FIG. 1 (b)). 3) Using the porous anodic oxide film 3 as a mask, a window 4 reaching the InP substrate 1 is opened in the Al film 2 by the argon sputtering method (FIG. 1 (c)). 4) Then, using the Al film 2 and the porous anodic oxide film 3 as a mask, GaInAsP is formed by a metal organic molecular beam epitaxy method.
Selective growth of the layer 5 is performed (FIG. 1D). 5) After the selective growth, the mask made of the Al film 2 and the porous anodic oxide film 3 is removed, and the GaInAsP layer 5 is filled with the InP layer 6 (FIG. 1 (e)). Through the above steps, the quantum well box made of GaInAsP can be formed in InP.
【0007】実施例2 図2は、本発明にかかる半導体微細構造の製作方法の他
の実施例の製作工程説明図である。その工程は以下の通
りである。即ち、 1)実施例1と同じく、InP基板1上にAl膜2を形
成する(図2(a))。 2)Al膜2を陽極酸化法により酸化し、多孔質陽極酸
化膜3を形成する(図2(b))。 3)多孔質陽極酸化膜3をマスクとして、アルゴンスパ
ッタ法によりAl膜2に窓4を開ける(図2(c))。 4)次いで、Al膜2、多孔質陽極酸化膜3をマスクと
して、InP基板1をエッチングして孔7を形成する
(図2(d))。 5)次いで、Al膜2、多孔質陽極酸化膜3からなるマ
スクを除去し、孔7をGaInAsP層8で埋め込み、
さらに表面をInP層9で覆う。 上記の工程により、実施例1と同様のGaInAsPか
らなる量子井戸箱をInP中に形成することができた。
なお、上記実施例では、Alの多孔質陽極酸化膜を用い
たが、Mg、Si、GaAs系半導体、あるいはInP
系半導体などの多孔質陽極酸化膜を用いてもよい。ま
た、InP基板を例にとって説明したが、GaAs系を
はじめSi、Geのウェハ、あるいはエピタキシャル積
層基板を用いてもよい。また、孔に埋め込み選択成長さ
せる材質は、InP系だけでなく、GaAs系をはじめ
SiやGeの単結晶の単独あるいはその組み合わせを使
用してもよい。さらに、アルゴンスパッタ法により、多
孔質陽極酸化膜をマスクとしてAl膜に窓を開けたが、
エッチング手段として湿式エッチングやドライエッチン
グを利用してもよい。Embodiment 2 FIG. 2 is an explanatory view of a manufacturing process of another embodiment of the method for manufacturing a semiconductor fine structure according to the present invention. The process is as follows. That is, 1) As in Example 1, the Al film 2 is formed on the InP substrate 1 (FIG. 2A). 2) The Al film 2 is oxidized by an anodic oxidation method to form a porous anodic oxide film 3 (FIG. 2B). 3) Using the porous anodic oxide film 3 as a mask, a window 4 is opened in the Al film 2 by an argon sputtering method (FIG. 2 (c)). 4) Next, using the Al film 2 and the porous anodic oxide film 3 as a mask, the InP substrate 1 is etched to form holes 7 (FIG. 2 (d)). 5) Next, the mask made of the Al film 2 and the porous anodic oxide film 3 is removed, and the holes 7 are filled with the GaInAsP layer 8.
Further, the surface is covered with the InP layer 9. Through the above steps, a quantum well box made of GaInAsP similar to that in Example 1 could be formed in InP.
Although a porous anodic oxide film of Al is used in the above embodiment, Mg, Si, GaAs based semiconductor, or InP is used.
A porous anodic oxide film such as a system semiconductor may be used. Although the InP substrate has been described as an example, a GaAs-based wafer, a Si or Ge wafer, or an epitaxial laminated substrate may be used. Further, as the material to be embedded and selectively grown in the holes, not only InP-based materials but also GaAs-based and single crystals of Si and Ge may be used alone or in combination. Furthermore, a window was opened in the Al film using the porous anodic oxide film as a mask by the argon sputtering method.
Wet etching or dry etching may be used as the etching means.
【0008】[0008]
【発明の効果】以上説明したように本発明によれば、半
導体基板面上にマスクを形成する工程と、該マスクを用
いて選択成長あるいはエッチングを行う工程と、該選択
成長あるいはエッチング後に前記マスクを除去する工程
と、前記マスクを除去した後埋め込み成長を行う工程を
有する半導体微細構造の製作方法において、マスクは多
孔質陽極酸化膜からなるため、10nm以下のサイズで
精度よく制御された均一性のよい半導体微細構造を製作
することができるという優れた効果がある。As described above, according to the present invention, the step of forming a mask on the surface of a semiconductor substrate, the step of performing selective growth or etching using the mask, and the mask after the selective growth or etching In a method for manufacturing a semiconductor fine structure, which comprises a step of removing a mask and a step of performing buried growth after removing the mask, since the mask is made of a porous anodic oxide film, the size is 10 nm or less, and the uniformity is controlled accurately. There is an excellent effect that a fine semiconductor microstructure can be manufactured.
【図1】(a)〜(e)は、本発明に係る半導体微細構
造の製作方法の一実施例の製作工程説明図である。1 (a) to 1 (e) are manufacturing process explanatory views of an embodiment of a method for manufacturing a semiconductor microstructure according to the present invention.
【図2】(a)〜(e)は、本発明に係る半導体微細構
造の製作方法の他の実施例の製作工程説明図である。2 (a) to 2 (e) are manufacturing process explanatory views of another embodiment of the method for manufacturing a semiconductor microstructure according to the present invention.
1 InP基板 2 Al膜 3 多孔質陽極酸化膜 4 窓 5、8 GaInAsP層 6、9 InP層 7 孔 1 InP substrate 2 Al film 3 Porous anodic oxide film 4 Window 5, 8 GaInAsP layer 6, 9 InP layer 7 Hole
フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01S 3/18 Continuation of front page (51) Int.Cl. 6 Identification number Office reference number FI technical display location H01S 3/18
Claims (2)
と、該マスクを用いて選択成長を行う工程と、該選択成
長後に前記マスクを除去する工程と、前記マスクを除去
した後埋め込み成長を行う工程を有する半導体微細構造
の製作方法において、マスクは多孔質陽極酸化膜からな
ることを特徴とする半導体微細構造の製作方法。1. A step of forming a mask on the surface of a semiconductor substrate, a step of performing selective growth using the mask, a step of removing the mask after the selective growth, and a step of embedded growth after removing the mask. A method of manufacturing a semiconductor fine structure, comprising a step of performing, wherein the mask is made of a porous anodic oxide film.
と、該マスクを用いてエッチングを行う工程と、該エッ
チング後に前記マスクを除去する工程と、前記マスクを
除去した後埋め込み成長を行う工程を有する半導体微細
構造の製作方法において、マスクは多孔質陽極酸化膜か
らなることを特徴とする半導体微細構造の製作方法。2. A step of forming a mask on the surface of a semiconductor substrate, a step of etching using the mask, a step of removing the mask after the etching, and a step of performing buried growth after removing the mask. A method of manufacturing a semiconductor fine structure having a mask made of a porous anodic oxide film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP35045293A JPH07202164A (en) | 1993-12-28 | 1993-12-28 | Manufacture of semiconductor micro-structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP35045293A JPH07202164A (en) | 1993-12-28 | 1993-12-28 | Manufacture of semiconductor micro-structure |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH07202164A true JPH07202164A (en) | 1995-08-04 |
Family
ID=18410594
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP35045293A Pending JPH07202164A (en) | 1993-12-28 | 1993-12-28 | Manufacture of semiconductor micro-structure |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07202164A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6121075A (en) * | 1997-05-30 | 2000-09-19 | Matsushita Electric Industrial Co., Ltd. | Fabrication of two-dimensionally arrayed quantum device |
US6309554B1 (en) | 1998-06-12 | 2001-10-30 | The University Of Tokyo | Method for producing needle diamond-type structure |
US6350389B1 (en) | 1998-06-12 | 2002-02-26 | The University Of Tokyo | Method for producing porous diamond |
WO2004055872A3 (en) * | 2002-12-13 | 2005-02-24 | Canon Kk | Columnar structured material and method of manufacturing the same |
JP2006191074A (en) * | 2005-01-07 | 2006-07-20 | Samsung Corning Co Ltd | Method for manufacturing epitaxial wafer |
JP2008511985A (en) * | 2004-08-31 | 2008-04-17 | エージェンシー フォー サイエンス,テクノロジー アンド リサーチ | Nanostructure and method for producing the same |
-
1993
- 1993-12-28 JP JP35045293A patent/JPH07202164A/en active Pending
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6121075A (en) * | 1997-05-30 | 2000-09-19 | Matsushita Electric Industrial Co., Ltd. | Fabrication of two-dimensionally arrayed quantum device |
US6287928B1 (en) | 1997-05-30 | 2001-09-11 | Matsushita Electric Industrial Co., Ltd. | Two-dimensionally arrayed quantum device |
US6319738B1 (en) | 1997-05-30 | 2001-11-20 | Matsushita Electric Industrial Co., Ltd. | Two-dimensionally arrayed quantum device fabrication method |
US6635494B2 (en) | 1997-05-30 | 2003-10-21 | Matsushita Electric Industrial Co., Ltd. | Method of forming a two-dimensionally arrayed quantum device using a metalloprotein complex as a quantum-dot mask array |
US7015139B2 (en) | 1997-05-30 | 2006-03-21 | Matsushita Electric Industrial Co., Ltd. | Two-dimensionally arrayed quantum device |
US6309554B1 (en) | 1998-06-12 | 2001-10-30 | The University Of Tokyo | Method for producing needle diamond-type structure |
US6350389B1 (en) | 1998-06-12 | 2002-02-26 | The University Of Tokyo | Method for producing porous diamond |
WO2004055872A3 (en) * | 2002-12-13 | 2005-02-24 | Canon Kk | Columnar structured material and method of manufacturing the same |
US7387967B2 (en) | 2002-12-13 | 2008-06-17 | Canon Kabushiki Kaisha | Columnar structured material and method of manufacturing the same |
US7892979B2 (en) | 2002-12-13 | 2011-02-22 | Canon Kabushiki Kaisha | Columnar structured material and method of manufacturing the same |
JP2008511985A (en) * | 2004-08-31 | 2008-04-17 | エージェンシー フォー サイエンス,テクノロジー アンド リサーチ | Nanostructure and method for producing the same |
JP2006191074A (en) * | 2005-01-07 | 2006-07-20 | Samsung Corning Co Ltd | Method for manufacturing epitaxial wafer |
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