JPH0477943A - Address information generation method - Google Patents

Abstract

PURPOSE:To unnecessitate ALU by changing the value of a second counter circuit in a next cycle when the value of a first counter circuit comes to the limited value of a desired area and holding a loaded value after an initial address position is loaded in the high-order bit group of the first counter circuit. CONSTITUTION:The initial address positions of the desired areas are loaded on the first and the second counter circuits 16a and 16b and they are divided into the high-order bit and low-order bit groups. The low-order bit group of the first counter circuit 16a which can be operated is set to be operable and the value of the low-order bit group is changed. Then, the value of the second counter circuit 16b is changed by one in the next cycle when the value comes to the boundary value of the desired area, namely, a maximum value or a minimum value. The high-order bit group of the first counter circuit 16a comes to a counting operation impossible state after the initial address position is loaded and the first counter circuit 16a returns to the initial value at that time since it holds the value. Thus, an arithmetic logical operation unit (ALU) is unnecessitated.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method for generating address information for addressing a memory, and particularly relates to a method for generating address information for addressing a desired area of a memory divided into a plurality of areas. .

[Prior Art] An address information generator is a device that generates desired X and Y address values for data writing or data reading. Address information generators are also used in semiconductor memory testing equipment that performs functional tests on semiconductor memories such as random access memories (hereinafter referred to as "RAM").

In general, a RAM functional test tests the data of the target memory cell and other memory cells in a predetermined manner, for example.
This is done by checking whether or not an error has occurred by reading the data alternately. Usually, cells of interest are designated in order starting from address 0.

[Problems to be Solved by the Invention] In a RAM functional test, if the RAM has a large capacity and the error location can be estimated to some extent, the memory test is performed on a specific memory area. For example, in FIG. 2, which shows a model of the memory capacity of a RAM, consider the case where only the area indicated by "f" is tested in a walking pattern, that is, each adjacent memory cell is tested in turn. In the f area, the address (x, y) is (1000000
0,01000000>～(10111111,011
11111), and the lower left address of the f area is address zero (o o o o o o o o
,oooo.

000), (10000000,01000
000).

In the conventional test method using a normal address counter circuit, when testing this f area, the change in the XY address value increases from the X address value (10000000) and reaches the maximum value (101, 11111). The offset amount described above must be reloaded on the next test cycle.

Alternatively, if an address generator having an arithmetic logic unit (called "ALtJ") function is used, the range of the X-axis address counter circuit can be set to the size of the f area (O~1000
000), and it is necessary to generate the desired address value by adding the above-mentioned offset amount every time the cycle moves to the next cycle. At this time, the cycle in which the offset amount is loaded to the address counter is a non-testable cycle, that is, a dummy cycle.
It becomes a cycle. Furthermore, in order to implement an ALU, the hardware configuration becomes complicated and expensive.

The drawback is that the operating frequency is also limited to a low level.

Furthermore, in the conventional testing method, when testing areas equally divided into predetermined sizes individually and sequentially, each time the area moves to the next area, the address value of the first position of the next area is loaded. To this end, conventionally, a plurality of registers are prepared in which the first address position of each area is stored, and the contents of the registers are rewritten while each area is being addressed. But with a large number of registers,
This has the drawback that the configuration becomes complicated, and in order to rewrite the contents of the register, it is necessary to store a large amount of data for rewriting in the data memory.

Therefore, the object of the present invention is to eliminate the need for ALU etc.
An object of the present invention is to provide an address information generation method that allows a desired area of a RAM to be addressed with a device having a simple configuration.

Another object of the present invention is to provide an address information generation method for efficiently specifying addresses continuously in a plurality of equally divided memory areas.

[Means for Solving the Problems] The present invention provides an address information generation method for addressing a desired area out of a plurality of equally divided areas of a memory area, the method comprising: A plurality of bits of at least a first counter circuit among the first and second counter circuits are divided into an upper bit group indicating the position of the plurality of equally divided areas and a lower bit group indicating the address position within the area. a first step; a second step of loading the first and second counter circuits with the addressing start address of the desired area; and a third step of enabling only the lower bit group of the first counter circuit to perform a counting operation; a fourth step of changing the value of the lower bit group of the first counter circuit and changing the value of the second counter circuit when the value reaches a predetermined boundary value of the desired area; The feature is that the fourth step is repeated until the designation is made.

[Operation] Load the first address position of the desired area into the first and second counter circuits, and count the lower bit group of the first counter circuit, which can be divided into upper bit and lower bit groups and made operational. the value of the lower bit group of the first counter circuit is changed, and in the next cycle when the value of the lower bit group of the first counter circuit reaches the boundary value of the desired region, that is, the maximum value or the minimum value, the value of the second counter circuit is changed by l. Ru. Since the upper bit group of the first counter circuit is disabled for counting after the first address location is loaded and holds the value, the first counter circuit returns to the initial value at this time. Therefore, it is necessary to reload the value of the first counter circuit or use the ALU to input the address.
There is no need to generate an address value by adding an offset amount from zero.

[Embodiment] FIG. 1 is a block diagram showing an address information generation device for realizing the address information generation method of the present invention. C
A sequence controller (10) including a PU is supplied with a clock signal, operates in synchronization with the clock signal, and generates various control signals for controlling the operation timing and the like of the apparatus.

The controller (10) is capable of supplying clock signals to other components in the device through its internal parts and also controlling the start and stop of their supply. A data memory (12) such as a RAM is preloaded with a microprogram for generating test patterns. This test pattern includes data such as numerical data for selecting memory cells of the memory under test, addressing order for writing and reading. The controller (10) has a memory (1
2) reads and decodes the microprogram, outputs a control signal, and controls the output of numerical data;

The X-axis address information is provided by the bit division latch circuit (14a)
, counter circuit (16a), register circuit (18a),
Digital comparator (20a) and carry generator (22)
The Y-axis address information is generated from an X-address information generator including a bit division latch circuit (14b), a counter circuit (16b), a register circuit (18b), a digital comparator (20b), and a carry generator (22). It is generated from a Y-axis address information generation unit including the Y-axis address information generator. The bit division latch circuit, counter circuit, register circuit, and comparator of the X-axis and Y-axis address information generation sections have the same configuration, and when explaining each of these components in common, the symbols a and b are used. Omitted. The X and Y address information from the X-axis and Y-axis address information generators are respectively sent to counter circuits (16a).
and (16b), and is used as address information for writing and reading data into the memory.

The counter circuit (16) is, for example, an 8-bit counter circuit, and has a clock terminal, a data terminal, a control terminal, a carry terminal, and a bit enable terminal. However, in this embodiment, the carry-1 terminal is used only in the Y-axis address generation section and is not used in the X-axis address generation section.A clock signal via the controller (10) is input to the clock terminal. Numerical data from the controller (10) is input to the data terminal, and the counter circuit (16)
After the numerical data serving as the first addressed position is loaded, the control signal supplied from the controller (10) to the control terminal that performs the counting operation in synchronization with the clock signal is as follows:
Controls loading of numerical data, counting direction (count up or count down), etc.

The feature of this counter circuit (16) is that it divides the output bits into two groups, arbitrary upper bits and lower bits, and selects only one group according to the bit enable signal supplied to the bit enable terminal. It is possible to perform a counting operation, that is, to enable it. Further, in the Y-axis counter circuit (16b), the counter circuit (16b) performs a counting operation with respect to the clock signal input during the period in which the signal is supplied to the carry-1 terminal. The specific configuration and operation of this counter circuit (16) will be described later.

The bit division latch circuit (14) includes a counter circuit (1
Data for dividing the output bits of step 6) into groups of upper and lower bits is input.

This data is held in the bit division latch circuit (14) when a latch enable signal is supplied. Further, the bit division latch circuit (14) is supplied with an upper bit or lower bit selection signal. Depending on this signal,
A bit enable signal for enabling one of the divided upper bits or lower bit groups is output from the bit division latch circuit (14).

In the X-axis address generator, the bit enable signal is
In addition to being supplied to the counter circuit (16a) as described above,
Carry signal generator (22) and digital comparator (20)
a) is also supplied. In addition, in the Y-axis address generation section,
The bit enable signal is provided to a counter circuit (16b) and a comparator (20b). The carry signal generator (22) has 8 bits, the digital comparator (20) has 8 pairs of input bits, and the same bit groups as the counter circuit (16a) are enabled.

As shown in FIG. 6, the carry signal generator (22) includes eight OR circuits corresponding to the input bits, four NAND gates to which these outputs are supplied, and the output of the NAND gate. The bit corresponding to the OR circuit is enabled by inputting O or 1 to one input terminal of the OR circuit. The carry signal generator (22a) generates a signal when the enabled bits of the count output from the counter circuit (16a) have the same value, that is, when they all become 1 in the case of counting up. In the case of countdown, a carry signal is generated when all O's are reached. Before starting the operation of the counter circuit (16), the Y-axis and Y-axis register circuits (18a) and (18b) record the final address positions of X and Y, respectively, of the address information to be generated.
Address values have been previously loaded from the controller (10).

The digital comparator (20) has a counter circuit (16) and a register circuit (
Compare each bit value of 18), and if the values match, supply a match signal to the controller (10) 6 x and Y axis comparator (
20a) and (20b) simultaneously transmit the coincidence signal to the controller (
10), the controller (lO) performs predetermined control based on the microprogram.

The operation of addressing a desired area using this address information generating device will now be described. Here, in order to simplify the explanation, each of the X and Y axis addresses of a 256x256 bit memory is equally divided into four areas to form a total of 16 areas, as shown in FIG.

First, among these 16 areas, for example, area f is selected as one desired area to be addressed. The addressing procedure performed within this area is as follows: For the minimum Y-axis address value, increase the X-axis address value, and each time the X-axis address value reaches the maximum value within this area, increase the Y-axis address value, and shall specify all address positions within.

Operationally, an X and Y axis bit split latch circuit (14a);
(14b) are both based on the data from the controller (10), in which 8 bits are divided into 6 lower groups.
Divide the bits so that the upper group has 2 bits. The lower 6 bits of the Y-axis and Y-axis address information are
Used for addressing within each area, the upper 2 bits are
It is easy to understand that this is used to specify one of the 16 areas.

In order to start addressing from the lower left end point of the f area, the
0) is loaded. In addition, in order to terminate at the upper right point of the f area, the X and Y register circuits (18a) and (1s b) have (1011, 1111) and (
01111111) is stored. Further, in order to specify addresses in the above order, a counter circuit (16a
) and (16b), the counting direction is ゛count・
"Up".

To begin addressing, the X and Y-axis bit split latch circuits (14a) and (14b) operate based on a lower bit selection signal from the controller (10) to enable the lower six divided bits. , generates the lower bit enable signal.

When the lower bits of the X and Y axes are enabled, the X-axis counter circuit (16a) starts counting from (10000000). In this state, the Y-axis counter circuit (
16b) holds (01000000).

When the X-axis counter value reaches (10111111), the carry generator (22) starts the Y-axis counter circuit (16).
generate a carry signal to be supplied to the carry terminal of b); When the Y-axis counter receives a carry signal, the counter value increases by 1 and becomes (01000001), and at the same time, the counter value of the X-axis force 92 counter circuit (16a) changes so that the lower bit becomes (OOO000). ). The upper bit group of the X-axis force 92 circuit (16a) is disabled, so it retains the value originally loaded; From (10111111) to (1
You can go back to 0000000. Thereafter, addresses are specified in the same way, and the X and Y axis counter circuits (16a),
The counter value of (16b) is the maximum address value of X and Y of f area (10111111) and (0111111,
1), the X and Y axis comparators (20a), (20
b) outputs the coincidence signal to the controller (10);
10) is a counter circuit (16a) in response to the coincidence signal.
and (16b), and the addressing operation is completed.

Next, a, b, c, d, e, f,
The operation of sequentially selecting and addressing areas g, h and i will be described with reference to FIGS. 2 and 3. This description will provide a more detailed understanding of the operation of the device.

For convenience, the lower bit groups of the X and Y axis address information are referred to as XL and YL, respectively, and the upper bit groups are referred to as X, respectively.
H and Y) I, and the X and Y axis address information is represented by
HOX LCI~X HmaxX Lmax and Y
The order of addressing within each area, expressed as HOY LO to Y HmaxY Lmax, is the same as the order described above for the f area. To start addressing from the bottom left point of area a, the X and Y axis counter circuits (1
6a), (16b), XHOXLO=
(00000000), Y)lOYLO= (OOOO
OOOO) value is loaded. In addition, in order to end counting at the upper right point of the i area, the X and Y register circuits (18a) and (18b) are provided with X Hmax
Lmax= (10111111) and Y HmaxY
Lmax=(10111111) is stored.

Similar to the above, an X and Y axis counter circuit (16a),
(16b) When the lower bit of the axis is enabled, the X-axis force 92 data circuit (15a)
Counting starts from 00000). In this state, Y
The axis counter circuit (16b) calculates YHOYLO= (OO
OOOO00) is held.

The X-axis counter value is XHOXLmax= (00111
11,1), the carry generator (22) detects that all the lower bits have become 1, and generates a 9th order clock that generates a carry signal to be supplied to the Y-axis counter circuit (16b). So, lower bit XL=(000000)
, the lower bit YL=(000001) increases, and the Y-axis counter value becomes YHOYL1=(0000
0001), and the carry signal returns to its original level. During this time, the X-axis digital comparator (20a) calculates the
Since XLmax=(111111) is compared with the X-axis counter value XL, a match signal similar to the carry signal of the carry generation circuit (22) is generated.

Lower bit Y of the counter value of the Y-axis counter circuit (16)
When L increases to YLmax=(l l 1111), the Y-axis digital comparator (20b) generates a match signal. YHOYLmax= (OO111111
), when the lower bit XL reaches XLmax,
The X and Y axis match signals are simultaneously supplied to the controller, and the controller (10) operates the X axis bit split latch circuit (1) based on the microprogram in the program memory (12).
4a), and the upper bit enable signal from the X-axis bit division latch circuit (14a) is supplied to the counter circuit (16a) and the comparator (20a).
The upper bit XH1, that is, the upper 2 bits of the signal are enabled. The upper bit enable signal is the carry generator (2
2) is also supplied. At the clock at which the X-axis upper bit selection signal is generated, lower bits XL and YL are both (0
00000), and the X and Y axis counter values are
HOXLO= (00000000) and YHOYLO
= (00000000), this address information is unnecessary data that again addresses the lower left point of area a. However, the timing at which this unnecessary data occurs is
Since this is known from the addressing procedure, it is sufficient to control the drive circuit (not shown) of the memory under test to prevent data write and read operations from occurring at this timing. At the next clock, the upper bit XH is incremented by 1 to become XH+=(01), and the addressed area is moved to the adjacent memory area on the right.

By a similar operation, the address specification moves from area b to area C, and the point at the upper right corner of area C, XHmaxXLmax=
(10111111), Y! (OY Lmax=
(0011111], ) is reached, the controller (10)
receives coincidence signals from the X and Y axis comparators (20a) and (20b) simultaneously. With the next clock signal, the controller (lO), based on the microprogram in the memory (12), sends the X and Y axis upper bit selection signals to the X and Y axis bit division latch circuits (14a) and (1, 4b)
supply to. At the clock to which these upper bit selection signals are supplied, the X and Y axis counter values are respectively XHmax
XI, O= (10000000), YHOYLO=
Since this address data (OO000000) is unnecessary data, it can be ignored if writing to or reading from the memory under test is not performed at this timing, as described above. At the next clock signal, the controller (1
0) generates the lower bit selection signal, and at the same time, the Y-axis counter value is Y)l]YLO= (01000000)
Therefore, the X-axis counter circuit has XHOXLO= (0
0000000) is loaded and the addressing area is
Move to area d shown in FIG.

Hereafter, by continuing the same address specification as above, e,
f% g, advance to the i area, the upper right point of the i area, that is, the last point of the addressing range, X HmaxX Ln
+ax=(101111,11), Yt(maxY
When Lmax= (101, 1111, ], ) is reached, the controller (10) simultaneously receives and receives coincidence signals from the
Generates an axis upper bit selection signal and enables the upper bit. Simultaneously with the generation of this signal, the X and Y axis counter values are respectively XHmaxXLO= (1000000
0), YHmaxYLO=(10000000). Upper bits XH and Yl (are Xmax and Yma
Since x is maintained, the X and Y axis comparators (20a),
(20b) continues to generate a match signal. Controller (
10) detects this state in which the X and Y axis coincidence signals are supplied and the X and Y axis upper bit selection signals are generated, the X and Y axis counter circuit (16a);
(16b) and stop supplying the clock signal to X and Y.
The axis counter values are XH cumulativeaxXLO and Y)lma, respectively.
xY held in LO. However, since the input of address information to the driver circuit of the memory under test is stopped when the upper bit selection signal is generated, these counter values are not used for address specification.

FIG. 4 is a circuit diagram showing a specific configuration of the counter circuit (16) shown in FIG. 1. However, the counter circuit (16) in FIG. 1 has an 8-bit output, but for the sake of simplicity, the counter circuit in FIG. 4 has a 4-bit output configuration. Even if the number of output bits is different, the actual operation is the same. The 4-bit output values Q0 to Q3 of the counter circuit (16) are supplied from the Q output terminals of four flip-flop circuits (hereinafter referred to as "FF circuits") (32) to (38). These four output bits are
By supplying a logic O signal to the enable input terminals /ENO to /EN3, a countable state is enabled, and by supplying a logic 1 signal, a countable state is enabled. Thus, by providing logical O and I signals, it is possible to divide into upper and lower bit groups and enable one group.

Each FF circuit has the same configuration, and has a data input terminal D, count up/down terminals U/D, and
Load terminal LOA Dl It has a count enable terminal /EN and a clock terminal CLK, and the output side has a count control output terminal /C in addition to the Q output terminal. The decoder (40) has three mode selection bit terminals on the input side and a carry signal to which a carry signal is supplied from the carry generator (22) when used as the Y-axis counter circuit (16b) in FIG. It has one terminal /CARRY. U/D terminals and LO of F1 circuits (32) to (38)
The AD terminal is connected to a control output terminal of the decoder (40) and is controlled according to mode selection data supplied to a mode selection bit terminal of the decoder (40). That is, F.F.
Control signals supplied to the U/D terminals of the circuits (32) to (38) determine whether the counter circuit (16) counts up or counts down during a counting operation. Furthermore, when the control signal supplied to the LOAD terminal becomes active, the FF circuit (32)
The data DO supplied to the data input terminal of ~(38)
~D3 is loaded. The /C output terminals of the FF circuits (32) to (38) become 0 when the Q output is 1 when the counter circuit (16) performs a count-up operation, and the Q output when the counter circuit (16) performs a count-down operation. When the terminal is O,
It becomes 0.

The two inverting input terminals of the NAND gate (42) are connected to the /TOGOLE output terminal and the bit enable input terminal /ENO of the decoder circuit (40), respectively. The NAND gate (42) outputs 0 only when both input signals are O, enabling the FF circuit (32) to count. The inverting input terminal and non-inverting input terminal of the NOR gate (44) are connected to the /C terminal and the bit enable input terminal /ENO of the FF circuit (32), respectively. The three inverting input terminals of the NAND gate (46) are connected to the /TOGOLE output terminal of the decoder circuit (40), the output terminal of the NOR gate (44) and the bit enable input terminal /ENI, respectively. Nando Gate (46) is
Only when all three input signals become 0, 0 is output and the FF circuit (34) is enabled for counting. The inverting input terminal and non-inverting input terminal of the NOR gate (48) are connected to the /C output terminal and the bit enable input terminal /ENI of the FF circuit (34), respectively. The four input terminals of the NAND gate (50) are connected to the decoder circuit (40).
/TOGOLE output terminal, output terminal of NOR gate (44), output terminal of NOR gate (48) and bit
Connected to enable input terminal /EN2. The NAND gate (50) outputs 0 and enables the FF circuit (36) only when all four input signals become 0.

The inverting input terminal and non-inverting input terminal of the NOR gate (52) are connected to the /C output terminal and bit enable input terminal /EN2 of the FF circuit (36), respectively. Nando
The five inverting input terminals of the gate (54) are connected to the /TOGOLE output terminal of the decoder circuit (40), the NOR gate (4
4), the output terminal of the NOR gate (48), the output terminal of the NOR gate (52), and the bit enable input terminal /EN3. Nando Gate (5
4) only when all five input signals become 0,
Count and enable the FF circuit (38).

In FIG. 5, mode selection data to the decoder (40) holds the /TOGGLE output at O and /ENO1/E
The operation timing is shown when 0 is supplied to NI and /EN2, 1 is supplied to /EN3, and the lower 3 bits are enabled for counting to perform a count up or count down operation.

Each operation can be easily understood from FIG. 5. Also, in the counting operation, when a carry signal is supplied to the carry terminal /CARRY, /T.

GOLE becomes O and the counter circuit (16) increases or decreases by l.

[Effect] According to the present invention, the value of the second counter circuit changes in the next cycle when the value of the first counter circuit reaches the limit value of the desired area, and the upper bit group of the first counter circuit is
After the first address location is loaded, it holds the loaded value, so as the second counter circuit changes,
The first counter circuit returns to its initial value. Therefore, in the next cycle when the value of the first counter circuit reaches the limit value,
There is no need to load the initial value of the first counter circuit.

Therefore, a dummy cycle due to a load operation does not occur, and ALυ for adding an offset amount from address zero is not required.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an address information generation device for realizing the address information generation method of the present invention, FIG. 2 is a simplified diagram showing an equally divided memory area, and FIG. 3 is a block diagram showing the address information generation device of the present invention. 4 is a circuit diagram showing the configuration of the counter circuit of FIG. 1, FIG. 5 is a timing diagram showing the operation of the counter circuit, and FIG. 6 is a timing diagram showing the operation of the counter circuit of FIG. 1. FIG. 2 is a circuit diagram showing a specific configuration of a carry signal generator in the device. In the figure, (16a) and (16b) are respectively X
and a Y-axis counter circuit.

Claims (1)

[Scope of Claims] An address information generation method for specifying an address for a desired area among a plurality of equally divided areas of a memory area, the method comprising: first and second address information for generating first and second address information, respectively;
a first step of dividing a plurality of bits of at least a first counter circuit among the counter circuits into an upper bit group indicating the position of the plurality of equally divided areas and a lower bit group indicating the address position within the area; a second step of loading the addressing start address of the desired area into the first and second counter circuits; a third step of enabling only the lower bit group of the first counter circuit to perform a counting operation; a fourth step of changing the value of the lower bit group of the first counter circuit and changing the value of the second counter circuit when the value reaches a predetermined boundary value of the desired area; An address information generation method characterized in that the fourth step is repeated until all address positions of the address information are specified.