JPH0476510B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an optical integrated device, and more particularly to a semiconductor device in which a pin host diode and a field effect transistor are integrated.

[Background of the invention]

Miura et al., Spring 1981 Applied Physics Conference Lecture Proceedings
7P-I-10 has n ⁺ grown on a GaAs semi-insulating substrate.
- It is described that a GaAs conductive layer constitutes a pin type photodiode section and a field effect transistor (FET) section. But with this structure
Since there is an n ⁺ layer with relatively low resistance under the FET, parasitic capacitance is generated in the FET section, which may result in deterioration of frequency response characteristics.

Structures that have improved this point are Hamaguchi et al. 1981 Autumn Conference of Applied Physics Conference Proceedings 12a-N-7 and Miura et al.
Since there is no n ⁺ layer in the FET section, the frequency response characteristics are improved. However, since this results in a structure with steps, there is a possibility that the precision of lithography necessary for FET fabrication may be impaired. Additionally, the wiring for connecting the pin photodiode section and the FET section runs over a step, so there is a possibility of disconnection.

In addition, in both of the above-mentioned methods, thermal diffusion of p-type impurities is used to form the p ⁺ region, so
The controllability of the diffusion depth of thermal diffusion is poor, and the in-plane distribution is highly non-uniform. Furthermore, lateral diffusion, which is often seen in thermal diffusion, causes an increase in the pn junction area, resulting in an increase in the junction capacitance of the pin photodiode and a decrease in frequency response.

Although these methods can be effectively utilized when the transmission speed is less than 1 Gb/sec, it is estimated that it is difficult to put them into practical use at high-speed transmissions of 1 Gb/sec or higher.

[Purpose of the invention]

The purpose of the present invention is to reduce the parasitic capacitance in the FET section and to flatten each surface within the element to facilitate microfabrication in manufacturing a photodetector in which a pin-type photodiode and a field effect transistor are integrated. It is an object of the present invention to provide a structure that can improve the yield of device fabrication and improve frequency response characteristics by easily forming a p ⁺ region of a pin host diode by implanting ions of a nuclide serving as a p-type impurity.

[Summary of the invention]

In the present invention, by utilizing the property of burying the trench and flattening it, which is unique to the liquid phase growth method, after forming an n ⁺ layer in the trench, filling the trench and forming a
The highly purified light absorption layer, which is essential for the production of pin photodiodes, is used as the buffer layer or ion implantation layer of the FET in the preamplifier. That is, first, a groove is formed in the substrate, an n ⁺ layer is formed only in the groove, and then an i layer is formed flatly on the entire surface by liquid phase growth method so as to bury it, and then on this surface. Form a high purity light absorption layer. The integrated light receiving device manufactured in this manner has a flat structure that is advantageous for microfabrication. In this structure, if the reproducibility of manufacturing the p ⁺ region of the pin photodiode is improved, higher performance and reliability of the device can be achieved.
For this purpose, we formed a p ⁺ region by ion implantation to improve the diffusion depth distribution seen in thermal diffusion, and the depth of the p ⁺ region could also be controlled to be as thin as 0.1 μm, making it suitable for manufacturing p electrodes. It has also been found that a highly concentrated layer can be formed.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

Example 1 This will be explained using FIG. 1. A groove 25 is formed in advance in the GaAs semi-insulating substrate 1, and n ⁺ −Ga _x
After Al ₁ − _x As (0<x≦0.5) layer 2 and n ⁺ -GaAs layer 3 are grown by liquid phase epitaxial growth, vapor phase growth, etc., layers 2 and 3 remain only inside the groove. Microfabrication is performed as shown in the figure. Next, high purity i-Ga _y
The Al ₁ − _y As (0<y≦0.5) layer 4 and the i-GaAs layer 5 are grown by liquid phase epitaxial growth so that the grooves are filled and flat layers 4 and 5 are formed. The FET active layer 14 to be formed on the surface of the planarized semiconductor layer is prepared by ion-implanting an n-type impurity nuclide into the i-GaAS layer 5, and then a region into which a p-type impurity nuclide is implanted. 6 as the light receiving surface of the pin host diode. Subsequently, a source 8, a drain 10, and an ohmic electrode for the p-electrode of the photodiode are formed, and then an insulating film 7 is formed. Openings are made in desired areas of this insulating film. Furthermore, gate 9
The shot key electrode and internal wiring 11 of the photodiode are fabricated by vapor deposition, and the n electrode 13 of the photodiode is etched from the back side into a via hole type ^.
After exposing up to Ga _x Al ₁ - _x As (in the figure, 12 indicates this hole), an electrode metal is deposited on the entire back surface. In addition, the photodiode and
It is sufficient to manufacture the FET section itself using conventional manufacturing methods. According to this example, the parasitic capacitance in the FET section is reduced, the frequency response characteristic is improved by flattening the element surface, and the pn of the host diode is improved by using ion implantation to form the p ⁺ region. This has the effect of improving the characteristics of the junction and improving the frequency response characteristics. Furthermore, the use of a via-hole type has the effect of reducing the series resistance of the host diode and improving frequency response characteristics.

Example 2 This example is an example in which a window layer is provided on a photodiode.

This will be explained using FIG. As in Example 1, i
- After forming the GaAs layer 5, an i-Ga _z Al ₁ - _z As window layer (0<z<0.5, y<z) 22 is formed, and a part of this window layer 22 is ion-implanted with p-type impurities. A p + region 6 was formed by adding a p ⁺ region. In this case, since the depth of ion implantation can be controlled by the thickness of the window layer 22, a stable device can be manufactured with high yield. The method for forming the n ⁺ GaAs layer is the same as in Example 1.

Example 3 In this example, the n-electrode 13 is formed using a method different from those in Examples 1 and 2.

This will be explained using FIG. A cross section of the device is shown in FIG. 3, but the n-electrode 13 is difficult to illustrate because it is located in front of and/or on the opposite side of the n ⁺ -GaAs layer. Therefore, this is illustrated by showing a sectional view taken along line A-A' in FIG. 4. The n-electrode is provided on the top of the semiconductor layer 4 for planarization and taken out to the outside. However, only one location of the n-electrode 13 is illustrated. It goes without saying that two or more locations may be provided as necessary.

Example 4 This example illustrates another way of drawing out the n-electrode 13.

This will be explained using FIGS. 3 and 5.

FIG. 5 is a sectional view taken along line A-A' in FIG.

The configuration of the n-electrode 13 is different from Example 3,
An n ⁺ GaAs layer was formed across the device, and an n electrode 13 was formed on the sidewall thereof. Only one side of the n-electrode 13 may be provided.

Example 5 FIG. 6 is a cross-sectional view of a device according to this example, in which the n-electrode 13 is
This is a case where the same as in Example 3 or 4 is applied.
(The cross-sectional view taken along line A-A' is omitted because it can be estimated from FIG. 4 or FIG. 5.) Example 6 This will be explained using FIGS. 7 and 8.

An example will be shown in which an active layer (n-channel layer) 15 separate from the semiconductor layer 5 for forming a photodiode of an FET is manufactured by epitaxial growth. FIG. 7 is a cross-sectional view of the device according to the embodiment. For example, the first
This is similar to the example in the figure.

FIG. 8 shows the case where the n-electrode 13 is formed by the method of Example 3 or Example 4, and the sectional view taken along line A-A' is omitted since it can be estimated from FIG. 4 or FIG.

In the above Examples 1 to 6, the two layers, the i-Ga _y Al _1-y As layer and the i-GaAs layer for embedding, were made highly purified (1×10 ¹⁴ cm ^-3 or less) by liquid phase epitaxial growth. (impurity concentration), and other growth layers 2,
Nos. 3, 15, 20, 22 and 23 are fabricated using general growth methods including liquid phase epitaxial growth to increase the impurity concentration of the n ⁺ layer to a high concentration (≧5×
10 ¹⁷ cm ^-3 ), and the high purity layer can have an impurity concentration of 1×10 ¹⁴ cm ^-3 or less. Further, it is desirable that the impurity concentration in the p ⁺ region is as high as 5×10 ¹⁸ cm ⁻³ or more.

〔Effect of the invention〕

According to the present invention, when a preamplifier consisting of a pin photodiode and a magnetic field effect transistor is integrated, not only the frequency response characteristics can be improved, but also the characteristics of the p ⁺ region of the photodiode are improved, making the device highly reliable. It has a measurable effect.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of the device shown in Example 1, FIG. 2 is a cross-sectional view of the device shown in Example 2, FIGS. 3 and 4 are cross-sectional views of the device shown in Example 3, and FIG. 5 is a cross-sectional view of the device shown in Example 3. 4, FIG. 6 is a sectional view of the device shown in Example 5, and FIGS. 7 and 8 are sectional views of the device shown in Example 6. 1; Semi-insulating GaAs substrate, 2; n ⁺ −Ga _x Al ₁ − _x
As layer (0<x≦0.5), 3; n ⁺ -GaAs, 4; i-
Ga _y Al _1-y As layer (0<y≦0.5), 5; i-GaAs light absorption layer, 6; p ⁺ region, 7; insulating film, 8; source,
9; gate, 10; drain, 11; internal wiring,
12; via hole, 13; n electrode, 14;
Ion implantation region of FET, 15; n-channel layer of FET, 20; n ⁺ -GaAs layer, 22; i-Ga _z Al ₁ -
_z As window layer (0<z≦0.5), 23; i-GaAs cap layer.

Claims (1)

[Claims] 1. A semiconductor device in which a pin-type photodiode and a field effect transistor used as a preamplifier are monolithically integrated on a semiconductor substrate,
a first semiconductor layer having a groove in a portion of the semiconductor substrate where a photodiode is to be formed; an n ⁺ layer in the groove; and a first semiconductor layer having a flat surface on top of the groove; 1. A semiconductor device comprising: a second semiconductor layer formed by a semiconductor device; the photodiode and a preamplifier are provided in the second semiconductor layer. 2. The semiconductor device according to claim 1, wherein the second semiconductor layer is composed of a plurality of layers. 3. The semiconductor device according to claim 2, wherein the second semiconductor layer is composed of a plurality of layers, and the photodiode and the preamplifier are provided in different layers of the plurality of layers. . 4. A method for manufacturing a semiconductor device in which a pin type photodiode and a field effect transistor used as a preamplifier are monolithically integrated on a substrate, at least the step of forming a groove in the position of the pin type photodiode on the substrate; in the groove
a step of forming an n ⁺ layer, a step of filling the groove using a liquid phase growth method to flatten the surface of the substrate, a step of forming one or more semiconductor layers on the surface of the substrate, a step of forming a predetermined layer on the semiconductor layer, 1. A method of manufacturing a semiconductor device, comprising the steps of forming a photodiode and a preamplifier.