JPH04759A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To enable this semiconductor memory to operate from a 5V single power supply by a method wherein memory cells are arrayed in a matrix, drains of memory transistors are connected to a bit line, gates to a word line and sources to a source line and a capacity is formed on each bit line. CONSTITUTION:Drains of memory cells 13 are connected to a bit line 15 and gates to a word line 14 and sources to a source line 16. A capacity 18 is connected to the bit line 15 and a signal PHI is input to the other electrode of the capacity 18. When writing in the memory cells 13, an I/O line is set at 'H' level and a Y gate 5 selected by a Y decoder 6 is turned on and a voltage of the selective word line is raised. Then, a signal PHI is set at 'H' level with a signal CLK1 at 'L' level. After a voltage of the bit line 15 is raised by capacity coupling, the signal CLK1 is set at 'H' level and the source line 16 is grounded. Writing is possible with a 5V single power supply by repeating a cycle of voltage rise of the bit line 15 by the capacity and the grounding of the source line 16.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a writing method for electrically writable nonvolatile semiconductor memory devices IP'ROM and flash EEPROM.

[Prior Art] Fig. 4 is a block diagram of a conventional flash EEPFIOM shown in the 1988 EEE 15SCC Digest of Technical Babers, page 132, and Fig. 5 is a cross-sectional view of the memory cell shown in Fig. 4. In the am diagram,
The memory array (1) has memory cells (13) shown in FIG.
) are arranged in the row and column directions, and the drain (2) of the memory cell/' (13) is connected to the bit line (22) K,
Connected to (23) (23). Word & 1 (23)
is the output of the X decoder (4). The bit line (22) is connected to the Y gate (5). The Y gate (5) is controlled by the Y decoder (6) and controls the connection between the bit line (22), a sense amplifier (not shown), and a write buffer (not shown).

The X decoder (4) and Y decoder (6) receive the output of the address buffer (7) and output one O7-)'M (23), 1
Select m(D Y '1-[5). Data written to the memory array (1) and data read from the memory array (1) are input and output via an input/output buffer (8). Furthermore, a command register (9) and a write/read control circuit (10) are provided. When in the command input state, the command register (9) sends a signal indicating the operating mode of the chip to the write/read control circuit (10) according to the input data. Write/read system a
The circuit (lO) performs chip write/read operations in response to signals sent from the command register (9).

Next, the operation will be explained. Data stored in the memory array (1) is erased all at once. A high voltage is applied to the sources (11) of all memory cells (13), and the control gates (3) are grounded.

Since a high electric field is applied to the oxide film between the floating gate (12) and the source (11), a tunnel current flows and the electrons accumulated in the floating gate (12) are removed. This lowers the threshold value of the memory transistor as seen from the control gate (3). That is,
In FPROM, the state becomes □゛, which is the same as the state after being erased by ultraviolet light. After the erase pulse is applied, the memory array (11
data is read out, and if erasing is insufficient, erasing is repeated. At this time, the erase pulse @ is the command register (
9) after the erasure code is input until the erasure confirmation code is input. That is, it is controlled from the outside.

Writing is performed in the same way as in EPROM, and the drain (2) and control gate (31) of the memory transistor are
A K high voltage pulse is applied and the source (11) is grounded.

Electrons generated by Apafunsier decay near the drain (2) are injected into the floating gate (12), and the threshold of the memory transistor as seen from the control gate (3) becomes high. The high voltage necessary for erasing and writing is supplied externally. This will beep when writing) @ (
This is because the current flowing through 22) is 1 mA to 5 mA, so a high voltage generating circuit such as a charge pump has insufficient current supply ability.

[Problems to be Solved by the Invention] Since the conventional flash EEPROM is configured as described above, there is a problem in that it requires a high-voltage power supply with a relatively large capacity for erasing and writing.

The present invention has been made to solve the above-mentioned problems, and a first object of the invention is to obtain a nonvolatile semiconductor memory device that operates with a single 5V power supply. Furthermore, the second
An object of the invention is to obtain a nonvolatile semiconductor memory device in which the capacitance value connected to the bit line is reduced by boosting the signal applied to the capacitance.

"Means for Solving the Problems" The flash EEPROV according to the first invention provides a capacitor for each bit line, charges the selected bit line, applies a signal to the other ! pole of the capacitor, boosts the voltage of the bit line, and then charges the selected bit line. The source line is grounded to cause Apafunsier collapse near the drain.Furthermore, in the second invention, the signal applied to the capacitor is configured to be boosted.

[Effect]

In the first invention, the nonvolatile semiconductor memory device according to the present invention boosts the voltage of the bit line by a capacitor provided for each bit line and operates with a single 5V power supply.

Furthermore, in the second invention, the capacitance value can be reduced by increasing the voltage applied to the capacitor.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a nonvolatile semiconductor memory device according to the first invention, and FIG. 2 is a block diagram of a nonvolatile semiconductor memory device according to the second invention. In the figure (4), (6)
, (13) are the same as those shown in the conventional example shown in FIGS. 4 and 5, so their explanation will be omitted. 1 shown in Figure 1.
In the invention, the drain of the memory cell (13) is connected to the bit line (15), the gate is connected to the word M (14), and the source is connected to the source line (16).

The source line (16) is grounded via a transistor (17) whose gate receives the signal CLKI. Bit line (
A capacitor (18) is connected to the capacitor (15), and a signal - is applied to the other electrode of the capacitor (18). (5) is a Y gate, (
20) is the I10 line.

Next, the operation of the Ume memory cell (13) will be explained with reference to FIG.
) if you want to write to 101JA (20)
level is set to "H" (power supply voltage level), and the Y gate (5) selected by the Y decoder (6) is turned on.

Furthermore, after boosting the selected word line, the signal CLKI
is set to "1', the signal - is set to "■", and the bit line (15) is boosted by capacitive coupling. After that, CLKI is set to "H" and the source line (16) is grounded. At this time, the bit line ( 15) to the source line (16) to the memory cell (13)
A current flows through the gate, and electrons are injected into the floating gate by avalanche injection. This bit line (15
) By repeating the cycle of boosting the voltage using the capacitor and grounding the source line (16), writing using a single 5V power supply becomes possible.

Next, the second invention shown in FIG. 2 will be explained.

In the figure, the drain of the memory cell (13) is connected to the bit line (1
5), the gate is the word line (14), the source is the source line (
16) respectively. The source line (16) is connected to a transistor (17) whose gate receives the signal CLKI.
). The bit line (15) has a capacitance (1
8) is connected, and a booster circuit (21) is applied to the other electrode of the capacitor (18). A signal - is applied to the booster circuit (21) via a transistor (19) to which a power supply voltage is applied to the gate. The external pressure circuit shown in FIG. 2 is an example, and is composed of two stages of inverters and a P-channel transistor. (5) is Y game), (20) is l10jI
Ii! It is.

Next, the operation will be explained with reference to FIG. Memory cell (13
), set the level of the I10 line (20) to “R” (power supply voltage level) and write to the Y decoder (6
) is selected by Y gate (5) t is turned on. Furthermore, the selected word line is boosted. Next, the signal CL K'
With l set to °L", the signal - is set to "■" and the booster circuit (
21) boosts the signal applied to the capacitor (18).

As a result, external pressure is applied to the bit line (15) due to capacitive coupling. After that, set CL K, 1 to ° and source # (16
) to ground. At this time, the source Ji from the bit line (15)
A current flows through the memory cell (13) in 1i1 (16), and electrons are injected into the floating gate by reapalance injection. The capacity of this pipe) M (15) (18
), and by repeating the cycle of grounding the source M (16), it becomes possible to write with a single 5V power supply.

Note that in the embodiment of the first invention, I
I explained the case where 10 wires (20) are shared, but
As in another embodiment of the first invention shown in FIG.
18) may be divided for each I10 line (20).

"Effects of the Invention" As described above, in the first invention, a capacitor is provided for each bit line, and the bit line is boosted by this capacitance so that avalanche injection occurs near the drain of the memory cell. This has the advantage of operating on a power supply.Furthermore, in the second invention, by boosting the voltage of the signal applied to the capacitor, there is an effect that the value of the capacitance connected to the bit line can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a nonvolatile semiconductor memory device according to an embodiment of the first invention, FIG. 2 is a block diagram of a nonvolatile semiconductor memory device according to an embodiment of the second invention, and FIG. 3 is a block diagram of a nonvolatile semiconductor memory device according to an embodiment of the second invention. 4 is a block diagram of a conventional flash EEPROM, and FIG. 5 is a cross-sectional view of the memory cell shown in FIG. 4) is an X decoder, (5) is a Y gate, (6) is a Y decoder, (13) is a memory cell, (
14) is a word line, (15) is a bit line, (16) is a source line, (17) and (19) are transistors, (18) is a capacitor, (20) is a 10-wire wire, (21) is an external pressure In the diagrams, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) Memory cells formed by memory transistors having floating gates are arranged in an array in the row and column directions, and the drains of the memory transistors are bit lines, the gates are word lines, and the sources are source lines. A nonvolatile semiconductor memory device characterized in that the bit line is connected to the bit line and a capacitor is formed in each bit line.