JPH0475143A - Processor with task switching function - Google Patents

Abstract

PURPOSE:To eliminate subordination between continuous instructions and to prevent register hazard occurring by inputting an independent instruction from another register to the instruction whose execution is being started at present by switching a task when the instructions unexecutable successively and set in the subordination mutually are detected in a processor made into a pipeline. CONSTITUTION:Plural instruction buffer means 1, an instruction decoder means 2, a task switching control means 3, an address conversion means 4, a register block 5, and plural arithmetic processing blocks 6 are provided. The instruction decoder means 2 is provided with a circuit which discriminates whether or not the instruction performing decoding at present can execute the continuous instructions with the same task as that of the instruction, and the task switching control means 3 sets a state so as to always execute a task switching operation when the next instruction with the same task is unexecutable. Thereby, it is possible to accelerate pipeline processing by reducing irregularities in the pipeline as possible, and to easily apply synchronism between the tasks when plural tasks are executed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a processor with a task switching function, and more particularly to a processor that is a type of high-performance processor and sequentially processes a plurality of tasks in a pipeline manner.

(Prior Art) Pipeline configurations have been very commonly used as a means of speeding up processors such as CPUs in computer systems. In general, in a pipeline configuration, one large process is divided into multiple processing elements, and each processing element executes new instructions one after another within the required time, that is, at the pipeline pitch, making it possible to greatly increase throughput.

Figures 5 (a) to (C) each show the pipeline processing method, where (a) is conventional sequential processing, (b) is ideal pipeline processing, and (C) is actual Vibration processing. In the figure, AlB, C, and D are instructions and Ts, respectively.
is the processing time for sequential processing, Tp is the time for ideal pipeline processing, Tpo is the processing time for realistic pipeline processing, and Δ is the pipeline pitch.

As is clear from Fig. 5, when executing consecutive instructions A, B, C, and D, the processing time Ts of the ideal Vibration processing is longer than that of the most primitive sequential processing. The processing time Tp has a value close to 1/N, where N is the number of pipeline division stages.

(Issue 8 to be solved by the invention) However, in order to realize the ideal pipeline processing as described above, each instruction A, B, and C must be processed separately.

Each D must be independent, but in reality, for example, the execution results of instructions A and C are used to create instruction B.

Situations such as when D is able to start occur frequently and the vibration line is disturbed. FIG. 5(C) shows a time chart of instruction execution in such a case, in which the total processing time: 'rp' is larger than the ideal processing time: Tp, but rather the sequential processing time. : Becomes close to Ts.

On the other hand, in recent years, multiprocessor systems have begun to be developed in which a processor is assigned to each task in order to process multiple tasks (a unit of processing that is a single instruction sequence) at high speed. In these systems, the instructions that are executed simultaneously on each processor are usually mutually independent, but sometimes it becomes necessary to execute dependent instructions between tasks, or there is a need to synchronize between tasks. However, in conventional systems, such processing could not be easily realized.

In view of the above, the present invention aims to reduce pipeline disturbances in pipeline processing in a processor system as much as possible, speed up pipeline processing, and facilitate synchronization between tasks when multiple tasks are executed. The purpose is to provide a processor configuration that allows for

(Means for solving the problem) In order to achieve the above object, the invention of claim (1):
A plurality of instruction buffer means each storing a part of a task which is a plurality of types of instruction sequences, and an address of the next instruction to be executed in each task, and when the instruction is actually executed, the value is changed. A program counter means which is updated and further holds the next instruction address, and outputs from each of the instruction buffer means are selectively taken in and sequentially decoded, and based on the decoding result, it is determined whether the next instruction to be executed is executable or not. an instruction decoding means that outputs a check signal indicating the instruction; and a task selection signal, which is information on the next task to be selected, based on the check signal from the instruction decoding means and internally set switching algorithm information for each task. a task switching control means for generating an actual register number by synthesizing a task selection signal from the task switching control means and a temporary register number output from the instruction decoding means; A register block that is capable of accessing the memory portion at the register number position by inputting a register number and writing data from or reading data to the internal bus; and a register block that is connected to the internal bus and that performs arithmetic processing on the data. The instruction decoding means includes a determination circuit that determines whether or not the instruction currently being decoded can execute consecutive instructions of the same task, The switching control means is configured to include a control circuit configured to perform a task switching operation whenever the next instruction of the same task cannot be executed due to a check signal from the instruction decoding means. be.

In addition, the invention of claim ('2J) realizes the same functions as a multiprocessor system with one processor, so in addition to the structure of claim (1), the invention also includes a processor that can input and output multiple data series in parallel. a data input/output port, a data switch means for connecting each data input/output port and a register block in response to a task selection signal from the task switching control means, and a plurality of data switch means connected to each of the plurality of instruction buffer means. This adds a configuration having a command input port.

In addition, the invention of claim (3) provides a method for specifying synchronization between a plurality of tasks and the execution order of arbitrary instructions between tasks.
In addition to the structure of claim (1) or ('2J), the instruction decoding means includes a strength counter that stores or updates the strength of the command, and a strength counter that is included in a part of the command code or as an independent non-execution/control code. a memory circuit that extracts and stores strength information present in each instruction sequence; a comparison circuit that compares the strength of the strength counter with the strength information of the memory circuit; and as a result of comparison by the comparison circuit, it is found that the strength counter is strength memory determination means comprising an output circuit that outputs a lock flag signal when the strength is high; and upon receiving the lock flag signal, locks execution of an instruction accompanied by strength information in an arithmetic processing block and stores the strength information. The program counter is provided with the same number of lock instruction buffer memories as the number of tasks and has a function of temporarily storing accompanying instructions, and the program counter is provided corresponding to each task and receives a lock flag signal from the output circuit. This adds a configuration that has a function to stop updating to the next instruction address.

Furthermore, the invention of claim (4) provides a method for easily controlling when various data processing instructions are requested from a plurality of tasks and storage of each result data in a register occurs at a complicated timing. The configuration according to claims (1) to (3) is provided with a register section of a multi-input/output port capable of independently executing at least writing and reading, and the arithmetic processing block has a multi-stage vibe line configuration, and each vibe line configuration has a plurality of stages. A shift register having a bit width sufficient to specify the register number and type of arithmetic processing block, a manual buffer memory having the same bit width as the data input section of each stage of the shift register, and a shift register having a bit width sufficient to specify the register number and type of arithmetic processing block; a status flag section indicating the state of the shift register, that is, empty, in use, or on standby, and an operation control means for determining the type of operation of each stage of the shift register according to the value of the status flag indicated by the status flag section; input position control means for inputting a destination register number for storing each arithmetic processing result output from the instruction decoding means into an appropriate stage number position of the shift register according to the number of vibe line stages required for the arithmetic processing; This is an additional configuration.

(Operation) According to the structure of the invention of claim (1), when instructions in a mutually dependent relationship that cannot be executed consecutively are detected in the vibe line, the task is switched and an instruction that is independent of the instruction currently being executed is detected. Bringing instructions from another task.

Further, according to the configuration of the claimed invention, with the configuration having a plurality of data input/output ports and instruction manual ports described above, simultaneous input/output of data and simultaneous input/output of instructions is possible, which is equivalent to a multiprocessor system. Execute processing.

Further, according to the configuration of the invention of claim (3), the strength of the code in the instruction sequence of each task is detected by the configuration consisting of the above-mentioned strength counter, lock instruction buffer memory, and strength memory determination means, and the current strength of the processor is detected. If the strength is higher than that, execution continues, and if it is lower, execution is stopped, thereby achieving synchronization between tasks.

Furthermore, according to the structure of the invention of claim (4), by the structure having the above-mentioned shift register section with input buffer memory,
The timing of the data write operation to the register of the destination operand written in the same instruction can be adjusted by appropriately selecting the input position to the shift register.

(Embodiment) FIG. 1 shows a first embodiment of the present invention, in which (1) is a plurality of instruction buffer means, in which a queue of instructions of a plurality of tasks is stored. Stored.

In addition, in FIG. 1, (2) is the instruction buffer means (
This is an instruction decoding means that selectively inputs and decodes one of the instructions in 1) and sends a control signal for executing the instruction to each block inside the processor. However, if two instructions are executed consecutively in the same task, a flag may be set in advance for part of the first instruction code that would disrupt the vibe line operation. This flag can be used, e.g.
C4-A+B...■ When executing consecutive instructions such as E←C-D...■, before the value of C, which is the addition result in ■, is determined. ■The instruction cannot be started (usually called register hazard)
However, with a little ingenuity in the assembler, compiler, etc., it is easy to detect that the ■→■ sequence causes a register hazard, and it is easy to set a flag in the instruction code for ■. .

The instruction decoding means (2) detects the flag and generates a check signal for continuous instruction execution, and also outputs the register number at the same time when an internal register is used as an operand of the instruction. However, it is highly likely that this register number is a uniquely determined number within the same task, or that the same number is also used in another task. Therefore, this register number is temporary, and the actual register number, together with the task number, is determined by the address conversion means (described later).
4).

Further, in FIG. 1, (3) is a task switching means, which performs task switching by integrating a check signal from the instruction decoding means (2) and an internal switching algorithm. In this case, the following method is a specific example of a method of assigning priority to each task and switching between them.

That is, 4°3, 2 for tasks a, b, c, and d.
．． It assigns a priority of 1 (the larger the number, the higher the priority) and starts execution from a.

The task switching control means (3) immediately switches the task to task b when a check signal is generated in the instruction decoding means (2), and also determines the number of consecutively executed instructions of task a even when no check signal is generated. Even when there are 4 units, the task is switched to b.

The instruction execution of task b is similarly switched to task C when a check signal is generated or when the number of consecutively executed instructions of task b reaches 3 units. Thereafter, task C is switched to task d1 and task d is switched again to task a.

FIG. 6 shows the hardware configuration of the task switching control means (3) for realizing the above-mentioned operation. In the figure, (31-1) to (31-5) are counters,
(32) is a decoder, (33) is an OR circuit, (34) is an AND circuit, (35) is a system basic clock, (36)
) is a check signal, (37) is a task selection signal, (38
) is a task switching pulse.

As shown in Fig. 6, prepare the same number of counters (31-1) to (31-4) as the maximum number of tasks handled by the processor, and initialize these to the same value as the priority of the corresponding task. put. In addition, each counter (31-1) to (31-
The system basic clock (35) corresponding to the vibration line pitch is input to the clock input of 4), and each counter (
311) to (31-4) are always kept in a counting state. However, the task switching pulse (38) is the counter (31-
Since it is input to the S terminals of 1) to (31-4), all counters (
31-1) to (31-4) are reset to restart counting from 0.

On the other hand, the currently executing task is displayed in another counter (31-5).
It is indicated by the output Ch and Q2, and is counted by the task switching signal, and the tasks are switched one after another. Then, the output Q+ of another counter (31-5),
Since Q2 is usually binary encoded, the decoder (3
2) by a, b.

It is decoded into individual signals for each task c and d and output.

The task switching pulse (38) is an AND of the count end signal E of the counters (31-1) to (31-4) corresponding to each task and the corresponding task selection signal (37).
and the check signal (36) sent from the instruction decoding means (2). In other words, when the count end signal E of the task currently being executed or the check signal (36) arrives, the task is switched to the next task, where the counter (3) for each task is newly set.
1-1) to (31-4) start counting from 0 to a value corresponding to the priority of the task.

In FIG. 1, (4) is task switching control means (3)
The address conversion means generates an actual register number by combining the task selection signal from the instruction decoding means (2) and the temporary register number output from the instruction decoding means (2), and the address conversion means (4) is, for example, Translation in a processor that supports a virtual memory system
Lo.

It can be realized with the same configuration as a kaside buffer (TLB).

In FIG. 1, (5) is a register block means, and upon input of the actual register number, the register block means (5) accesses the storage part at the register number position and receives data from the internal bus. Data can only be written to or read from the internal bus.

As shown in FIG. 1, the signal converted into an actual register number by the address conversion means (4) is supplied to the address decoder (5-1) of the register block (5).
The register storage section (5-2) is accessed to perform register reading and writing operations. The data output from the register block (5) is then transferred to the internal bus (7).
) is supplied to the arithmetic processing block (6) for arithmetic processing, and the result is usually written to the register block (5) again via the internal bus (7).

The example of the arithmetic processing block (6) in FIG. 1 shows a configuration in which two-stage pipeline processing is executed inside the arithmetic processing block (6). The first stage of the processor, (6-2) is an intermediate latch that holds intermediate results, (6-3) is the second stage of the arithmetic processor, (6-4)
is a tag that holds the final result.

In FIG. 1, (8) is a program counter means indicating the address of the next instruction to be executed after each task,
The program counter means (8) stores the address of the instruction to be executed in each task, and as the instructions of each task are executed, the value of the corresponding program counter is updated, and the updated address is held. . Further, when a branch instruction or the like is executed, the value of the program counter is converted into a jump destination number, as in the conventional case.

The instruction decoding means (2) includes a decoder circuit for decoding instructions of a normal processor, a selector circuit for selecting a task in the input section, and an instruction successive execution possibility detection section and check signal generation as an additional part of the decoder circuit. Consists of circuits.

FIG. 2 shows a second embodiment of the present invention, and the configuration of this second embodiment includes, in addition to each component of the first embodiment,
a plurality of instruction input ports (11) that are connected to each of the instruction buffer means (2) and input independent instructions for each task from outside the processor; and a plurality of independent data that can input and output a plurality of data series in parallel. Input/output port (1
2), and data switch means (2) for connecting the data input/output port (12) and the register block (5) in response to a task selection signal from the task switching control means (3).
13) is added. With this configuration, the conventional multiprocessor system is equivalently replaced with one processor.

FIG. 3 shows a third embodiment of the invention.

In this third embodiment, when ordering the execution of instructions between tasks or synchronizing tasks, strength information is assigned to each instruction in advance, and instructions that do not require synchronization are given the strongest strength. This is done by setting the discrimination strength of the processor itself one rank lower than that in the strength counter (2-3). For example, if the instruction Xd of task d is executed first, then the instruction Yc of task C, then the instruction zb1 of task b, and then the instruction Wa of task a,
Xd intensity is 4, Yc intensity is 3, zb intensity is 2, W
Set the strength of a to 1 and the initial strength of the processor to 4.

The strength memory determination means (2-2) includes a memory circuit that stores a portion including strength information of each instruction, and the strength counter (2-2) described above.
The strength flag signal of the processor output from 2-3) (
2-4), a comparison circuit for comparing the strength of each instruction, and a next strength generation output circuit, and the strength memory determination means (2-2)
(a) When the instruction strength is greater than or equal to the processor strength, the next strength generation circuit calculates a value obtained by subtracting 1 from the instruction strength value, and this is again sent to the strength update signal (2-
5), return it to the strength counter (2-3) and set it to that value, and conversely, (b) if the processor strength is stronger than the instruction strength, the remaining part except the strength information of that instruction is set to the lock instruction. It is stored in the buffer memory (2-1), locks execution of instructions in the arithmetic processing block (6), also stops the program counter (8) of the corresponding task, and issues a check signal for task switching.

For example, if zb is first supplied to the instruction decoding means (2) of the processor, the strength of the processor is 4 and zb
The intensity of is 2 and corresponds to case (b), so Z
b is temporarily stored in the strength memory determining means (2-3), lock instruction buffer, and memory (2-1) corresponding to task b, the corresponding program counter (8) is stopped, and the task is switched to C. Next, when instruction Xd arrives, this time it is case (a), so Xd is executed as is,
Furthermore, the processor strength is updated from 4 to 3 by the strength memory determining means (2-2). Next, when Wa arrives (b
), Wa also becomes locked and the task is switched to task b, but since task b is locked, further task switching occurs and task C is switched. When instruction Yc arrives next, this corresponds to case (a), so Yc is executed as is, and the processor strength is updated to 2. If the task is then switched to b, the case (a) will occur and the locked zb will be executed. Finally, Wa is executed, and instructions existing in other tasks are also executed in the order of Xd-+Yc-+Zb-+Wa.

FIG. 4 shows a fourth embodiment of the present invention, and this fourth embodiment has a command decoding means (2) that is different from the first embodiment.
In addition to the number designation signal line (24), which is a direct path through which the virtual register number output from the address conversion means (4) is directly supplied, the input buffer memory (21
), the status flag section and control section (23), and the shift register (22), and after a certain time delay, the address conversion means (4) and the output latch section (6-4) of the arithmetic processing block (6). It is equipped with a passageway that is supplied to the In this case, the direct number designation signal line (24) supplies the register number of the source operand for arithmetic processing, and is connected from the input buffer memory (21) to the status flag section and control section (23) to the address conversion means (4). This path supplies the register number of the destination operand with a delay. Here the shift register (22)
Each stage has a sufficient number of bits to specify a register number, and data is transferred stage by stage to the address conversion means (4) using the basic clock of the system. The input buffer memory (21) has a shift register (2
2), and is set to perform the following operation depending on the state of each stage of the shift register (22) stored in the status flag unit and control unit (23). . In other words, the shift register (22
) is empty, the input data (register number) passes through the input buffer memory (21) and is directly stored in the shift register (2
3). If the shift register (23) of that stage is already filled with data (register number), the input data is stored in the input buffer memory (21).

Further, the shift operation of the shift register (23) is stopped when data is stored in the input buffer memory (21) at the next stage.

FIG. 7(b) shows the configuration of a control circuit that operates as described above, and this FIG. 7(b) shows the configuration of one stage each. In the same figure, IN-DATA indicates input data, IN-
RQ is an input request pulse signal to be input to this stage, and CK is a system basic clock. Also, in the same figure, (21) is an input buffer memory, and specifically, when the E input is asserted, D (L)
a multi-bit flip-flop circuit in which the input is stored;
(23-1) is 1 bit of the status flag section (23), and in addition to the E input and D (L) input, the clock CK
(23-2) is a flip-flop circuit that stores the D input by an edge trigger of the input; (23-2) is a flip-flop circuit with E input and D (L) input; (22) is a shift register for one stage; It is a multi-bit flip-flop circuit with (L) input, CK large input and D input. Also, in the figure, (23-3) is a logic circuit network for realizing a desired operation, and (2B-4) is a selector circuit network that selects either the input buffer or the data from the preceding shift register. , status flag Q+,
The definition of Q2 is as described in FIG. 7(a).

In addition, in FIG. 4, (25) is the instruction decoding means (2).
) outputs an input request pulse to the appropriate input stage of the shift register (22) according to the number of pipeline stages of the arithmetic processing block (6) used when executing each instruction output from the input (1) that supplies data. ) is a control means.

(Effects of the Invention) As explained above, according to the processor with a task switching function according to the invention of claim (1), in a pipelined processor, mutually dependent instructions that cannot be executed consecutively are detected. When switching tasks, an independent instruction for the instruction currently being executed is brought from another task, so instructions from multiple tasks can be executed sequentially, so there are no dependencies between consecutive instructions. There is no relationship and no register hazard occurs. Therefore, according to the present invention, a pipeline operation close to the ideal can be realized, and a processor with extremely high execution performance can be obtained.

Further, according to the processor with a task switching function according to the invention of claim (2), since it is provided with a plurality of data output ports and command input/output ports to the outside of the processor,
Simultaneous data input/output and simultaneous instruction input/output are now possible.
A multiprocessor system can be realized with a single processor, and data input/output instructions, which generally take a long time to execute and are a major cause of disrupting pipeline operation, can be handled by task switching, making them ideal. It can be converted into Noku Eveline. Therefore, according to the present invention, high-speed calculation processing is possible.

Further, according to the processor with a task switching function according to the invention of claim (3), an intensity counter, an intensity buffer counter,
Since it is equipped with a strength memory determination means, it detects the strength in the code during the instruction sequence of each task and compares it with the current strength of the processor.If the strength is higher than that, execution continues, and if it is lower, execution is stopped. This makes it possible to achieve synchronization between tasks, so the synchronization of processing between processors, which has been a problem in conventional multiprocessor systems, is solved by the present invention.
This can be easily realized by adding a small amount of hardware using a pseudo multiprocessor configuration using processors.

Therefore, according to the present invention, processing time can be significantly reduced compared to the conventional synchronization method using software.

Furthermore, according to the processor with a task switching function according to the invention of claim 14, when a plurality of arithmetic processing blocks are caused to execute instructions one after another, the generation timing of the result varies depending on the number of pipeline stages of each arithmetic processing block. ,
As mentioned above, since it is equipped with a shift register section with an input buffer memory, the timing of the data write operation to the register of the destination operand written in the same instruction can be adjusted by appropriately selecting the input position to the shift register. The output latch and write register of the arithmetic processing block can be accessed according to the generation timing, so the instruction operation code, source operand, and destination operand can all be written on the same line. becomes possible. Therefore, according to the present invention, the efficiency of program development is greatly improved.

With the task switching function-equipped processor according to any of the above inventions, the execution performance of a processor with a highly pipelined configuration can be greatly improved, and the ease of use can be increased.

[Brief explanation of the drawing]

FIG. 1 is an internal configuration diagram of a processor showing a first embodiment of the present invention, and FIG. 2 is a configuration of a second embodiment that adds input/output ports, etc. to the configuration of the first embodiment to achieve even greater effects. 3 is a block diagram of a third embodiment of the present invention that can specify synchronization between tasks and the order of execution of instructions, and FIG. A circuit configuration diagram of a fourth embodiment of the present invention that can control operation, FIG. 5 is a timing diagram of conventional pipeline operation in general, FIG. 6 is a diagram showing a task switching circuit, and FIG. input buffer memory,
FIG. 2 is a diagram showing a detailed circuit of one stage of shift register, a status flag section, and a control section. 1... Instruction buffer means 2... Instruction decoding means 2-1... Lock instruction buffer memory 2-2... Strength storage determining means 2-3... Strength counter 3... Task switching control means 4...Address conversion means 5...Register block 6...Arithmetic processing block 7...Internal bus 8...Program counter...Instruction input port 2...Data input/output port 3... Data switch means 1...Input buffer memory 2...Shift register 3...Status flag section and control section 5...Input position control means Figure 3b Figure 6

Claims (4)

[Claims] (1) A plurality of instruction buffer means each storing a part of a task which is a plurality of types of instruction sequences, and storing the address of the next instruction to be executed in each task, and the instruction is actually executed. and a program counter means for holding the next instruction address; and a program counter means for selectively taking in and sequentially decoding the outputs of the respective instruction buffer means, and determining whether or not the next instruction to be executed is executable based on the decoding result. an instruction decoder that outputs a check signal indicating whether the instruction is possible; and task selection, which is information on the next task to be selected, based on the check signal from the instruction decoder and internally set switching algorithm information for each task. task switching control means for outputting a signal; address conversion means for generating an actual register number by synthesizing the task selection signal from the task switching control means and the temporary register number output from the instruction decoding means; a register block that is capable of accessing the storage part at the register number position by inputting the actual register number and writing data from or reading data to the internal bus; and a single or plural arithmetic processing blocks that execute arithmetic processing, and the instruction decoding means has a determination circuit that determines whether or not the instruction currently being decoded can execute consecutive instructions of the same task. The task switching control means includes a control circuit configured to perform a task switching operation whenever the next instruction of the same task cannot be executed due to a check signal from the instruction decoding means. A processor with a distinctive task switching function. (2) a plurality of data input/output ports that can input/output a plurality of data series in parallel; and a data switch that connects each of the data input/output ports and a register block in response to a task selection signal from the task switching control means. 2. A processor with a task switching function according to claim 1, further comprising a plurality of instruction input ports connected to each of said plurality of instruction buffer means. (3) The instruction decoding means includes a strength counter that stores or updates the strength of the instruction, and strength information that is included in a part of the instruction code or exists in each instruction sequence as an independent non-execution/control code. a storage circuit for storing, a comparison circuit that compares the intensity of the intensity counter with intensity information of the storage circuit, and an output that outputs a lock flag signal when the intensity of the intensity counter is higher as a result of comparison by the comparison circuit. and a number of tasks having a function of locking the execution of an instruction with intensity information in the arithmetic processing block and temporarily storing the instruction with the intensity information upon receiving the lock flag signal. and the same number of lock instruction buffer memories, and the program counter is provided corresponding to each task, and has a function of stopping updating to the next instruction address upon receiving a lock flag signal from the output circuit. A processor with a task switching function according to claim 1 or 2, characterized in that the processor has a task switching function. (4) At least a register section with multiple input/output ports capable of independently executing writing and reading is provided, and the arithmetic processing block has a multi-stage pipeline configuration, and for each pipeline configuration, the register number and the arithmetic processing block are specified. A shift register with a bit width sufficient to specify the type, an input buffer memory with the same bit width as the data input section of each stage of the shift register, and a state of each stage of the shift register, that is, empty, in use, and standby. each operation control means for determining the type of operation of each stage of the shift register according to the value of the status flag indicated by the status flag section, and each operation outputted from the instruction decoding means. Claim characterized by comprising an input position control means for inputting a destination register number for storing a processing result to an appropriate stage number position of the shift register according to the number of pipeline stages required for the arithmetic processing. The task switching type processor according to (1) to (3).