JP2002244846A - Processor, computer-readable recording medium with circuit source for the same recorded thereon, and assembler converting processing program for processor into machine language - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify a control part and increase the processing speed in a processor such as a CPU core by switching a data transmission route to an arithmetic logic unit to a bypass route and avoiding the occurrence of a resister conflict phenomenon without using a bypass control logic circuit. SOLUTION: A control code 44 switching a data input route which is determined based on a combination of commands before and after is embedded into a command code 45 to directly transmit bit information of the control code 44 to DMUX 13 of a multiplexer for switching a data input route to ALU 15 through a control line L1. Consequently, even if the combination of commands before and after is one causes occurrence of the resister conflict phenomenon, occurrence of the phenomenon can be avoided by switching the route to ALU 15 to the bypass route.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline control type processor that divides an instruction into several stages and processes the plurality of stages in parallel. Regarding techniques to avoid.

[0002]

2. Description of the Related Art Conventionally, in a pipeline control type processor, the processing of the operation execution stage of the current instruction is started before the processing of the operation result storage stage of the previous instruction is completed. Or, when the contents of the memory are used for the operation of the current instruction, there is a problem that the contents of the register or the memory before being updated by the previous instruction are used for the operation of the current instruction, and a correct operation result cannot be obtained. there were. Since this problem occurs when a plurality of consecutive instructions use the same register or memory in conflict (Conflict), it is generally called a register conflict problem. FIG. 7A shows a mechanism of the occurrence of the register conflict problem when the number of stages used in the pipeline processing is four. Exec of the current instruction
ute (calculation execution) stage (hereinafter abbreviated as E stage)
The contents of the register C used for 101 are referred to by the current instruction at the end of a decode (decode) stage (hereinafter abbreviated as D stage) 102 immediately before the E stage 101. However, at this point, the previous instruction Write
Since the processing of the Back (operation result storage) stage (hereinafter abbreviated as WB stage) 103 is not completed, the content of the register C before being updated by the previous instruction is used for the E stage 101 of the current instruction. Occurs.

On the other hand, if the occurrence of a register conflict phenomenon is predicted in advance from the combination of the instruction to be executed before and after, the input to the arithmetic logic unit which is the source of the operation in the E stage of the current instruction is performed. As data,
2. Description of the Related Art There is known a processor of a bypass control system that directly uses an output value from an arithmetic logic unit in a previous instruction instead of the contents of a register or a memory specified by an operand of a current instruction (for example, Japanese Patent Application Laid-Open No. 2000-305777). reference). This type of processor is, for example, shown in FIG.
As shown in (b), the register C updated by the previous instruction
Is referred to by the current instruction, not the contents of the register C itself, but the contents of the new register C, which is the result of the operation by the E stage 105 of the previous instruction, at the D stage 106 of the current instruction using a bypass circuit. The direct reference method avoids the above-described register conflict phenomenon. Also, in the process of converting each instruction word in the source program into an instruction code in a machine language format by an assembler, detecting a combination of instruction words in which a register conflict phenomenon occurs, and detecting such a combination. Between the previous instruction and the current instruction
peration) Insert an instruction that does nothing to avoid the occurrence of the register conflict phenomenon.
There is a P insertion type processor. For example, as shown in FIG. 7C, when using the contents of the register C updated by the previous instruction in the current instruction, the processor of this system inserts a NOP instruction between the previous instruction and the current instruction. By doing so, the contents of the register C updated at the WB stage 108 of the previous instruction can be referred to at the D stage 109 of the current instruction.

[0004]

However, in the above-mentioned conventional processor of the bypass control system, the occurrence of the register conflict phenomenon is detected in advance, and the data transmission path to the arithmetic logic unit is changed to the bypass path. A logic circuit for switching (a bypass control logic circuit) is required. When the number of instructions and registers that can be used in the device is large, a large number of conditions under which a register conflict phenomenon occurs occur, and the scale of the bypass control logic circuit also increases. Therefore, in such a case, the presence of the bypass control logic circuit causes the control unit (controller unit) of the device to be complicated, which causes an increase in the logic scale of the entire device, and also reduces the system clock frequency. This is a factor that causes a decline. In addition, the conventional NO
In a P-insertion type processor, if the combination of the preceding and following instructions is a combination that causes a register conflict phenomenon, it is necessary to execute the NOP instruction in addition to the original instruction, so that the execution efficiency of the program is reduced. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem. When a combination of instructions before and after is a combination in which a register conflict phenomenon occurs, the present invention can be applied without using a bypass control logic circuit. By switching the data transmission path to the arithmetic logic unit to a bypass path, it is possible to avoid the occurrence of the register conflict phenomenon, thereby simplifying the control unit and reducing the logic scale of the entire device. While you can
It is an object of the present invention to provide a processor capable of increasing the processing speed.

[0006]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a pipeline control type processor which divides an instruction into several stages and processes a plurality of stages in parallel. A plurality of registers to be held, a memory for storing various data including an executable program, an arithmetic logic unit for performing various operations based on the data stored in the registers and the memory, and a register, a memory and an arithmetic logic unit. A multiplexer that switches a data transmission path between various circuits inside the device, and a control unit that controls various circuits inside the device,
The instruction code constituting the executable program stored in the memory incorporates a control code determined based on a combination of the preceding and following instruction codes, and the control unit has a control line connected to the multiplexer. Read the instruction code stored in the memory, transmit bit information of the control code incorporated in the instruction code to the multiplexer through a control line, and switch a data transmission path between predetermined circuits in the device. It was done.

In the above configuration, the control unit transmits bit information of the control code determined based on the combination of the preceding and following instruction codes in the program to be executed to the multiplexer through the control line, A data transmission path is switched between predetermined circuits in the device. Therefore, even when the combination of the previous instruction and the current instruction is a combination in which a register conflict phenomenon occurs, for example, the multiplexer to which the control code is transmitted is a multiplexer for switching the data input path to the arithmetic logic unit, and the instruction If the control code embedded in the code indicates connection to the bypass path,
The control unit can transmit the bit information of the control code to the multiplexer to switch the data input path to the arithmetic logic unit to the bypass path. As a result, the occurrence of the register conflict phenomenon can be avoided.

[0008] The data transmission path switched by the control unit is a path for input to the arithmetic logic unit. The path to be switched includes an output from the arithmetic logic unit and a normal register or memory. It is desirable to include a bypass path for inputting directly to an input-only register to the arithmetic logic unit without intervention. Thus, when the combination of the previous instruction and the current instruction is a combination in which a register conflict phenomenon occurs, the control code incorporated in the instruction code is instructed to connect to the bypass path. However, by transmitting the control code to the multiplexer, the data transmission path to the arithmetic logic unit can be switched to the bypass path.

When the control code in the read instruction code is a code indicating switching to a bypass path, the control unit transmits the bit information of the control code to the arithmetic logic unit via a control line. It is desirable to switch the input path to the arithmetic logic unit to the bypass path by transmitting the signal to the input path switching multiplexer. As a result, the above operation can be obtained accurately.

According to a fourth aspect of the present invention, there is provided a computer-readable recording medium recording a source of a circuit of a processor, wherein the source is a circuit of the processor according to any one of the first to third aspects. Is a source of hardware description language level. In this configuration, after the source is read by a computer, the source is converted into a logic gate by logic synthesis, and the converted logic gate is reflected on a logic integrated circuit such as an FPGA, thereby obtaining the same as the above. Action can be obtained.

According to a fifth aspect of the present invention, there is provided a computer-readable recording medium recording an assembler for converting each instruction word included in a source of a processing program for a processor into an instruction code in a machine language format. Detects whether or not a conflict occurs in a register or a memory in a processor during execution of an instruction code based on a combination of preceding and succeeding instruction words in a source program, and determines a predetermined condition in the processor based on the detection result. A control code for switching the data transmission path between the circuits is generated, and this control code is incorporated in the instruction code. By executing the instruction code generated by the assembler by the processor according to the first aspect, the operation according to the first aspect can be accurately obtained.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a CPU core which is a processor according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration around the CPU core according to the present embodiment. The CPU core 1 is a simple RISC processor, and is a kind of intellectual property (IP) incorporated and used on a field programmable gate array (hereinafter referred to as FPGA) 2. Field programmable gate array (hereinafter F
The CPU core 1 and the C
An IP3 such as a macro cell or a mega cell to be controlled by the PU core 1 is arranged. The CPU core 1 decodes the contents of the instruction to control the entire CPU core 1, controls a data path 5 including various registers and multiplexers, and detects an interrupt signal generated inside or outside the FPGA 2. An interrupt control unit 6 for notifying the control unit 4 is provided.

Next, the configuration of the data path 5 will be described. Data path 5 is IR (Instruction Registe)
r: instruction register) 7, program counter (Program
Counter: hereinafter abbreviated as PC) 8. PR which is a register for holding a return address when a JUMP instruction is executed
J (Program counter Return for Interrupt) 9; PRI (Program counter Return for Interrupt) 1 which is a register for holding a return address when an interrupt occurs
0, a global register (GR) 11 which is a kind of data input / output port from a device outside the CPU core 1, and an AR 12 which is a general-purpose register for storing calculation results and the like. The data path 5 includes an arithmetic logic unit (Arithmetic L
ogic Unit (hereinafter abbreviated as ALU) 15 and a DMUX (Data Input Multiplexer) 13 which is a multiplexer for switching a data input path to the arithmetic logic unit 15.
And SRC (Source Registe) which is a register for temporarily storing input data to the ALU 15 via the DMUX 13
r) 14 and a SREG (System Regis) which is a register for storing a system flag (a flag indicating that an overflow has occurred, an interrupt has occurred, an operation result is 0, etc.)
ter) 16. Furthermore, data path 5
Is the data that stores the data used by ALU15, etc.
The memory 17 includes a memory 17 and a program memory 18 storing a program describing the processing of the CPU core 1 (hereinafter, referred to as an operation description program). Various registers such as the PRJ 9, the ALU 15, the DMUX 13, and the data memory 17 mutually input and output data via the data bus 19. The IR 7, the PC 8, and the program memory 18 mutually input and output each instruction code in the operation description program via the program bus 20.

Next, a transmission path for data transmission (hereinafter, referred to as a transmission path)
R1 to R8 will be described. Route R1
Is a bypass data transmission path for directly inputting output data from the ALU 15 to the SRC 14 which is a register dedicated to input to the ALU 15 without passing through the AR 12 or the data memory 17. The route R2 is a GR1
1 is a data transmission path for outputting output data from the IP 1 to IPs inside and outside the FPGA 2. Also, routes R3 to R8
Is a path connecting the CPU core 1 and the IP inside and outside the FPGA 2, and among these paths, the paths of R 3, R 4 and R 8 are used when reading the data of the IP inside and outside the FPGA 2 from the CPU core 1. Specifically, the route R3 is C
Module ID of destination IP to be read from PU core 1
The route R4 is a route for designating the IP address of the other party to be read from the CPU core 1. The route R8 is a route for the CPU core 1 to read data output from the destination IP. When the CPU core 1 transmits the module ID and the address of the IP to be read to the destination IP via the route R3 and the route R4, the read destination of the read destination corresponding to the module ID transmitted via the route R3 is transmitted. The IP returns the data of the address transmitted on the route R4 to the CPU core 1 via the route R8. Thereby, data at an arbitrary address in an arbitrary IP can be read from the CPU core 1.

The routes R5 to R7 are routed from the CPU core 1 to the F
Used when outputting data to IP inside and outside PGA2,
Each of the routes R5, R6, and R7 is a route for designating the module ID of the IP of the output partner, and the IP of the output partner.
And a path for transmitting the data output from the CPU core 1. When the CPU core 1 transmits the module ID, the address, and the output data of the output destination IP to the output destination IP via the routes R5, R6, and R7, the output corresponding to the module ID transmitted on the route R5 is performed. The IP stores the output data transmitted on the route R7 in the address transmitted on the route R6. As a result, an arbitrary I
Any data can be written to any address in P. Also, GR (15: 0), IP_IN_ID (3: 0), IP_IN
_ADR (11: 0), IP_ID (3: 0), IP_ADR (11: 0), IP_DATA (15:
0) and IP_DIN (15: 0) indicate the name and length (bit length) of the data transmitted through each of the above-described R2 to R8 paths.

Next, control lines L1 to L1 to which control signals are transmitted
L5 will be described. The control line L1 is a control line for transmitting a control signal or the like for switching a path from a decoder inside the control unit 4 to the DMUX 13. The control line L2 is connected to C
This is a control line for transmitting an IP_WE signal which is a write enable signal when data is output from the PU core 1 to the IP3. The control line L3 is a control line for transmitting a clock (CLK) signal generated by a clock generator provided inside or outside the FPGA 2. The control line L4 is a control line for transmitting a clear (CLR) signal sent from circuits inside and outside the FPGA 2. The control line L5 is a control line for transmitting interrupt request signals IRQN_0 to IRQN_7 from IP inside and outside the FPGA 2. The control line L6 and the control line L7 are respectively a control line for transmitting an interrupt request signal IRQ from the interrupt control unit 6 to the control unit 4 and a transmission line of the interrupt enable signal IACK from the control unit 4 to the interrupt control unit 6. Control line.

As shown by the arrow A in the figure, the control unit 4 converts each instruction code in the operation description program stored in the program memory 7 into the program bus 20 and the I / O bus.
When read through R7, this instruction code is
It is stored in an internal decoder (not shown). Then, based on the information analyzed by the decoder unit, the control unit 4 transmits a control signal including a control code for switching the data transmission path and an operation symbol to the ALU 15 as shown by an arrow B in the DM.
The command is transmitted to the UX 13 and the processing corresponding to the read instruction code is executed. Further, the control unit 4 includes an interrupt control unit 6
When an interrupt request signal IRQ is received from the controller via the control line L6, if the interrupt request is to be permitted, the interrupt control signal is transmitted to the interrupt controller 6 via the control line L7.
Send ACK. Upon receiving this signal, the interrupt control unit 6 transmits an interrupt vector, which is a jump destination address, to the PC 8 in the data path 5 as indicated by an arrow C. Thereby, the interrupt processing is started.

Next, with reference to FIG. 2, a description will be given of a control technique for simplifying the control unit 4 employed in the CPU core 1 and increasing the processing speed. FIG.
(A) and (b) show a comparison between the conventional control method and the control method of the present invention. The assembler process P1 shown in each of these figures is a process performed before the CPU core is incorporated into the FPGA, and the conventional assembler 33 or the assembler 43 of the present invention uses the respective instruction codes (in the case of the present invention, Code 45) is generated and each program
Memory (in the case of the present invention, program memory 1 in FIG. 1)
8). Further, the processor internal processing P2 is executed after the CPU core is incorporated on the FPGA.
This is a process performed by the control unit inside the CPU core. In the conventional assembler process P1, as shown in FIG. 2A, the assembler 33 converts the assembly language instruction words 31,
The instruction codes 34 and 35 in the machine language format are generated by simply converting the M.32 into machine language (machine language). These instruction codes 34 and 35 are
The data was written into the program memory inside the core and used in the processor internal processing P2. In the processor internal processing P2, the bypass control logic circuit 36 provided inside the control unit of the CPU core executes the above-described instruction codes 34 and 35.
Prior to the execution of the instruction code, these instruction codes 34 and 35 are read from the program memory,
It has been detected whether or not the combination of 4, 35 corresponds to the combination that causes the register conflict phenomenon. If applicable, the control code 37 for switching the data input path to the ALU is transmitted to the bypass control circuit 38 in the data path, so that A
The data input path to the LU 15 is switched to a bypass path to avoid occurrence of a register conflict phenomenon.

On the other hand, as shown in FIG. 2 (b), in the assembler processing P1 of the present invention, the assembler 43 converts the instruction words 41 and 42 of the assembly language into a register conflict phenomenon. Is detected. When such a combination is detected, the control code 44 for switching the data input path to the ALU 15 is incorporated into the current instruction code 45, and the installed instruction code 45 is stored in the program in the CPU core 1.・
Write to memory 18. In the processor internal processing P2,
The control unit 4 shown in FIG. 1 reads out the instruction code 45 from the program memory 18 and converts the control code 44 in the instruction code 45 into a control signal for bypass control in the data path via the control line L1 shown in FIG. Circuit 50 (DM in FIG. 1)
(Corresponding to the UX 13), thereby switching the data input path to the ALU 15 to the bypass path to avoid the occurrence of the register conflict phenomenon.

As described above, in the present invention, the assembler 43 generates the control code 44 for switching the path to the bypass circuit R1 when generating the instruction code 45,
Since the control code 44 is incorporated in the instruction code 45, unlike the conventional bypass control system, the CPU core 1 is provided with a bypass control logic circuit 36 for generating a control code for path switching. Eliminates the need. Therefore, the controller 4 of the CPU core 1
Has a simpler structure than the control unit of a conventional bypass control type processor. Also, this CPU core 1
Unlike the conventional NOP insertion type processor, even when the combination of the previous instruction word 41 and the current instruction word 42 is a combination in which a register conflict phenomenon occurs,
Since the occurrence of the register conflict phenomenon can be avoided without executing the NOP instruction, the execution efficiency of the program can be improved and the processing can be speeded up as compared with the NOP insertion type processor.

A description will be given of a correspondence relationship before and after the conversion when converting the instruction word into the instruction code (machine language) by the assembler. In the conventional assembler 33, if the current instruction word 32 to be converted is the same mnemonic instruction word, the converted instruction code 35 is always the same code. That is, a one-to-one correspondence has been established between the instruction word 32 of the conversion source and the instruction code 35 after the conversion. On the other hand, in the assembler 43 of the present invention, even if the current instruction word 42 as the conversion source is the same mnemonic instruction word, the combination of the instruction word 42 and the immediately preceding instruction word 41 is a register conflict. Since the control code 44 incorporated in the converted instruction code 45 can be different depending on whether the combination causes a phenomenon or not, the correspondence between the conversion source instruction word 42 and the converted instruction code 45 Has a one-to-n relationship. As described above, the assembler 43 sets the correspondence between the conversion source instruction word 42 and the converted instruction code 45 to a one-to-n relationship different from the conventional one, and includes a control for bypass control in the converted instruction code 45. By incorporating the code 44,
When the control unit 4 reads the instruction code 45, A
By appropriately switching the data input path to the LU 15 to the bypass circuit, the occurrence of the register conflict phenomenon can be avoided.

Next, the mechanism of the bypass control using the control code 44 will be described with reference to FIG.
Registers 12a and 12b in the figure are general-purpose registers corresponding to AR12 in FIG.
Are respectively connected to these registers 12a, 12b and SR
This is a data transmission path connecting C14. DST4
Numeral 6 denotes a memory for holding data to be operated, and specifically indicates one of the registers or the data memory 17 corresponding to the AR 12 in FIG. As shown in the figure, the part storing the control code 44 in the decoder 47 inside the control unit 4 is a DMU which is a multiplexer for switching the data input path to the ALU 15 via the control line L1.
It is directly connected to X13. Therefore, IR7 in FIG.
Is read by the decoder 47 at the same time as the bit information constituting the control code 44 is
The data is transmitted to X13, and the data input path to ALU 15 is switched to a path corresponding to the bit information. FIG.
When the current instruction code 45 is generated, the assembler 43 shown in FIG. 4 shows that the combination of the instruction word that is the source of the instruction code 45 and the instruction word before it is a combination that causes a register conflict phenomenon. Incorporates bit information corresponding to the bypass route R1 into the generated instruction code 45. For example, the bypass route R1 in the figure
If the bit information corresponding to is "100",
If the assembler 43 determines that the combination of the instruction word that is the source of the instruction code 45 to be generated and the instruction word before it is a combination that causes a register conflict phenomenon, the assembler 43 avoids the occurrence of the register conflict phenomenon. In order to execute, the bit information in the instruction code 45 is “10”.
A control code 44 of 0 'is incorporated. When the decoder 47 reads the instruction code 45, the bit information “100” is transmitted from the decoder 47 to the DMU via the control line L1.
The data is transmitted to X13, and the data input path to the ALU 15 is switched by the DMUX 13 to the bypass path R1 corresponding to the bit information. Thereby, the control unit 4
When the instruction code 45 is executed, the occurrence of the register conflict phenomenon can be avoided without performing the process of detecting the occurrence of the register conflict phenomenon based on the combination of the preceding and succeeding instruction codes. The processing can be speeded up.

Next, a specific example of the process using the bypass control mechanism shown in FIG. 3 will be described with reference to FIGS. 4 (a), 4 (b) and 4 (c). In each of these figures, a frame 51 corresponds to the decoder 47 in FIG. 3, and each instruction in this frame 51 indicates the content of each instruction code in the Decode (decode) stage. Each instruction in the frame 52 indicates the content of each instruction code in the Execute (operation execution) stage. As shown in FIG. 4A, the instruction in the operation execution stage is No Operation (an instruction that does nothing: hereinafter abbreviated as NOP), and the instruction in the decode stage is R
If the instruction is to add the contents of the DST 46 to the value held in the EG-A 48 to update the contents of the REG-A 48 (hereinafter, referred to as an ADD instruction), a NOP instruction that is currently in the operation execution stage is Next, it is impossible to update the contents of the REG-A 48 or DST 46 used for the ADD instruction for executing the operation. Therefore, when the ADD instruction is executed, it is unlikely that a register conflict phenomenon will occur. For this reason, the assembler 43 shown in FIG. 2 uses this ADD instruction with the R information instead of the bit information corresponding to the bypass path R1 at the time of assembling.
The bit information corresponding to the normal route R11 connecting the EG-A 48 and the SRC 14 is incorporated.

Therefore, when the decoder 47 reads the ADD instruction, the bit information corresponding to the path R11 is transmitted to the DMUX 13 via the control line L1, and the DMUX 1
3, the data input path to the SRC 14 and the ALU 15 is switched to the path R11. After this, usually ALU
15 executes the instruction in the operation execution stage.
In the case shown in (a), the instruction to be executed is NOP
Since this is an instruction, the processing by the ALU 15 is not actually performed. On the other hand, when the decoding of the ADD instruction is completed, the decoder 47 instructs the REG-A 48 to output the held data. As a result, the data of the REG-A 48 is output to the SRC 14 via the route R11.

Next, as shown in FIG. 4B, the above-mentioned ADD instruction enters the operation execution stage, and the next instruction (an instruction for writing the contents of the REG-A 48 into the data memory 17: , STORE instruction) is read, the STOR is sent to the DMUX 13 via the control line L1.
The bit information embedded in the code of the E instruction is transmitted. The bit information embedded in the STORE instruction code corresponds to the bypass route R1. The reason is that the process of updating the data in the REG-A 48 by the above ADD instruction and the R by the above STORE instruction
When the process of writing the data in the EG-A 48 and the process of writing the data in the EG-A 48 are successively performed, the register S S which is a register dedicated to input to the ALU 15
The RC 14 needs to read the data of the REG-A 48 after the execution of the ADD instruction used for the STORE instruction before the data update processing of the REG-A 48 by the ADD instruction is completed.
This is because even if the data of the G-A 48 is read, the data of the REG-A 48 before the execution of the ADD instruction is read. That is, when the SRC 14 reads the data of the REG-A 48 used for the STORE instruction, a register conflict phenomenon occurs. Therefore, SR
The C14 cannot read the data of the REG-A48 after the execution of the ADD instruction unless the C14 directly reads the data for updating the REG-A48 via the bypass path R1. The assembler 43 shown in FIG. 2 detects the occurrence of the register conflict phenomenon during assembling (machine language conversion) and incorporates bit information corresponding to the bypass route R1 into the instruction code of the STORE instruction.

As described above, since the bit information incorporated in the STORE instruction code corresponds to the bypass route R1, when the decoder 47 reads the STORE instruction code, the bit information incorporated in the STORE instruction code is embedded in the STORE instruction code. The bit information is transmitted to the DMUX 13 via the control line L1, and the DMUX 13 switches the data transmission path to the normal path R11.
Is switched to the bypass route R1.

On the other hand, the ALU 15 executes the ADD instruction based on the data set in the SRC 14 and the data set in the DST 46 at the start of the execution of the operation. The operation result of this ADD instruction is REG-A4
8 is written to the SRC 14 via the bypass path R1 at the same time. As a result, ALU15
Can refer to the value of the REG-A 48 reflecting the execution result of the above ADD instruction when the next STORE instruction is executed.

Next, as shown in FIG. 4C, the above STORE instruction enters an operation execution stage, and
When the next instruction (NOP instruction) is read to the control line L
1, bit information indicating that all the data input paths are switched off is transmitted to the DMUX 13 through the SRC
14 and the data input path to the ALU 15 are all closed. The reason is that the assembler 43 shown in FIG.
This is because the content of the control code 44 incorporated in the P instruction is bit information for turning off the switches of all data input paths.

On the other hand, the ALU 15 sets the above-mentioned A set in the SRC 14 at the start of the execution of the operation of the STORE instruction.
Execution result of DD instruction ("REG-A + DST" in the figure)
And writes the execution result in the data memory 17.

Next, with reference to FIG. 5, the hardware necessary for incorporating the CPU core 1 into the FPGA 2 will be described. In order to incorporate the CPU core 1 into the FPGA 2, a personal computer 62 and an ASAP (Advertisement) which is an interface device between the personal computer 62 and the FPGA 2 are used.
aptive Scan Agent Pod) 63 is used. ASA
P (Adaptive Scan Agent Pod) 63 is a TAP (Test
Access port) is provided with a dedicated terminal for boundary scan test.
(Adaptive Scan Handler: adaptive scan processing unit) 64. The ASH64 is a module for transmitting and receiving signals to and from the ASAP15. Also, CD-RO
In M61, VHDL (VHSIC Hardware) of CPU core 1 is provided.
A description language level source, a source of an operation description program of the CPU core 1 described in an assembly language, and an assembler 43 for assembling the source are stored.

Next, referring to FIG. 6 in addition to FIG.
A process of incorporating the CPU core 1 into the FPGA 2 will be described. Prior to the process of incorporating the CPU core 1, the user reads the source of the operation description program of the CPU core 1 stored in the CD-ROM 61 with the personal computer 62 (# 1) and reads the contents of the operation description program into the FPGA.
2 is customized according to other IP3 specifications (# 2). Next, the user reads the assembler 43 stored in the CD-ROM 61 with the personal computer 62 (#
3), the source of the operation description program is assembled by the assembler 43 (# 4). At this time, as described above, the assembler 43 incorporates the control code 44 corresponding to the combination of the preceding and following instructions into each instruction code constituting the converted operation description program. Next, the user inputs a VHD of IP3 that is a target of the CPU core 1.
After creating the L-level source (# 5), the CD-ROM
The VHDL-level source of the CPU core 1 stored in the CPU 61 is read (# 6), and the logic of the IP3 source and the source of the CPU core 1 is synthesized (# 7). Then, the user downloads the result of the logic synthesis and the operation description program assembled in # 4 to the FPGA 2 (#
8). In this way, the CPU core 1 and its operation description program are
Together with the FPGA 2.

As described above, the CPU according to the present embodiment
According to the core 1, the control code 44 determined based on whether or not the combination of the preceding and following instruction codes 45 is a combination in which a register conflict phenomenon occurs is included in the instruction code 45 constituting the execution-type operation description program. By directly transmitting the bit information of the control code 44 to the DMUX 13 via the control line L1.
The data input path to the ALU 15 is switched. Thereby, when the combination of the instruction codes 45 before and after is a combination in which a register conflict phenomenon occurs, the ALU 15 can be used without using a logic circuit dedicated to bypass control required for the CPU core 1 of the conventional bypass control method. By switching the data input path to the path R1 to the bypass path R1, the occurrence of the register conflict phenomenon can be avoided.

The present invention is not limited to the above embodiment, and various modifications are possible. For example, in the above embodiment, the control line L1 for transmitting the control code 44 is provided between the decoder 47 and the DMUX 13, but the control line for transmitting the control code may be provided between the IR and DMUX.
In the above-described embodiment, an example is shown in which the REG-A48, which is a general-purpose register, is connected to the input terminal of the DMUX 13, which is a multiplexer for switching the data input path to the ALU 15, but the data terminal is connected to the input terminal of the DMUX. -A memory may be connected. As a result, the occurrence of the register conflict phenomenon in the data memory can be avoided.

[0034]

As described above, according to the first aspect of the present invention,
A method of incorporating a control code determined based on a combination of the preceding and following instruction codes into an instruction code constituting an executable program, and directly transmitting bit information of the control code to a multiplexer via a control line, the inside of the apparatus is controlled by a method. The data transmission path between the predetermined circuits is switched. Thereby, even when the combination of the previous instruction and the current instruction is a combination in which a register conflict phenomenon occurs, for example, the multiplexer to which the control code is transmitted is a multiplexer for switching the data input path to the arithmetic logic unit, If the control code incorporated in the instruction code indicates connection to the bypass path, the control unit transmits the control code directly to the multiplexer, and changes the data input path to the arithmetic logic unit to the bypass path. Can be switched to This makes it possible to avoid the occurrence of the register conflict phenomenon without using a logic circuit (a bypass control logic circuit) for generating a control code for bypass control. Therefore, as compared with a processor using a conventional bypass control logic circuit, the control unit of the device can be simplified and the logic scale of the entire device can be reduced. Also, unlike the conventional NOP insertion type processor, even if the combination of the previous instruction and the current instruction is a combination that causes the register conflict phenomenon, the occurrence of the register conflict phenomenon is avoided without executing the NOP instruction. Therefore, the execution efficiency of the program can be improved and the processing speed can be increased as compared with the NOP insertion type processor.

The data transmission path switched by the control unit is a path for input to the arithmetic logic unit, and a path to be switched includes an output from the arithmetic logic unit directly for input to the arithmetic logic unit. By including a bypass path for input to the register, even if the combination of the previous instruction and the current instruction is a combination that causes a register conflict phenomenon, the control code incorporated in the instruction code can be bypassed. If the connection to the route is instructed, the effects described above can be obtained accurately.

In the case where the control code in the read instruction code is a code indicating switching to the bypass path, the control unit transmits the bit information of the control code to the arithmetic logic unit via the control line. By transmitting the signal to the input path switching multiplexer and switching the input path to the arithmetic logic unit to the bypass path, the effects described above can be obtained accurately.

According to the invention of claim 4, after the source is read by the computer, the source is converted into a logic gate by logic synthesis, and the converted logic gate is converted to a logic integrated circuit such as an FPGA. By reflecting the same, an effect equivalent to the above-described invention can be obtained.

According to the fifth aspect of the present invention, the computer reads the assembler and executes the instruction code generated by the assembler by the processor according to the first aspect. The described effects can be obtained accurately.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration around a CPU core which is a processor according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a contrivance for speeding up processing while simplifying a control unit employed in the CPU core.

FIG. 3 is a diagram showing a mechanism of bypass control using a control code in the CPU core.

4 (a), (b) and (c) respectively show the CPU
The decoder in the core is ADD instruction, STORE instruction, NO
FIG. 9 is a diagram illustrating a mechanism of switching a data input path to an ALU when a P instruction is read.

FIG. 5 is a diagram showing hardware necessary for incorporating the CPU core into an FPGA.

FIG. 6 is a flowchart showing a process of incorporating the CPU core into an FPGA.

FIG. 7A is a diagram illustrating a mechanism of occurrence of a register conflict problem, FIG. 7B is a diagram illustrating a method of solving a register conflict problem by a bypass control method,
(C) A diagram showing a method of solving a register conflict problem by the NOP insertion method.

[Explanation of symbols]

Reference Signs List 1 CPU core (processor) 4 Control unit 13 DMUX (multiplexer for switching data input path to arithmetic logic unit) 14 SRC (register exclusively for input to arithmetic logic unit) 17 Data memory 18 Program memory 41, 42 Instruction word 43 assembler 44 control code 45 instruction code 47 decoder 61 CD-ROM (recording medium) L1 control line (control line connected to multiplexer) R1 bypass data transmission path R11, R12 data transmission path

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kenji Mogi 1-4-16 Higashitenma, Kita-ku, Osaka F-term in the Laurent Co., Ltd. 5B013 AA00 AA02 CC01 CC05 CC07 CC08 CC10 5B081 AA07 CC21 CC25 CC41

Claims (5)

[Claims] 1. A pipeline-controlled processor that divides an instruction into several stages and processes the plurality of stages in parallel, comprising: a plurality of registers for holding various data; and various data including an executable program. And an arithmetic and logic unit for performing various operations based on the data stored in the registers and the memory; and a data transmission path between various circuits in the device including the register, the memory and the arithmetic and logic unit. And a control unit for controlling various circuits in the device. The instruction code constituting the executable program stored in the memory is determined based on a combination of the preceding and following instruction codes. Control code is incorporated therein, wherein the control unit has a control line connected to the multiplexer. It reads the instruction codes stored in said memory,
The bit information of the control code incorporated in the instruction code is transmitted to the multiplexer through the control line,
A processor characterized in that a data transmission path between predetermined circuits inside the device is switched. 2. A data transmission path switched by the control unit is a path for input to the arithmetic logic unit, and a path to be switched includes an output from the arithmetic logic unit and a normal register. 2. The processor according to claim 1, further comprising a bypass path for directly inputting to an input-only register to each arithmetic logic unit without using a memory. 3. The control unit according to claim 1, wherein, when the control code in the read instruction code is a code indicating switching to a bypass path, the control unit transmits the bit information of the control code to the arithmetic logic unit via the control line. The processor according to claim 2, wherein a path for input to the arithmetic logic unit is switched to the bypass path by transmitting the data to a multiplexer for switching a data input path to the arithmetic logic unit. 4. A computer-readable recording medium recording a source of a circuit of a processor, wherein the source is a hardware description language level of the circuit of the processor according to claim 1. A computer-readable recording medium recording a source of a circuit of a processor, characterized by being a source of a computer. 5. A computer-readable recording medium on which an assembler for converting each instruction word included in a source of a processing program for a processor into an instruction code in a machine language format is recorded, wherein the assembler includes: At the time of execution, whether or not a conflict occurs in a register or a memory in the processor is detected based on a combination of preceding and following instruction words in the source program, and a predetermined circuit in the processor is determined based on the detection result. An assembler for converting a processing program for a processor into a machine language, wherein a control code for switching a data transmission path between the control codes is generated, and the control code is incorporated in the instruction code.