JPH0474379A - Memory integrated circuit - Google Patents

Abstract

PURPOSE:To easily execute the test fo a refresh request signal by adding a test mode setting circuit for inputting one of address signals and outputting a test mode setting signal, and providing a means for inputting the test mode setting signal to a data system control circuit and a read-out control input circuit of an I/O control part and activating it. CONSTITUTION:A test mode setting circuit 9 is added to a pseudo SRAM circuit 1, a test mode setting signal outputted therefrom is inputted to a Data system control circuit 6a, an OE system control circuit 7 and a WE system initial stage circuit 8 and data is outputted to an external I/O terminal at the timing synchronized with generation of an internal automatic refresh request signal at the time of self-refresh by an activation holding state of a refresh terminal. Accordingly, the generation confirmation and the synchronization measurement of the internal automatic refresh request signal which cannot be measured directly form the outside up to the present are facilitated. In such a way, the secured quality of a product can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory integrated circuit, and in particular to a pseudo static R.
This relates to test mode settings for AM integrated circuits.

[Conventional technology]

FIG. 8 is a block diagram of an example of a conventional memory integrated circuit.

The pseudo SRAM integrated circuit 1b includes a memory array section 5 that peripherally includes a Tecoder row, a sense amplifier row, and an I/O bus, an address section 2 that includes address control circuits and internal address counters in each row and two columns, and a refresh system. It is composed of refresh sections 3a and 3b that control the data, and an I/O section 4b that controls data input/output.

In the self-refresh mode in such a pseudo SRAM integrated circuit 1b, by controlling the external refresh terminal RFSH, the RFSH first-stage circuit 3a generates internal self-refresh request signals φRR and φRA, which are sent to the address section 2 and the REFRESH control circuit. The row address selection and sense system are activated and refresh is performed.

At this time, the I/O control unit 4b is not operated at all to reduce the current.

When the integrated circuit 1b enters this self-refresh mode, a refresh request signal φRR is generated at a constant period.

φRA is generated and a series of refresh operations are performed to hold the data in the memory cells of the memory array section 5.

When testing this memory integrated circuit, it is similar to the counter check of the address counter for internal row address generation, which is adopted to alleviate the complexity of refresh control required for RAM using one-transistor type dynamic cells. Various attempts have been made to test the refresh state, but no effective method has been found.

Pseudo-SRAM integrated circuits use one-transistor type dynamic cells in the memory array section, and SRAMs that do not require refreshing
It is a RAM-compatible package and has the advantages of lower cost compared to SRAM and easier refresh operation compared to highly integrated DRAM.
Recently, it has been attracting attention as an intermediate between SRAM.

The internally automatically generated refresh request signal during self-refresh used in this pseudo SRAM integrated circuit etc. is generated correctly, but in order to check whether it is generated at the correct cycle, basically the self-refresh request signal is generated correctly. During the refresh mode period, the self-refresh mode is continuously executed for a period of time that actually exceeds the data hold time to the extent that the internal refresh operation is not performed normally and becomes defective.

Also, a desired internal refresh request signal φRR.

If the period of φRA is short, checking using the above method is impossible, but in that case, checking is performed using the current value.

In this pseudo-SRAM integrated circuit, when it is necessary to hold data, which is the fate of D'RAM using transistor cells, it must be carried out regardless of whether it is in a standby state or an active state such as writing and reading. It is important to make the required refresh operation at regular intervals as close as possible to the characteristics of SRAM.

Here, the refresh mode when the SRAM is on standby is a self-refresh mode, and the refresh mode F when it is active is a latched refresh mode.

Further, although SRAM retains data even in a standby state, the current consumption in this case is very small, and it is also important to reduce the current consumption during self-refresh.

In self-refresh mode, refresh is generally carried out at regular intervals to retain data in dynamic cells, and the current at this time consists of an AC component current required for refreshing and a DC component in standby state. In order to reduce this, the absolute values of the DC and AC components are reduced and the period of the AC component is lengthened. That is, the purpose is to extend the generation cycle of internal refresh request signals φRR and φRA as much as possible.

Therefore, the required data retention time of pseudo SRAM is longer than that of normal DR.
It is longer than AM.

[Problem to be solved by the invention]

The conventional memory integrated circuit described above can only indirectly check the generation and timing of the internal automatic refresh request signal, so it cannot be accurately grasped, and when the cycle is too long, it is checked if the period is longer than the self-refresh mode hold time. Tests for retention are time consuming, and tests at room temperature, where data retention is particularly long, take even more time.

In other words, in a pseudo SRAM, etc., if the timing at which the internal automatic refresh request signal is generated during self-refresh is too long, it may cause a data hold failure, and if it is too short, the current may increase, resulting in a current failure. Therefore, strict control is required, and there is a problem that there is no simple check method to test and understand the internal automatic refresh request signal.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory integrated circuit in which an internal refresh request signal can be easily tested.

[Failure to solve the problem]

The memory integrated circuit of the present invention has a memo 9721 part having an L transistor type dynamic cell, and a memory part 9721 having address signals inputted from a plurality of address terminals.
a refresh section that inputs a refresh signal from a refresh terminal and outputs an internally automatically generated refresh signal to control the sense amplifier column of the memo 9721 section and the address section; ,
and an I/O control section having a plurality of I/O terminals for reading data in the memory array section by inputting an enable signal from a read enable terminal, and the pseudo static RAM enters an automatic refresh mode by the refresh signal. In the memory integrated circuit, a test mode setting circuit that receives one of the address signals and outputs a test mode setting signal is added, and the data system control circuit and read control input circuit of the I/O control section are provided with the test mode setting circuit. A means for inputting and activating a mode setting signal is provided, and the data is output to the I/O terminal in synchronization with the internal automatic refresh request signal.

Further, the memory integrated circuit of the present invention includes a memory array section having a one-transistor type dynamic cell, an address section for inputting address signals from a plurality of address terminals to control a decoder column of the memory array section, and a refresh terminal for refreshing. A refresh section inputs a signal and outputs an internally automatically generated refresh signal to control the sense amplifier row and the address section of the memory array 7s, and a refresh section inputs an enable signal from a read enable terminal to control the data in the memory amplifier section. Multiple I/Os for reading
A test mode in which one of the address signals is input and a test mode setting signal is output in a pseudo static RAM memory integrated circuit having an I/O control unit having a terminal and which enters an automatic refresh mode in response to the refresh signal. A setting circuit is added, and means is provided for inputting and activating the test mode setting signal to the data system control circuit and write control input circuit of the I/O control section, and in synchronization with the internal automatic refresh request signal. Data inputted to the memory array section from the I/O terminal is output to the I/O terminal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The pseudo SRAM integrated circuit 1 includes a test mode setting circuit 9 that inputs a signal from an address terminal An and outputs a test mode setting signal φCC in the pseudo SRAM integrated circuit 1b shown in FIG. 8, and further includes an I/O control section 4b. Except for the fact that the Data system control circuit 6a and the OE system film stage circuit 7a, which respectively input the test mode setting signal φCC, are replaced in the Data system control circuit 6a and OE system film stage circuit 7a.
This is the same as the conventional example.

The operation of this block is such that the address signal of the address terminal An is input to the test mode setting circuit 9 to enter the timing test mode of internal automatic refresh request signals φRA and φRR, and the test mode setting signal φCC is input to the NO of the data system control circuit 6a. 'CE input to one end of the R gate and one end of the OF system film stage circuit 7aN0IR gate,
Data system, CE system, and D that operate only when `` is activated.
Activates the ata amplifier and output buffer column, and inputs the data at the address specified by the row address generated by the internal address counter and the column address 0 or the last address, which is in the reset state because of the CEE activation state.
Output from /O terminal.

This data output time is not output unless the internal automatic refresh request signals φRA and φRR are output to specify the row address and activate the selected word line, so the data is output only during the word line activation period. that's why,
The internal automatic refresh cycle is determined by observing this output data.

By applying a voltage higher than the power supply voltage to one of the address terminals AO to An, the test moto setting signal φCC
occurs.

When the n-th address terminal An is from Ov to about the power supply voltage, the field effect transistors Qi+1 to Qi+j are turned on by the gate level control transistor group Ql, C2, C3, and C4, so the node N goes to Low level. The held signal φCC is also held at a low level.

When a voltage higher than the power supply voltage level is applied to address terminal An, diode-connected transistors Q5 to Q
All the transistors from i and Qi+1 to Qi+j are turned on, and the node N becomes a DC level determined by the ON of the transistors from C5 to Qi+j.

When this level exceeds the threshold voltage of the next-stage inverter 1, the signal φCC becomes the old gh level, and the test mode of the internal automatic refresh request signal generation cycle is entered.

FIG. 3 is a circuit diagram of the data system control circuit of FIG. 1.

The Data-related control circuit 6 & connects the NOR gate 01 which inputs the output signal φDD of the Data-related control circuit and the test mode signal φCC, which is the normal operation path during normal operation, to the first stage of the conventional Data-related control circuit 6 shown in FIG. It is installed instead of an inverter.

The NOR circuit 02 is enabled by the activation of the signal φDD into which the signal φCD of the refresh section 3b, which is generated during normal CEE conversion, or the main test mode setting signal φCC is activated, and the output signal φRD of the REFRESHE control circuit is activated (this In this case, the output signal φDE is activated.

As a result, each data block sequence decoder.

The Read-related control circuit, the Write-related control circuit, and the input/output buffer array are activated.

FIG. 4 is a circuit diagram of the OE system film stage circuit in FIG. 1, in which the inverter in the 72nd stage of the OE system film stage circuit in FIG. ■
5 is replaced with a NOR gate 03 connected to the output terminal of 5.

The NOR gate)03 inputs the 1-system activation signal φCD and the output signal φC8 of the first stage circuit of the chip select circuit C8.

Although it is controlled by the output signal φDS of the data-related control circuit, when the determination signal φCC of this test mode is activated, the output signal φOE is unconditionally activated.

Therefore, all data system circuits are normally activated only when CE- is activated, but by activating the test mode setting circuit 9 and entering the main test mode, the refresh terminal R
During internal refresh using the internal address counter by activation of FSH, the internal data system control timing is R.
It is controlled by the timing of the output signal φRD of the EFRESHE control circuit and is activated under the same operation sequence as the normal operation, and specified by the column side fixed address that remains inactive and the row address generated by the internal count. This means that the data of the cells to be read can be read.

FIG. 5 is a timing diagram of each signal for explaining the operation of the blocks in FIG. 1.

By keeping the refresh terminal RESH activated, the integrated circuit 1 enters the self-refresh mode, and the address terminal A
When a potential of power supply voltage +α is applied to n, internal automatic refresh request signal φRA is generated.

Data synchronized with the generation of φRH is, for example, I/O (1
) and output to the I/O (2) pin. Therefore, the cycle of the internal automatic refresh request signal can be checked.

FIG. 6 is a block diagram of a second embodiment of the invention.

In this embodiment, instead of the I/O control unit 4 in FIG. 1, the test mode setting signal φCC is sent from the OE system to the WE system film stage circuit 8 &
A modified I/O control section 4a is provided to perform a write operation by changing input data instead of outputting from an I/O bin.

WE system film stage circuit 8a As shown in FIG. 7, the conventional second stage inverter is replaced with NOR gate 05. Regardless of the signal, the W
The E-system first-stage signal φWE is activated, and the entire Write system, input buffer array, Write amplifier, etc. are all activated.

Therefore, if the self-refresh mode is entered upon activation of the refresh terminal RFSH and the address terminal An satisfies the condition of the power supply voltage voltage α, the row address determined by the internal address counter is different from that in synchronization with the activation of the internal automatic refresh request signal. Writing is performed to the cell specified by the fixed column address by activation.

By reading the data at this time later, the control state of the input data and input data width at this time is observed, and internal automatic refresh request signals φRA and φRR are set.
It is possible to check whether the timing of occurrence of the event satisfies the required level.

〔Effect of the invention〕

As described above, the present invention adds a test mode setting circuit to a conventional pseudo SRAM circuit, and outputs a test mode setting signal to a data system control circuit.

Data is input to the OEE control circuit and WE system first stage circuit and is output to the external I/O terminal at a timing synchronized with the generation of the internal automatic refresh request signal during self-refresh due to the refresh terminal being kept activated. This makes it easier to confirm the occurrence of and synchronously measure the internal automatic refresh request signal, which was previously impossible to measure directly from the outside, and is effective in improving the guaranteed quality of the product.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the first embodiment of the present invention, FIG. 2 is a circuit diagram of the test mode setting circuit of FIG. 1, and FIGS. 3 and 4 are the data system control circuit and FIG. OE system film stage circuit diagram; FIG. 5 is a timing chart of signals in each part to explain the operation of the blocks in FIG. 1; FIG. 6 is a block diagram of the second embodiment of the present invention; FIG. is AE in Figure 6
FIG. 8 is a block diagram of an example of a conventional memory integrated circuit. 1, la...Pseudo SRAM integrated circuit, 2...
...address section, 3a, 3b...
Refresh unit, 4... I/O control unit, 5...
...Memory array part, 6a...Data system control circuit, 7a...OE system film stage circuit 8a...
...WE system first stage circuit, 9...Test mode setting circuit, /O...RFSH first stage circuit, φCC...
...Test mode setting signal, φRA, φRR...
...Internal automatic refresh request signal, An...
・Nth address terminal, Ilo... I/O terminal, OE... Read enable terminal, RFSH...
...Refresh terminal. Agent: Susumu Uchihara, patent attorney Figure 2 Figure 3 Figure 4 Figure 7

Claims (1)

[Scope of Claims] A memory array section having a 1,1 transistor type dynamic cell, an address section that inputs address signals from a plurality of address terminals to control a decoder column of the memory array section, and a refresh signal from a refresh terminal. a refresh section that inputs an enable signal from a read enable terminal and outputs an internally automatically generated refresh signal to control the sense amplifier array and the address section of the memory array section; and a refresh section that inputs an enable signal from a read enable terminal to read data from the memory array section. In a pseudo static RAM memory integrated circuit having a plurality of I/O terminals having a plurality of I/O terminals, the memory integrated circuit is set to an automatic refresh mode by the refresh signal, and one of the address signals is input to set the test mode. A test mode setting circuit for outputting a signal is added, and means is provided for inputting and activating the test mode setting signal to a data system control circuit and a read control input circuit of the I/O control section, and the internal automatic refresh request is A memory integrated circuit characterized in that the data is output to the I/O terminal in synchronization with a signal. 2. A memory array section having a one-transistor type dynamic cell, an address section that inputs address signals from a plurality of address terminals to control the decoder array of the memory array section, and an internal automatic control section that inputs refresh signals from a refresh terminal. a refresh section that outputs a generated refresh signal and controls the sense amplifier array and the address section of the memory array 4 section; and a plurality of I/O terminals that input an enable signal from a read enable terminal to read data from the memory array main unit. in a pseudo static RAM memory integrated circuit having an I/O control unit having an I/O control unit, which enters an automatic refresh mode in response to the refresh signal, a test mode setting which inputs one of the address signals and outputs a test mode setting signal; A circuit is added, and means is provided for inputting and activating the test mode setting signal to a data system control circuit and a write control input circuit of the I/O control section, and activating the test mode setting signal in synchronization with the internal automatic refresh request signal. A memory integrated circuit characterized in that data input to the memory array section from an I/O terminal is output to the I/O terminal.