JPH0472740A - Ohmic electrode - Google Patents

Ohmic electrode

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Publication number
JPH0472740A
JPH0472740A JP18635090A JP18635090A JPH0472740A JP H0472740 A JPH0472740 A JP H0472740A JP 18635090 A JP18635090 A JP 18635090A JP 18635090 A JP18635090 A JP 18635090A JP H0472740 A JPH0472740 A JP H0472740A
Authority
JP
Japan
Prior art keywords
layer
type
layers
electrode
small
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18635090A
Other languages
Japanese (ja)
Inventor
Yasushi Shiraishi
靖 白石
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NEC Corp
Original Assignee
NEC Corp
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Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18635090A priority Critical patent/JPH0472740A/en
Publication of JPH0472740A publication Critical patent/JPH0472740A/en
Pending legal-status Critical Current

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  • Recrystallisation Techniques (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To make it possible to obtain an ohmic electrode, whose internal resistance is small and moreover, whose contact resistance can be made small, by a method wherein while the compositional ratios of indium in n-type InxGa1-x As layers and n-type InYGa1-Y as layers hold a constant relation, the compositional ratios of indium are gradually increased from the side of a GaAs substrate to the side of the surface and the surface is constituted of a superllatice layer, which consists of both n-type layers, and an electrode metal film formed on the superllatice layer. CONSTITUTION:An n-type InxGa1-x As layer 2 and an n-type In YGa1-Y As layer 3 are alternately laminated on a GaAs substrate and while both of compositional ratios X and Y of indium in those layers hold a relation of X<Y, the compositional ratios of indium are gradually increased from the side of the substrate toward the side of the surface and the surface is constituted of a superllatice layer 4, which consists of the n-type InxGa1-x As layers 2 and the n-type InYGa1-Y As layers 3, and an electrode metal film 6 formed on the layer 4. As an ohmic electrode has a structure, in which the compositional ratios of In in the layers 2 and 3 are gradually increased from the lower side of the layer 4 toward the surface, a large potential barrier does not exist and as a current flows as a tunnel current in the layer 4, the ohmic electrode having a small internal resistance is obtained. Moreover, as a compositional ratio of In in an n-type InGaAs layer 5, in which a com-positional ratio of In is large and which comes into contact to the electrode metal film 6, can be made sufficiently small, a potential barrier in the interface between the film 6 and the layer 5 can be made small and the contact resistance of the ohimc electrode can be made very small.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に係り、特にn型GaAsへのオー
ム性電極に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to an ohmic electrode for n-type GaAs.

〔従来の技術〕[Conventional technology]

n型GaAsへの低抵抗ノンアロイオーム性電極として
、GaAs基板上にn型I nGaAsのIn組成比を
基板側から表面に向かって徐々に増加させたI nGa
As傾斜組成層を形成し、表面をInの組成比の高いn
型InG’aAs層とし、その上に電極金属を設ける構
造が、例えばウラドール(Wooda l I >等に
よりジャーナル オブ バキューム サイエンス アン
ド テクノロジー(Journal of Vacuu
m 5cience and Technology)
19巻626頁(’1981年)に提案されている。
As a low-resistance non-alloy ohmic electrode for n-type GaAs, an InGaAs substrate with an In composition ratio of n-type InGaAs gradually increasing from the substrate side to the surface is used.
An As graded composition layer is formed, and the surface is coated with n having a high In composition ratio.
A structure in which a type InG'aAs layer is formed and an electrode metal is provided on the layer is described in the Journal of Vacuum Science and Technology by Woodal et al.
m 5science and Technology)
It is proposed in Vol. 19, p. 626 ('1981).

その電極構造におけるエネルギーバンド図を第3図に示
す。In組成比の高いI nx Ga1−XA55にお
いては禁制帯幅がGaAs 1に比べて非常に小さく、
n型に高濃度にドーピングした場合には金属6との界面
のポテンシャル障壁が非常に小さくなる。またこの構造
においてはGaAsとI nGaAsが傾斜組成層7で
つながれているため、GaAsとInGaAs層の間に
ポテンシャル障壁が存在せず、低抵抗のオーム性電極が
得られる。第4図に実線でこのようなI nGaAs傾
斜組成層を分子線成長法(以下MBE法と記す)にて形
成する場合のInおよびGaの分子線フラックス強度の
制御を示す。つまりInの分子線セルの温度を上げてI
nフラックス強度を増大させ、逆にGaの分子線セルの
温度を下げてGaフラックス強度を減少させることによ
りI nGaAs傾斜組成層を形成する。
An energy band diagram for this electrode structure is shown in FIG. In Inx Ga1-XA55 with a high In composition ratio, the forbidden band width is very small compared to GaAs 1.
When heavily doped to n-type, the potential barrier at the interface with metal 6 becomes extremely small. Furthermore, in this structure, since GaAs and InGaAs are connected by the graded composition layer 7, there is no potential barrier between the GaAs and InGaAs layers, and an ohmic electrode with low resistance can be obtained. In FIG. 4, solid lines indicate the control of the molecular beam flux intensities of In and Ga when such an InGaAs gradient composition layer is formed by the molecular beam growth method (hereinafter referred to as MBE method). In other words, by increasing the temperature of the In molecular beam cell, I
An InGaAs graded composition layer is formed by increasing the n flux intensity and conversely decreasing the Ga flux intensity by lowering the temperature of the Ga molecular beam cell.

またI nGaAs傾斜組成層の代わりにGaA s 
/ I n A s超格子層を用いる電極構造も、例え
ばペンダ(Peng)等によってアプライド フィジッ
クス レターズ(Applied Physics L
etters)第53巻900頁(1988年)に提案
されている。その電極構造におけるエネルギーバンド図
を第5図に示す。超格子の周期が短い場合、n型GaA
s層8とn型InAs層9とで成る超格子層10中をト
ンネル電流として電流が流れるため内部抵抗が小さく、
非常に低抵抗のオーミック電極が得られる。
Also, instead of the InGaAs graded composition layer, GaAs
Electrode structures using superlattice layers have also been described, for example, by Peng et al. in Applied Physics Letters.
etters), Vol. 53, p. 900 (1988). An energy band diagram of the electrode structure is shown in FIG. When the period of the superlattice is short, n-type GaA
Since current flows as a tunnel current through the superlattice layer 10 consisting of the s-layer 8 and the n-type InAs layer 9, the internal resistance is small.
An ohmic electrode with very low resistance can be obtained.

さらにGaAs/InAs超格子層の代わりにGaAs
/InGaAs超格子層を用いる方法が度板によって 
公開特許公報 平2−18965に提案されている。こ
の場合I nGaAs層は組成一定であるかあるいはI
n組成を下部から表面にかけて徐々に増加させてもよい
、In組成を増加させた場合のエネルギーバンド図を第
6図に示す。この方法によればn型GaAs層11とn
型I nGaAs層12とで成る超格子層13中に存在
するポテンシャル障壁はGaAs/InAs超格子層1
0の場合よりも小さく、より低抵抗のオーミック電極が
得られることが期待される。
Furthermore, GaAs/InAs superlattice layer is replaced with GaAs/InAs superlattice layer.
/The method using InGaAs superlattice layer is
This is proposed in Japanese Patent Publication No. 18965/1999. In this case, the composition of the InGaAs layer is constant or the I
FIG. 6 shows an energy band diagram when the In composition is increased, and the N composition may be gradually increased from the bottom to the surface. According to this method, the n-type GaAs layer 11 and the n-type
The potential barrier existing in the superlattice layer 13 consisting of the type I nGaAs layer 12 is the GaAs/InAs superlattice layer 1.
It is expected that an ohmic electrode that is smaller and has lower resistance than the case of 0 can be obtained.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来例で述べたようなオーミック電極においては、Ga
AsとInAsの格子定数差が約7%と大きいことによ
り困難が生じた。つまり傾斜組成層中や超格子層中に格
子定数差に起因する転位が発生しやすく、転位のまわり
に空乏層が広がり、内部抵抗が増大するという問題点が
あった。転位の発生を抑えるには、傾斜組成層の場合膜
厚を約300オングストローム程度と薄くし、また組成
変化をなめらかにする必要があった。このような構造を
MEB法で形成するためには、第4図に実線で示すよう
にInの分子線セルの温度を上げてInフラックス強度
を増大させ、逆にGaの分子線セルの温度を下げてGa
フラックス強度を減少させなければならない。しかし分
子線フラックス強度を短時間になめらかに制御すること
は困難であり、設計どうりの組成層が形成できず、組成
変化の急峻な部分が形成され転位が発生しやすくなるこ
とがあった。またInフラックスがオーバーシュートし
てInとAsの分子線フラックスの比が設計値と変わり
、InGaAsの結晶性が低下する原因ともなった。実
際のフラックス変化の一例を第4図に破線で示しである
。このように問題点が多いため、InGaAs層の構造
や厚さを自由に設計することができなかった。
In the ohmic electrode as described in the conventional example, Ga
Difficulties arose due to the large difference in lattice constant between As and InAs, about 7%. In other words, there is a problem in that dislocations due to lattice constant differences are likely to occur in the graded composition layer or superlattice layer, and a depletion layer spreads around the dislocations, increasing internal resistance. In order to suppress the occurrence of dislocations, it was necessary to reduce the film thickness to about 300 angstroms in the case of a gradient composition layer, and to smooth the compositional change. In order to form such a structure using the MEB method, the temperature of the In molecular beam cell is increased to increase the In flux intensity, and conversely, the temperature of the Ga molecular beam cell is increased, as shown by the solid line in Figure 4. Lower Ga
Flux intensity must be reduced. However, it is difficult to smoothly control the molecular beam flux intensity in a short period of time, and a designed compositional layer cannot be formed, resulting in the formation of parts with steep compositional changes, which tend to cause dislocations. In addition, the In flux overshooted and the ratio of the molecular beam fluxes of In and As changed from the designed value, which also caused a decrease in the crystallinity of InGaAs. An example of an actual flux change is shown in FIG. 4 by a broken line. Because of these many problems, it has not been possible to freely design the structure and thickness of the InGaAs layer.

傾斜組成層の代わりにGaAs/InAs超格子層を用
いる方法では、MBE法においてInとGaの分子線フ
ラックス強度を変える必要がない。しかし、InAsと
GaAsの格子定数差が約7%と大きいため転位の入ら
ない限界膜厚は5〜10オングストロームと非常に薄く
、転位の入らない超格子層を形成するにはI nAs 
1分子層/GaAs1分子層程度の超格子層が要求され
たにのような超格子層は成長条件が非常に難しく、転位
の入らない超格子層の成長は非常に困難であった。
In the method of using a GaAs/InAs superlattice layer instead of a graded composition layer, there is no need to change the molecular beam flux intensities of In and Ga in the MBE method. However, because the difference in lattice constant between InAs and GaAs is as large as approximately 7%, the critical film thickness at which dislocations do not form is extremely thin at 5 to 10 angstroms, and to form a dislocation-free superlattice layer, InAs is used.
The growth conditions for a superlattice layer such as that required for a superlattice layer of about one molecular layer/one molecular layer of GaAs are extremely difficult, and it has been extremely difficult to grow a superlattice layer free of dislocations.

またGaAs/InGaAs超格子層を用イル方法では
、GaAs/InAs超格子の場合より格子定数差が小
さく転位の入らない限界膜厚が厚くなり、超格子の形成
が容易である。しかし電極金属とInGaAs層の界面
のポテンシャル障壁を低くするためには、表面のI n
GaAsのIn組成を高くしなければならず、結局格子
定数差の大きい超格子層にならざるをえない。
In addition, in the case of using a GaAs/InGaAs superlattice layer, the difference in lattice constant is smaller than in the case of a GaAs/InAs superlattice layer, and the critical film thickness at which dislocations do not occur is thicker, making it easier to form a superlattice layer. However, in order to lower the potential barrier at the interface between the electrode metal and the InGaAs layer, it is necessary to
The In composition of GaAs must be increased, resulting in a superlattice layer with a large difference in lattice constants.

本発明の目的は、従来の欠点を除去したオーム性電極を
提供することにある。
An object of the present invention is to provide an ohmic electrode which eliminates the drawbacks of the prior art.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のオーム性電極は、G a A’ s上に形成さ
れる電極であって、n型I nx Ga1−x Asと
n型I ny Ga、イAsとが交互に積層され、それ
らのインジウム組成比XおよびYの両方がX<Yの関係
を保ちなからGaAs側から表面側に向けて徐々に増加
し、かつ表面をn型InYGa、−7Asとした超格子
層と、前記超格子層上に形成された電極金属とによって
構成されることを特徴とする。
The ohmic electrode of the present invention is an electrode formed on GaA's, in which n-type Inx Ga1-x As and n-type Iny Ga and As are alternately laminated, and their indium A superlattice layer in which the composition ratios X and Y both gradually increase from the GaAs side to the surface side while keeping the relationship X<Y, and the surface is made of n-type InYGa, -7As, and the superlattice layer. and an electrode metal formed thereon.

〔作用〕[Effect]

第1図は本発明のオーム性電極のエネルギーバンド図で
ある。超格子の下部から表面に向かって各層のIn組成
が徐々に増加する構造をもつため、大きなポテンシャル
障壁が存在せず、また超格子層中を電流がトンネル電流
として流れるため、内部抵抗の小さいオーム性電極が得
られる。
FIG. 1 is an energy band diagram of the ohmic electrode of the present invention. Because the structure has a structure in which the In composition of each layer gradually increases from the bottom to the surface of the superlattice, there is no large potential barrier, and current flows through the superlattice layer as a tunnel current, resulting in an ohmic film with low internal resistance. A sexual electrode is obtained.

また電極金属と接触するI nGaAsのIn組成比を
十分に小さくできるため、電極金属との界面におけるポ
テンシャル障壁を小さくでき、接触抵抗を非常に小さく
できる。
Furthermore, since the In composition ratio of InGaAs in contact with the electrode metal can be made sufficiently small, the potential barrier at the interface with the electrode metal can be made small, and the contact resistance can be made very small.

さらに超格子層において格子定数差の大きな界面が存在
しないため、超格子層の周期を長くしても転位が発生す
ることなく、超格子層の形成が容易である。例えばGa
As上のI n、、3 Ga(,7Asの限界膜厚は約
30オングストロームである。そのため、転位が発生す
ることなく超格子層の厚さを自由に変えることができる
Furthermore, since there is no interface with a large lattice constant difference in the superlattice layer, dislocations do not occur even if the period of the superlattice layer is lengthened, and the superlattice layer can be easily formed. For example, Ga
The critical thickness of In,,3Ga(,7As) on As is about 30 angstroms. Therefore, the thickness of the superlattice layer can be changed freely without generating dislocations.

〔実施例〕〔Example〕

次に、本発明の一実施例について図面を参照して説明す
る。
Next, an embodiment of the present invention will be described with reference to the drawings.

第1図は本発明のオーミック電極の一実施例を説明する
ためのエネルギーバンド図である。0型GaAs動作層
1上にn型I nXGa1−、(As層2とn型I r
ly Ga1−v As層3を交互に積層した超格子層
4が形成されている。超格子の周期は20オングストロ
ーム/20オングストロームとし、超格子層4の厚さは
全体で400オングストロームとする。n型I nX 
Ga1−x As層2のIn組成比XはGaAs動作層
1側から表面に向けて0から0.75に増加し、n型I
nYGat−yAsABO3n組成比は同様に0.5か
ら0゜8に増加する構造とっている6さらに超格子層4
上にIn組成比の大きいI nGaAs層として例えば
I n 6.B G a□、2 A 8層5が200オ
ングストローム形成されている。ドーピング濃度はn型
GaAs動作層1で2 X 1018cm−3とし、超
格子層4では徐々に増加し、 I n o、B G a
o、2 A 8層5においては2 X 1019cm−
3と高濃度にドーピングされている。I nr3.B 
G aQ2A s層5の上に例えばT i / P t
 / A uからなる金属多層膜を用いて電極金属6が
形成されている。Ino、BGaO,2As層5と電極
金属6とのポテンシャル障壁は理論上はとんど0に等し
く、電極金属と半導体層の熱処理による合金化を行わな
くても、十分に低抵抗なオーム性接触が得られる。
FIG. 1 is an energy band diagram for explaining one embodiment of the ohmic electrode of the present invention. n-type I nXGa1-, (As layer 2 and n-type I r
A superlattice layer 4 is formed by alternately stacking ly Ga1-v As layers 3. The period of the superlattice is 20 angstroms/20 angstroms, and the total thickness of the superlattice layer 4 is 400 angstroms. n-type I nX
The In composition ratio X of the Ga1-x As layer 2 increases from 0 to 0.75 from the GaAs active layer 1 side toward the surface, and the n-type I
The structure has a structure in which the nYGat-yAsABO3n composition ratio similarly increases from 0.5 to 0°8.6 Furthermore, the superlattice layer 4
For example, as an InGaAs layer with a high In composition ratio, for example, In6. B Ga □, 2 A 8 layers 5 are formed with a thickness of 200 angstroms. The doping concentration is 2 x 1018 cm-3 in the n-type GaAs working layer 1, and gradually increases in the superlattice layer 4.
o, 2 A 2 X 1019 cm- in 8 layers 5
It is doped at a high concentration of 3. I nr3. B
For example, T i /P t on the GaQ2A s layer 5
The electrode metal 6 is formed using a metal multilayer film made of /Au. The potential barrier between the Ino, BGaO, 2As layer 5 and the electrode metal 6 is theoretically almost equal to 0, and a sufficiently low resistance ohmic contact can be achieved without alloying the electrode metal and the semiconductor layer by heat treatment. is obtained.

この構造において、格子定数差の最も大きな界面はGa
As動作層1と超格子層4の界面であるが、それでも格
子定数差は約3.5%であり、周期を20オングストロ
ーム/20オングストロームと厚くしても転位の発生を
抑えられる。
In this structure, the interface with the largest lattice constant difference is Ga
At the interface between the As active layer 1 and the superlattice layer 4, the difference in lattice constant is still about 3.5%, and even if the period is increased to 20 angstroms/20 angstroms, the generation of dislocations can be suppressed.

第2図は本発明の一実施例として、MBE法においてI
nの分子線セルを1個、Gaの分子線セルを2個用いた
場合のオーミック電極の製造方法を説明するためのIn
およびGaの分子線フラックス制御を示した図である。
FIG. 2 shows an embodiment of the present invention in which I
In order to explain the manufacturing method of an ohmic electrode when one n molecular beam cell and two Ga molecular beam cells are used.
and FIG. 6 is a diagram showing molecular beam flux control of Ga.

MBE成長中の基板温度は500℃で一定とし、Asフ
ラックスは5.Ox 10””To r rで一定とす
る。n型GaAs動作層1を成長した後、超格子層4を
成長する。超格子層4成長中に第1のGaセルの温度を
800℃から740℃まで変化させ、その間にGaフラ
ックスは3.4×10−’Torrから1.7X10−
’Torrまで減少する。第2のGaセルは温度を74
0℃から710℃まで変化させ、その間にGaフラック
スは1.7X10−’Torrから6.8X10−8T
orrまで減少する。Inセル温度は例えば600°C
から640℃まで変化させ、その間にIpフラックスは
7.5X10−8Torrから1.5XIO−’Tor
rまで増加する。超格子の周期は20オングストローム
720オングストロームとし、超格子層4の厚さは全体
で400オングストロームとする。n型I nX Ga
p−)< As層2のIn組成比Xは動作層側から表面
に向けて徐々に例えば0から0.5に増加し、n型In
YGa、−。
The substrate temperature during MBE growth was kept constant at 500°C, and the As flux was 5. It is assumed that Ox is constant at 10"" Torr. After growing the n-type GaAs active layer 1, a superlattice layer 4 is grown. During the growth of the superlattice layer 4, the temperature of the first Ga cell was varied from 800°C to 740°C, during which the Ga flux was varied from 3.4 × 10-'Torr to 1.7X10-
'Decrease to Torr. The second Ga cell has a temperature of 74
The temperature was varied from 0℃ to 710℃, during which the Ga flux was changed from 1.7X10-'Torr to 6.8X10-8T.
decreases to orr. For example, the In cell temperature is 600°C.
to 640℃, during which the Ip flux was changed from 7.5X10-8Torr to 1.5XIO-'Torr.
increases to r. The period of the superlattice is 20 angstroms to 720 angstroms, and the total thickness of the superlattice layer 4 is 400 angstroms. n-type I nX Ga
p-)< The In composition ratio X of the As layer 2 gradually increases from, for example, 0 to 0.5 from the active layer side toward the surface, and
YGa, -.

As層3のIn組成比は同様に0.5がら0.8に増加
する構造となっている。さらに超格子層4上にI no
、s cao、2 As層5を例えば200オングスト
ローム形成する。n型GaAs動作層1においては2−
 X 1018am−3のSiドーピングを行い、超格
子層4ではドーピング濃度を徐々に増加させ、I n(
1,g Gao2As層5においては2×1019cm
−3と高濃度にドーピングしである。
Similarly, the In composition ratio of the As layer 3 increases from 0.5 to 0.8. Furthermore, I no on the superlattice layer 4
, scao,2 As layer 5 is formed to have a thickness of, for example, 200 angstroms. In the n-type GaAs active layer 1, 2-
Si doping of X 1018 am-3 is performed, and the doping concentration is gradually increased in the superlattice layer 4, and
1,g 2×1019 cm in Gao2As layer 5
It is doped at a high concentration of -3.

その上に例えばTi (500オングストローム)/P
t(500オングストローム) / A u(300オ
ングストローム)からなる金属多層膜を用いて電極金属
6が形成する。
On top of that, for example, Ti (500 angstroms)/P
Electrode metal 6 is formed using a metal multilayer film consisting of t (500 angstroms)/A u (300 angstroms).

以上説明した製造工程により、本発明の実施例のオーム
性電極を製造することができる。第2図のIn及びGa
の分子線フラックス制御の図に示されるように、セルを
2個用いて交互に開閉しているため、超格子層成長中に
セル温度を急激に変化させる必要がなく、分子線フラッ
クスの制御が容易である。つまり超格子層成長中のIn
およびGaの2個の分子線セルの温度制御は数10℃程
度であり、第4図に示した従来例において100℃以上
の制御を行わなければならないのに比べて、制御が容易
である。この場合、Inフラックスは大きく変化させる
必要がなく、一定でもよい。このように各分子線フラッ
クス強度の制御が容易であり、本発明の構造においては
設計どうりのオーム性電極を製造することができる。
The ohmic electrode of the embodiment of the present invention can be manufactured by the manufacturing process described above. In and Ga in Figure 2
As shown in the molecular beam flux control diagram, since two cells are used and are alternately opened and closed, there is no need to rapidly change the cell temperature during superlattice layer growth, and the molecular beam flux can be controlled. It's easy. In other words, In during superlattice layer growth
The temperature control of the two molecular beam cells of Ga and Ga is on the order of several tens of degrees Celsius, which is easier to control than in the conventional example shown in FIG. 4, which requires control over 100 degrees Celsius. In this case, the In flux does not need to be changed greatly and may be constant. In this way, the intensity of each molecular beam flux can be easily controlled, and with the structure of the present invention, an ohmic electrode can be manufactured as designed.

また本実施例においてはInセルを1個、Gaセルを2
個用いたが、■セル2個、Gaセル1個、あるいはIn
セル2個、Gaセル2個を用いてもかまわない、また基
板温度、各分子線セル温度および各分子線フラックス強
度、In組成、膜厚、ドーピング濃度等はここに示した
値である必要はない。通常のMEB装置いおいて同じソ
ースの分子線セルを2個設けることは、特に問題とはな
らない。
In addition, in this embodiment, there is one In cell and two Ga cells.
I used two ■cells, one Ga cell, or In
Two cells and two Ga cells may be used, and the substrate temperature, each molecular beam cell temperature, each molecular beam flux intensity, In composition, film thickness, doping concentration, etc. do not need to be the values shown here. do not have. In a normal MEB device, providing two molecular beam cells with the same source does not pose any particular problem.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明のオーム性電極においては、
第1図のエネルギーバンド図に示されるように、超格子
の下部がら表面に向がってIn組成が徐々に増加する構
造をもつため、大きなポテンシャル障壁が存在せず、ま
た超格子層中を電流がトンネル電流として流れるため、
内部抵抗の小さいオーム性電極が得られる。また電極金
属と接触するI nGaAsのIn組成比を十分に小さ
くできるため、電極金属との界面におけるポテンシャル
障壁を小さくでき、接触抵抗を非常に小さくできる。
As explained above, in the ohmic electrode of the present invention,
As shown in the energy band diagram in Figure 1, the In composition has a structure in which the In composition gradually increases from the bottom to the surface of the superlattice, so there is no large potential barrier, and Because the current flows as a tunnel current,
An ohmic electrode with low internal resistance can be obtained. Furthermore, since the In composition ratio of InGaAs in contact with the electrode metal can be made sufficiently small, the potential barrier at the interface with the electrode metal can be made small, and the contact resistance can be made very small.

さらに超格子層においても格子定数差の大きな界面が存
在しないため、超格子層の周期を長くしても転位が発生
することなく、超格子層の形成が容易である。そのため
、転位が発生することなく超格子層の厚さを自由に変え
ることができる。
Furthermore, since there is no interface with a large lattice constant difference in the superlattice layer, no dislocation occurs even if the period of the superlattice layer is lengthened, and the superlattice layer can be easily formed. Therefore, the thickness of the superlattice layer can be freely changed without generating dislocations.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を説明するためのエネルギー
バンド図、第2図はその製造方法を説明するためのMB
E法における各フラックス制御を示した図である。第3
図は第1の従来例を説明するためのエネルギーバンド図
であり、第4図は従来例の製造方法を説明するためのM
BE法における各フラックス制御を示した図である6第
5図は第2の従来例を説明するためのエネルギーバンド
図である。第6図は第3の従来例を説明するためのエネ
ルギーバンド図である。 1−・−n型GaAs動作層、2−n型InXGat−
XAs層、3−・−n型Iny Ga1−y As層、
4−−− n型I nX cl−X  As/n型I 
nY Ga1−yAs超格子層、5・・・In組成比の
大きいn型I nGaAs層、6・・・電極金属、7−
・−n型InG a A s傾斜組成層、8−= n型
GaAs層、9−′・n型InAs層、10 =−n型
G a A s / n型InAs超格子層、11 ・
n型G a A s層、12 ・n型InGaAs層、
13−n型G a A s / n型I n G a 
A s超格子層。
Figure 1 is an energy band diagram for explaining one embodiment of the present invention, and Figure 2 is an MB diagram for explaining its manufacturing method.
It is a figure showing each flux control in E method. Third
The figure is an energy band diagram for explaining the first conventional example, and FIG. 4 is an energy band diagram for explaining the manufacturing method of the conventional example.
FIG. 6, which is a diagram showing each flux control in the BE method, is an energy band diagram for explaining the second conventional example. FIG. 6 is an energy band diagram for explaining the third conventional example. 1-.-n-type GaAs operating layer, 2-n-type InXGat-
XAs layer, 3-/-n-type InyGa1-yAs layer,
4--- n-type I nX cl-X As/n-type I
nY Ga1-yAs superlattice layer, 5... n-type In GaAs layer with high In composition ratio, 6... electrode metal, 7-
・-n-type InGaAs gradient composition layer, 8-=n-type GaAs layer, 9-'.n-type InAs layer, 10=-n-type GaAs/n-type InAs superlattice layer, 11 ・
n-type GaAs layer, 12/n-type InGaAs layer,
13-n-type G a As / n-type In Ga
A s superlattice layer.

Claims (1)

【特許請求の範囲】[Claims]  GaAs基板上に、n型In_XGa_1_−_XA
sとn型In_YGa_1_−_YAsとが交互に積層
され、それらのインジウム組成比XおよびYの両方がX
<Yの関係を保ちながら前記基板側から表面側に向けて
徐々に増加し、かつ表面をn型In_YGa_1_−_
YAsとした超格子層と、前記超格子層上に形成された
電極金属とによって構成されることを特徴とするオーム
性電極。
On the GaAs substrate, n-type In_XGa_1_-_XA
s and n-type In_YGa_1_-_YAs are alternately stacked, and both of their indium composition ratios X and Y are
< Y gradually increases from the substrate side to the surface side while maintaining the relationship, and the surface is made of n-type In_YGa_1_-_
An ohmic electrode comprising a superlattice layer made of YAs and an electrode metal formed on the superlattice layer.
JP18635090A 1990-07-13 1990-07-13 Ohmic electrode Pending JPH0472740A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18635090A JPH0472740A (en) 1990-07-13 1990-07-13 Ohmic electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18635090A JPH0472740A (en) 1990-07-13 1990-07-13 Ohmic electrode

Publications (1)

Publication Number Publication Date
JPH0472740A true JPH0472740A (en) 1992-03-06

Family

ID=16186822

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18635090A Pending JPH0472740A (en) 1990-07-13 1990-07-13 Ohmic electrode

Country Status (1)

Country Link
JP (1) JPH0472740A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0624907A2 (en) * 1993-05-10 1994-11-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device, heterojunction bipolar transistor, and high electron mobility transistor
CN112750925A (en) * 2020-12-31 2021-05-04 广东省科学院半导体研究所 Deep ultraviolet LED device structure and preparation method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0624907A2 (en) * 1993-05-10 1994-11-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device, heterojunction bipolar transistor, and high electron mobility transistor
EP0624907A3 (en) * 1993-05-10 1995-05-03 Mitsubishi Electric Corp Semiconductor device, heterojunction bipolar transistor, and high electron mobility transistor.
US5459331A (en) * 1993-05-10 1995-10-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device, heterojunction bipolar transistor, and high electron mobility transistor
CN112750925A (en) * 2020-12-31 2021-05-04 广东省科学院半导体研究所 Deep ultraviolet LED device structure and preparation method thereof
CN112750925B (en) * 2020-12-31 2022-04-08 广东省科学院半导体研究所 Deep ultraviolet LED device structure and preparation method thereof

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