JPH0472732U

JPH0472732U -

Info

Publication number: JPH0472732U
Application number: JP11591990U
Authority: JP
Priority date: 1990-11-06
Filing date: 1990-11-06
Publication date: 1992-06-26

Description

[Brief explanation of the drawing]

第１図は、本考案の一実施例の回路構成を示す
図、第２図は第１図中のＲＡＭの構成を示す図、
第３図は、上記実施例の動作の概要を示すジエネ
ラルフローチヤート、第４図は第３図中の個別情
報受信処理を詳細に示すフローチヤート、第５図
は第３図中の共通情報受信処理を詳細に示すフロ
ーチヤート、第６図は第３図中の計時・タイマ処
理を詳細に示すフローチヤートである。１……受信アンテナ、２……受信部、３……デ
コーダ部、４……ビツト同期回路、５……誤り検
出訂正回路、６……シリアルパラレル変換回路、
７……フレームレジスタ、８……アドレスレジス
タ、９……アドレス比較回路、１０……プリアン
ブル検出回路、１１……フレーム同期信号ＳＣ_１検出回路、１２……フレーム同期信号ＳＣ_２検出
回路、１３……タイミング制御回路、１４……Ｉ
Ｄ−ＲＯＭ、１５……電子スイツチ、ＳＷ……電
源スイツチ、１６……電源電池、１７……オール
クリア回路、１８……ＲＡＭ、１９……ＣＰＵ、
２０……基準信号発生部、２１……キー入力部、
２２……スピーカドライバ、２３……スピーカ、
２４……ＬＥＤドライバ、２５……ＬＥＤ、２６
……表示バツフア、２７……表示部、ＢＲ……バ
ツフアレジスタ、ＰＤ……表示ポインタ、ＳＦ…
…時刻データ受信済フラグ、Ｄ……表示フラグ、
Ａ……アラームフラグ、Ｔ……タイマレジスタ、
Ｎ……受信数カウンタ、ＴＲ……計時レジスタ、
ＣＭ……受信情報記憶部、ＳＡ……呼種別情報エ
リア、ＭＡ……受信メツセージエリア、ＴＡ……
受信時刻エリア。 FIG. 1 is a diagram showing the circuit configuration of an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of the RAM in FIG. 1,
FIG. 3 is a general flowchart showing an overview of the operation of the above embodiment, FIG. 4 is a flowchart showing details of the individual information reception process in FIG. 3, and FIG. 5 is a general flowchart showing the common information in FIG. 3. FIG. 6 is a flowchart showing details of the reception process. FIG. 6 is a flowchart showing details of the clock/timer process in FIG. DESCRIPTION OF SYMBOLS 1... Receiving antenna, 2... Receiving section, 3... Decoder section, 4... Bit synchronization circuit, 5... Error detection and correction circuit, 6... Serial to parallel conversion circuit,
7...Frame register, 8...Address register, 9...Address comparison circuit, 10...Preamble detection circuit, 11...Frame synchronization signal SC ₁ Detection circuit, 12... Frame synchronization signal SC ₂ detection circuit, 13... Timing control circuit, 14...I
D-ROM, 15...Electronic switch, SW...Power switch, 16...Power battery, 17...All clear circuit, 18...RAM, 19...CPU,
20...Reference signal generation section, 21...Key input section,
22...Speaker driver, 23...Speaker,
24...LED driver, 25...LED, 26
...Display buffer, 27...Display section, BR...Buffer register, PD...Display pointer, SF...
...Time data received flag, D...Display flag,
A...Alarm flag, T...Timer register,
N...Reception number counter, TR...Time register,
CM...Reception information storage unit, SA...Call type information area, MA...Reception message area, TA...
Reception time area.

Claims

[Scope of claim for utility model registration] Clock means that receives power supply and starts measuring time, and when receiving a call, receives the received data,
reception data storage means for storing the received data in association with the time that the clock means is measuring at that time; and when current time information is received, the time that the clock means is measuring at that time and the received current time; A paging receiver with a clock function, characterized in that the paging receiver is equipped with a correction means for correcting the unadjusted time stored in the received data storage means and the time measured by the timekeeping means based on the difference between the received data storage means and the time measured by the timekeeping means.