JPH0470950A - Inter-cpu communication equipment - Google Patents

Abstract

PURPOSE:To attain the mutual communication among the CPUs with the transmission bit data that detected a communication error with high efficiency by transmitting in duplication the same transmission bit data among the CPUs and receiving these data by each CPU while comparing the contents of bits with each other. CONSTITUTION:A data transmission means including a command transmission system 1a and a status transmission system 2b transmits in duplication the transmission data bits set by the CPU A and B to other CPUs continuously by at least two bits. Then the data transmission means compares the transmission bit data received in duplication by the reception means 2a and 1b of the CPU A and B from other CPUs continuously by at two bits with each other for each bit in order to detect a communication error. As a result, the transmission bit data can be easily produced for effective detection of the communication errors compared with the processing where the data are transmitted with addition of a parity bit. Thus the communication processing is attained between both CPUs with the transmission bit data that can effectively detect the communication errors.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a communication device that transmits and receives data between CPUs, and particularly relates to a communication device that serially communicates predetermined data between CPUs.

[Prior Art 1] Conventionally, in an apparatus having a system configuration in which a plurality of CPUs are provided and each CPU executes data processing while serially communicating with each other, for example, a copying machine, each CPU is provided in each control section.
The PU is executing serial communication processing.

In this case, in a communication device that serially exchanges data between two CPUs, in order to improve the accuracy of communication, the transmitting side adds odd or even parity to the bit string of the transmitted data, and the receiving side adds parity to the bit string of the transmitted data. By checking whether the number of "1" pots in the data bit string is even or odd, it is checked whether there are any errors in communication.

Furthermore, simply checking whether the "1" bit of the data provided with the parity bit is an even number or an odd number as described above cannot deal with errors in even numbered bits, so transmission and reception are performed more than once.

Furthermore, when performing intra-device communication in an electrophotographic recording device, there is often a high-voltage power supply within the device, creating an environment that is extremely susceptible to noise.

[Problems to be Solved by the Invention] As described above, in conventional CPU-to-CPU communication processing, the transmitting side requires processing to add parity pits to the bit string of a series of data to be transmitted, and the receiving side
” processing is required to check the number of bits.

In addition, parity checking alone cannot deal with errors in even bits, so if transmission and reception are performed more than once, it is necessary to transmit two or more parity pits that are meaningless to the communication content, which may reduce communication efficiency. There was a problem.

This invention was made to solve the above problem, and each CPU repeatedly transmits the same transmission bit data to other CPUs, and while comparing the contents of each bit, By receiving the data from the CPU, each CPU can detect communication errors with high precision (detectable transmission bit data).
The purpose is to obtain low communication between CPUs in which U can communicate with each other.

[Means for solving the problem 1 In the CPU-to-CPU low communication according to the present invention, each CPU
data transmitting means for repeatedly transmitting the same transmission bit data as the transmission bit data set to other CPUs, and each CPU comparing each bit of the transmission bit data that is repeatedly transmitted from the other CPU. Each CPU is provided with a receiving means for receiving the data.

Further, the data transmitting means is configured such that each CPU repeatedly transmits a small number (two consecutive sets) of the same transmission bit data as the transmission bit data set for the other CPUs.

Further, the data transmitting means is configured such that each CPU repeatedly transmits each bit of the set transmission data bits to the other CPUs in a continuous manner at least two bits each.

[Operation] In this invention, when the same transmission bit data as the transmission bit data set to another CPU is repeatedly transmitted from the data transmission means of each CPU, the reception means of each CPU receives the transmission bit data from the other CPU. It is possible to detect communication errors by receiving while comparing each bit of transmitted bit data that is transmitted repeatedly.

Further, the data transmitting means repeatedly transmits at least two consecutive sets of transmitting bit data identical to the transmitting bit data set for each CPU to the other CPU, and the receiving means of each CPU receives two sets of transmitting bit data from the other CPU. To make it possible to detect a communication error by comparing each bit data while dividing transmission bit data that is continuously and repeatedly transmitted as a set into upper and lower parts.

Further, the data transmitting means repeatedly transmits each bit of the transmission data bits set to the other CPUs in a small number (2 bits in a row), and the receiving means of each CPU receives each bit from the other CPUs. It is possible to detect a communication error by comparing transmission bit data that is repeatedly transmitted bit by bit at least two bits in a row.

[Embodiment 1] Fig. 1 is a block diagram illustrating the configuration of low communication between CPUs showing an embodiment of the present invention.
Corresponds to serial communication with PUB, CPU
B performs processing upon receiving commands from the CPUA, and is configured to notify the CPUA of various information depending on the status.

In this figure, 1a is a command transmission system that converts the command in the command buffer 3a into a transmission format and outputs the command serially in synchronization with the clock generated by the oscillator 6a, and 2a is a status reception system that receives the status that is sent out. is fetched in synchronization with the clock generated by the oscillator 6a and written into the status buffer 4a. A main processing system 5a writes commands indicating instructions to the CPUB into the command buffer 3a as necessary based on the information in the status buffer 4a. Note that in this embodiment, the CPU
A. The basic clock for communication between CPUB is CPUA.
The signal is output from the side, and the oscillator 6a serves as the signal source.

The CPUB side receives the command sent from the command transmission system 1a in synchronization with the basic clock, writes it to the command buffer 3b, the command reception system 1b, the command buffer 3b, the status buffer 4b, and converts the status of this status buffer 4b into a transmission format. It is comprised of a status transmission system 2b that converts the data and sends it out in synchronization with the basic clock, a main processing system 5b that processes according to commands from a command buffer 3b, and writes status information to a status buffer 4b, and the like.

In addition, the signal CBSY between the above CPUA and CAUB
, 5BSY, DATA, and CLK are signal lines L, which will be described later.
1 to L4.

Below, each signal CBSY, 5BSY, DATA.

The function of CLK will be explained.

Signal CBSY: Indicates that the CPUA is sending a command, TR is sent when the CPUA is sending a command.
The UE transmits FALSE while not transmitting.

Signal 5BSY: Indicates that CPUB is transmitting status. TRUE is transmitted when CPUB is transmitting status, and FALSE is transmitted when CPUB is not transmitting status.

Signal DATA This is data including serial commands, serial status, etc.

Signal CLK corresponds to the basic clock output by the oscillator 6a of the CPUA.

In the inter-CPU communication device configured in this way, each C
Same as the transmission bit data set for other CPUs from the data transmission means (in this embodiment, command transmission system 1a, status transmission system 2b) of PU (in this embodiment, CP [between JA and CPUB)] When the transmission bit data of the CPUs are transmitted redundantly, the receiving means of each CPU (in this embodiment, the status receiving system 2a and the command receiving system 1b) compares each bit of the transmission bit data that is redundantly transmitted from the other CPUs. It is possible to receive and detect communication errors.

In addition, the data transmission means (in this embodiment, the command transmission system 1a and the status transmission system 2b) allow each CPU to communicate with other CPUs.
The same transmission bit data as the transmission bit data set for U is set to a smaller number (both 2
Duplicate transmission is performed in consecutive sets, and the receiving means of each CPU divides the transmitted bit data that is repeatedly transmitted in two consecutive sets from other CPUs into upper and lower parts, and compares each bit data to detect communication errors. make it possible.

FIG. 2 is a structural diagram showing an example of the inter-CPU data data shown in FIG.
This shows the bit data of commands and statuses recorded in, for example, the case of 4 bits. (b) shows the bit data transmitted from the command transmission systems 1a, 1b or the status transmission systems 2a, 2b. For example, the 4-bit bit data shown in (a) is arranged into the upper 4 bits and the lower 4 bits, resulting in a total of 8 bits. Send bit.

In this way, as shown in (b), the command receiving system 1b and the status receiving system 2a receive the bit data transmitted in the upper 4 bits and lower 4 bits, respectively, and receive the upper 4 bits and lower 4 bits of the command and status. The validity of the received data is checked by comparing the received data. Furthermore, when performing a parity check on the receiving side, it is known that the number is always an even number, so it is sufficient to confirm that the bit of ■ is an even number.

The data communication processing operation in the inter-CPU communication device according to the present invention will be described below with reference to FIGS. 3(a) and 3(b).

FIGS. 3(a) and 3(b) are flowcharts illustrating an example of a data communication processing procedure in the inter-CPU communication device according to the present invention. In addition, (1) to (7) and (11)
~(17) shows each step. Further, (a) in the same figure corresponds to the processing of the command sending system 1a, and (b) of the same figure corresponds to the processing of the command receiving system 1b.

In the command transmission system 1a, first, the signal CBSY is set to t.
rue and fl) in the command buffer 3a as shown in Figure 2 (
Read the command stored in the format shown in a) 2) and transmit it twice in succession in synchronization with the reference clock output from the oscillator 6a (3). As a result, the command is transmitted as an 8-bit command as shown in FIG. 2(b).

Next, the status receiving system 2a is notified of the end of command transmission 4), and the signal CBSY is set to false (
5). Next, the system waits until the status reception system 2a notifies the end of reception 6), and when it is notified, the signal 5BS
The process waits for Y to become false (7), and returns to step (1) when the signal 5BSY becomes false.

On the other hand, in the command receiving system 1b, the status transmitting system 2b
11), and waits for notification of the end of transmission from the signal C.
Wait for BSY to become true12), signal CB
When SY becomes true, status reception starts (13). Next, compare the upper 4 bits and lower 4 bits of the command sent in the format shown in Figure 2(b)14), and determine whether the upper and lower 4 bits are equal15). If so, proceed to step (17) onward, and if YES, convert it into the format shown in FIG. Return to (ll).

Each step above is performed by the command transmission system 1a in the CPUA.
The explanation has been given using the signal processing of the command receiving system 1b in the CPUB as an example, but the command, status, and signals CBSY and 5BSY are also reversed for the status transmitting system 2b in the CPUB and the status receiving system 2a in the CPUA, and the basic clock (signal CLK) is the signal CLK sent from the oscillator 6a of the CPUA, and the control is similar to that of the command transmission system 1a of the CPUA and the command reception system 1b of the CPUB.

By executing command and status transmission/reception processing in this manner, it is possible to easily check received data with increased accuracy.

In addition, in the above embodiment, as shown in FIGS. 2(a) and 2(b), the same bit data is transmitted to the upper 4 bits and the lower 4 bits, and the communication is performed by comparing each upper bit and lower bit. Although we have explained the case of determining an error, on the transmitting side, as will be described later, the basic clock (signal CLK)
It may be configured such that data of the same bit is transmitted continuously in clock cycles, and the receiving side determines whether or not the two bits are equal each time they are received, and if different data is received, the receiving process is terminated at that point.

That is, the data transmitting means (in this embodiment, the command transmitting system 1a and the status transmitting system 2b) transmits each bit of the transmitted data bits set by each CPU to the other CPUs as shown in FIG. The receiving means of each CPU compares each bit of transmitted bit data that is repeatedly transmitted with at least 2 consecutive bits from other CPUs to detect communication errors. enable detection.

FIG. 4 is a block diagram illustrating a signal interface of an inter-CPU communication device showing another embodiment of the present invention, and the same components as in FIG. 1 are given the same reference numerals.

In the figure, LLI and LL2 are interrupt lines, and the interrupt line LLI transmits an error signal DCERA to CPUB when the CPU recognizes a reception error. Also,
An error signal DCERB is sent to the interrupt line LL2 to the CPUA when the CPUB recognizes a reception error.

FIG. 5 is a structural diagram illustrating the structure of bit data transmitted by the signal line L3 shown in FIG. 4, in which data of the same bit is transmitted two consecutive clocks of the basic clock (signal CLK).

The data communication processing operation of the inter-CPU communication communication device according to the present invention will be described below with reference to FIGS. 6(a) and 6(b).

FIGS. 6(a) and 6(b) are flowcharts illustrating an example of a data communication processing procedure in the inter-CPU communication device according to the present invention. In addition, (11 to (8) and (11)
-(19) indicate each step.

In the command transmission system 1a, first, the signal CBSY is set to t.
rue 1) Insert the command buffer 3a in Figure 2 (
The command stored in the format shown in a) is read out (2), and data of the same bit is transmitted for two consecutive clocks in synchronization with the reference clock output from the oscillator 6a (3). During this time, the CPUA is monitoring whether or not the error signal DCERB has been input as an interrupt, and +41 YE
If S, return to step (3); if NO, notify the status receiving system 2a that command transmission has ended 5);
The signal CBSY is set to false (6). Next, the process waits until notification of the end of reception from the status receiving system 2a (7), and when notified, waits for the signal 5BSY to become false (8). When the signal 5BSY becomes false, the process returns to step (1). In this way, step (3)
In step (5), interrupts are enabled as soon as the command transmission starts, and in step (5), interrupts are disabled as soon as the transmission ends. During this time,
If the error signal DCERB from CPUB becomes true, the process returns to step (3) and the command is retransmitted.

On the other hand, in the command receiving system 1b, the status transmitting system 2b
11), and waits for notification of the end of transmission from the signal C.
Wait for BSY to become true12), signal CB
When SY becomes true, start receiving commands (
13).

Next, compare the two consecutive bits of the command sent in the format shown in Figure 5 (14) to determine whether there is a communication error (15), and if NO, change to the format shown in Figure 2 (a). Convert and write to command buffer 3a (
16), to notify the status transmission system 2b of the end of reception 1
7), return to step (11).

On the other hand, if it is determined in step (15) that there is a communication error, the error signal DCERB is set to true18), and then,
The error signal DCERB is set to false (19) and the process returns to step (13).

Note that the relationship between the command and the status, the relationship between the signal CBSY and the signal 5BSY, and the relationship between the error signal DCERA and the error signal DCERB are reversed in the status transmission system 1b on the CPUB side and the command reception system 2a on the CPUA side. , except that the basic clock is the external signal CLK, the command transmission system 1a of the CPU, the CP
The processing is similar to that of the UB command receiving system 1b.

[Effect of the invention 1 As explained above, this invention allows each CPU to communicate with other CPUs.
data transmitting means for repeatedly transmitting the same transmission bit data as the transmission bit data set for the CPU; and receiving means for each CPU to receive while comparing each bit of the transmission bit data transmitted repeatedly from other CPUs. and each CP
Since it is provided in U, it is possible to easily create transmission bit data that can effectively detect communication errors, compared to the conventional processing in which a parity bit is added and transmitted when transmitting data. Furthermore, since the receiving means receives the same transmitted bit data at least twice, communication accuracy is improved.

In addition, the data transmission means is configured so that each CPU transmits the same transmission bit data as the transmission bit data set to other CPUs in small quantities (two sets consecutively), so it is very simple. Through the transmission process, transmission bit data that can effectively detect communication errors can be created.

Furthermore, the data transmission means is configured such that each CPU repeatedly transmits each bit of the transmission data bits set to the other CPUs while making at least 2 bits consecutive. It is possible to create transmission bit data that can effectively and immediately detect communication errors.

Therefore, even in a system environment where high-frequency noise is extremely strong, effective communication processing between CPUs can be continued.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating the configuration of an inter-CPU communication device showing an embodiment of the present invention, and FIG. 2 is a structural diagram showing an example of the inter-CPU communication data shown in FIG. 1. , FIGS. 3(a) and 3(b) are flowcharts illustrating an example of a data communication processing procedure in the inter-CPU communication device according to the present invention, and FIG.
FIG. 5 is a block diagram illustrating the signal interface of the U-to-U communication device, and FIG. 6 is a structural diagram illustrating the structure of bit data transmitted by the signal line shown in FIG.
,,(b) is a flowchart illustrating an example of a data communication processing procedure in the inter-CPU communication device according to the present invention. In the figure, A and B are CPUs, la is a command transmission system, 2a is a status reception system, 1b is a command reception system, and 2b is a status transmission system. SB SB Figure 2 (a) (b) SB SB (a) Figure (b) Figure 4

Claims (3)

[Claims] (1) In an inter-CPU communication device in which each CPU serially communicates with each other, each CPU has a data transmitting means for redundantly transmitting the same transmission bit data as the transmission bit data set to other CPUs, and An inter-CPU communication device characterized in that each CPU is provided with a receiving means for receiving while comparing each bit of the transmission bit data transmitted redundantly from another CPU. (2) The data transmission means is characterized in that each CPU sequentially and repeatedly transmits at least two sets of transmission bit data that are the same as transmission bit data set for each CPU. communication device between CPUs. (3) The CPU according to claim (1), wherein the data transmitting means repeatedly transmits each bit of the transmission data bits set by each CPU to the other CPUs while making at least two consecutive bits. communication device.