JPH0470764U - - Google Patents
Info
- Publication number
- JPH0470764U JPH0470764U JP11390290U JP11390290U JPH0470764U JP H0470764 U JPH0470764 U JP H0470764U JP 11390290 U JP11390290 U JP 11390290U JP 11390290 U JP11390290 U JP 11390290U JP H0470764 U JPH0470764 U JP H0470764U
- Authority
- JP
- Japan
- Prior art keywords
- thick film
- hybrid integrated
- film hybrid
- dielectric substrate
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 4
- 238000005259 measurement Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 1
- 239000011521 glass Substances 0.000 claims 1
- 230000001681 protective effect Effects 0.000 claims 1
- 239000012528 membrane Substances 0.000 description 2
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
Description
第１図は本考案の実施例に係る厚膜混成集積回
路を示す平面図、第２図は従来の厚膜混成集積回
路の一例を示す平面図である。
１……誘電体基板、２……膜回路、３……抵抗
値測定用パターン、４……抵抗体、１１……誘電
体基板、１２……膜回路、１３……抵抗体。
FIG. 1 is a plan view showing a thick film hybrid integrated circuit according to an embodiment of the present invention, and FIG. 2 is a plan view showing an example of a conventional thick film hybrid integrated circuit. DESCRIPTION OF SYMBOLS 1...Dielectric substrate, 2...Membrane circuit, 3...Resistance measurement pattern, 4...Resistor, 11...Dielectric substrate, 12...Membrane circuit, 13...Resistor.
Claims (1)
護ガラスを設けた厚膜混成集積回路において、誘
電体基板の余白部分に抵抗値測定用パターンを備
えるとともに、該抵抗値測定パターンの形状を多
数の厚膜混成集積回路からなる集団において各々
同一になるよう形成したことを特徴とする厚膜混
成集積回路。 In a thick film hybrid integrated circuit in which a conductor, a resistor, and a protective glass are provided on the surface of a dielectric substrate, a resistance measurement pattern is provided in the blank area of the dielectric substrate, and the resistance measurement pattern has many shapes. 1. A thick film hybrid integrated circuit characterized in that a group of thick film hybrid integrated circuits are formed to be identical to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11390290U JPH0470764U (en) | 1990-10-30 | 1990-10-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11390290U JPH0470764U (en) | 1990-10-30 | 1990-10-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0470764U true JPH0470764U (en) | 1992-06-23 |
Family
ID=31861531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11390290U Pending JPH0470764U (en) | 1990-10-30 | 1990-10-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0470764U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61208805A (en) * | 1985-03-13 | 1986-09-17 | シャープ株式会社 | Manufacture of thin film wiring substrate |
| JPS62133792A (en) * | 1985-12-06 | 1987-06-16 | 株式会社日立製作所 | Thick film hybrid integrated circuit device |
-
1990
- 1990-10-30 JP JP11390290U patent/JPH0470764U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61208805A (en) * | 1985-03-13 | 1986-09-17 | シャープ株式会社 | Manufacture of thin film wiring substrate |
| JPS62133792A (en) * | 1985-12-06 | 1987-06-16 | 株式会社日立製作所 | Thick film hybrid integrated circuit device |