JPH0469968A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase the capacity of a semiconductor device and to improve yield and productivity by forming a first sidewall, forming a second sidewall, then opening a second capacitor contact window, and forming a contact window of a capacitor electrode with first source/drain regions by an SAC method. CONSTITUTION:Since an overetching for perforating an opening, i.e., a capacitor contact window is not always necessary at the time of forming a first sidewall 6S to be formed on the side of a gate electrode 4 according to manufacture of a semiconductor device, its withstand voltage is improved, and since a second capacitor contact window 12B is opened after a second sidewall 12S is formed, the sidewall 68 can hold a sufficient withstand voltage. Further, since the window 12B of a capacitor electrode 14 with first source/drain regions 7A is formed with the sidewall 12B provided on the sidewall 6S as a mask by a so-called an SAC method, the area of one memory cell is reduced to increase the capacity of the semiconductor device.

Description

[Detailed Description of the Invention] [Industrial Application-rn The present invention is a cliff conductor'! A device 1, especially for example DRAM
(Involved in manufacturing method C of 1" conductor measuring device such as Dynamic Sondano... Ak1! Su Me [su) etc.

[Summary of the Invention] The present invention relates to a method for manufacturing a conductor device.
Form an insulating layer j2, 61 on the first polycrystalline ゛↓′ conductor layer,
Lurite electrode formation t5. After that, the gate electrode (2) is covered with a mask 2 to form a low concentration source/1.rain region, and a first dielectric layer 11□.6 consisting of an insulating layer is formed on the side surface of the gate electrode. 102, Ge 1 electrode 11 1st
Nori Itotsu A-) Ii h', t-, Masuia and (
,,,,-(Sosu,t"t" 1% i",,,/
iiQ territory! lIJ forming 2, Gel 1 electrode, 1, first side wall I: C,', entire C formed in first absolute H layer z7 1. Otsu 2. ) Ha > 1st
0 oblique r; edge surface t, 'overall j1.゛-th:), form a polycrystalline 〛I'' conductor layer j22, and further □, ゛, ゛th ゛), form a conductor layer ij, , on the entire surface (1,
Forming the edge surface 12, forming the polycrystalline conductor layer of the 2nd C, 1st, 1' conductor layer, 4, 2nd, 3rd disassociation The first conductor layer and the second 5th edge layer, r
': 1st (') 4 Yaba N/S711.・Kukt] to fire ′〕7 intelligence-). Ij2 “Go2, 2nd 1st Theta Month”
20th) 41) 1 A-11-Ruk: J-S 1st, 28th, 2nd polycrystalline wheel in each window 1st (7) The first insulating layer and the core of the conductor layer and the first insulating layer, 10th), : capacitor E
1st contact: 4th communication to 5th: No 4 Yababi/ri, -
Drill 1 window j7ζ,', 1st rule and 2nd ten→・
Inside the Bashita contact window! j, JY in full (7,
A second and fourth polycrystalline i+'-conductor layer is formed. 4th after i
The polycrystalline semiconductor layer of 1. ．． ．． -Butter 7
2C2, the second insulating layer and the second sidewall
1. After removing the layer, the second polycrystalline semiconductor layer is removed into the desired pattern.1. 1,! , patterned and made of a fourth polycrystalline semiconductor layer 2'.
'A vine electrode layer is formed. Steps 1 and 2: Form a dielectric layer on the surface of each capacitor electrode layer. 2) Form a fifth polycrystalline "1"6 conductor layer on the entire surface through this dielectric layer. By patterning this 2 and forming a counter electrode 4, it is possible to increase the capacity of the semiconductor device and improve the accuracy.

[Conventional technology]

The semiconductor device 111 RA Pl is composed of an array of memory cells consisting of a switching transistor, a so-called L transistor, a λ40S (insulated G-1 type field effect L sympathizer 2 star), and a capacitor. .

In recent years, efforts have been made to increase the memory capacity of 1" conductor devices, and along with this, the reduction of the memory cell area is beneficial.
It is requested. For example, in order to realize a 16 Mbit LILRAM or a 64 Mbit DRAM, the area of 1 memory cell must be 4 μm2 or more.
J-like, master-C Within a small area, famous T: IJ
4! C3' in the name 1 - separator or contact 1
Various manufacturing methods and structures have been proposed to form the window reliably and to sufficiently maintain the capacitance of the window.

The manufacturing method of an example of the semiconductor device 11 RAM (I) will be explained with reference to the process diagram of FIG. 2A and 0.

In this example, in order to make the surface area of the electrode layers constituting 4 layers, each lamination of the electrode layer 1. c configuration φru, Iwari)
1-2) Yaba-Nta type 011 A 1
If you get 1, you need to use the fine me+sp as mentioned above.
To get le. Mask fit 1↓5A to reduce tolerance
Adopt the C (Self-Ally, Ment 1:/Tatato) methodj7. This shows the case where

First, as shown in Figure 2, a 4 mm substrate (1) made of Si, etc. is heated 2. by, for example, thermal oxidation. Thick S
Elementary separation layer (2) consisting of i, 02, etc., so-called 1, ,
, OCOS is formed, and then a thinner dielectric layer (3) is formed by thermal oxidation.

As shown in Figure 2B, for example, a low resistivity polycrystalline Si layer and a 5iOz layer are laminated and patterned into two required patterns, for example, a pair of transfer・A pair of gate electrodes that constitute a gate transistor (
4) and an insulating layer (35A) is formed. Next, using the gate electrode (4) and the insulating layer (35A) as masks, impurities of the first conductivity type, for example, n-type As, are implanted at a low concentration.
A first low concentration source/drain region (58) of each transfer gate transistor of a pair of memory cells and a common second low concentration source/drain region (5B
) to form.

Then, as shown in FIG. 2C, an insulation M (35B) made of SiO□ or the like is applied over the entire surface.

Thereafter, as shown in the second diagram, anisotropic etching such as RIE (reactive ion etching) is performed until the surface of the substrate (1) is exposed. At this time, the side walls of the gate electrode (4) and the insulating layer (35A) are not etched away because the thickness of the insulating layer is substantially large, and sidewalls (355) are formed. , an opening (3) is formed between the sidewall (35S) between the pair of gate electrodes (4).
5C) and a side wall (35S) outside both gate electrodes (4) and a thick element isolation layer (2).
An opening (35D) is formed between. In this case, over-etching is performed so that the insulating layer (35B) does not remain within both openings (35C) and (35D).

And through these openings (35C) and (35D)
Impurities such as s are implanted to form first and second source/l/rain regions (78) and (7B).

After that, as shown in Figure 2E, the sidewall (35
For example, a low resistivity polycrystalline Si layer is deposited on the entire surface including the predetermined source/drain region (78) where the capacitor is to be connected through S), and this is coated as required by photolithography or the like. A capacitor electrode (14) is obtained by patterning the capacitor electrode (14).

As shown in FIG. 2F, for example, SiO□5iN-
A dielectric layer (15) made of 5iO□ is deposited on the entire surface,
Furthermore, after depositing, for example, a low resistivity polycrystalline Si layer through this dielectric layer (15), this is patterned into a desired pattern to form a counter electrode (16).

Next, as shown in FIG. 2G, the entire surface is covered with, for example, a thick film.
An insulating layer (17) consisting of G is deposited by a CVD (Chemical Vapor Deposition) method or the like, and this insulating layer (17) and a dielectric layer (17) are formed on the second source/drain region (7B).
5) through which a bit contact window (18) is drilled. Then, a wiring layer (19), ie, a bit line, made of AI or the like is formed on the entire surface including the inside of this bit contact window (I8), thereby obtaining a semiconductor device (30).

In a semiconductor device manufactured by such an SAC method, the convergence of the opening (<35D) in the second diagram mentioned above can be made relatively small;
Since over-etching is required to reliably form the sidewall (35D), there is a risk that the withstand voltage characteristics of the sidewall (35S) will deteriorate due to RIE at this time, resulting in a decrease in yield.

In addition, as described above, openings (35C) and (35D)
The width of the opening (35C) is regulated in a self-aligned manner by the distance between the sidewalls (35S) or between the sidewall (35S) and the element isolation layer (2).
and (35D) are formed into sidewalls (35S) and openings (35C) or (35D) by applying photolithography.
), the so-called helirad contact method is used to maintain the required spacing between the sidewalls (3
5S) and the openings (35C) and (35D), the breakdown voltage can be improved. Due to limitations arising from necessity, the width of the opening (35D) cannot be reduced to about 0.6 μm or less, which impedes the reduction of the area occupied by the memory cell.

Furthermore, in a star-socket capacitor type DRAM, the capacitor electrode has a structure with multiple fins to increase its surface area and reduce the area occupied by one memory element, but it is not possible to sufficiently increase the capacitance of the capacitor. A structure has been proposed to obtain

In the manufacturing method of DRAM with such a fin structure, in order to avoid damage to the underlying layer, such as the base (1) or the element isolation layer (2), when removing the insulating layer between the plurality of fins. For example, an insulating layer made of SiN is provided. However, due to the strain and stress caused by this SiN layer, the fin-structured capacitor electrode tends to break, resulting in a decrease in yield and productivity.

[Problems to be Solved by the Invention] The present invention solves the above-mentioned problems and avoids deterioration of the characteristics of a semiconductor device. We aim to increase capacity and improve yield and productivity.

[Means to solve the problem]

An example of the method for manufacturing a semiconductor device according to the present invention is shown in FIGS.
This is shown in the process diagram.

In the present invention, as shown in FIG. 1A, a gate insulating layer (3)
A process of forming a gate electrode (4) using the first polycrystalline semiconductor layer, and a process of forming a low concentration source/drain region (5A) and (5A) using this gate electrode (4) as a mask.
B), and as shown in FIG.
) and the first sidewall (6S) as masks to form source/drain regions (7A) and (7B), and as shown in FIG.
The first insulating layer (
8), a step of forming a second polycrystalline semiconductor layer (9) entirely on the first insulating layer (8), and a step of forming a second polycrystalline semiconductor layer (9) on the first insulating layer (8). Polycrystalline semiconductor layer (9)
forming a second insulating layer (10) over the entire surface;
A step of forming a third polycrystalline semiconductor layer (11) entirely on the second insulating layer (10);
11) and the second insulating layer (1,0), and forming a first capacitor contact window (12A) on the inner periphery of the first capacitor contact window (12^). 1. As shown in FIG. 9) and the first insulating layer (
8) drilling a second capacitor contact window (12B) that communicates with the first capacitor contact window (128); and forming the first and second capacitor contact windows (12A) and (12B). A step of forming a fourth polycrystalline semiconductor layer (13) on the entire surface including the inside, and a step of patterning the fourth polycrystalline semiconductor layer (13) into a desired pattern as shown in FIG. 1F. and a second insulating layer (10)
and a step of removing the second sidewall (12S), patterning the second polycrystalline semiconductor N (9) into a desired pattern, and combining this with the patterned fourth polycrystalline semiconductor layer (13). A step of forming a dielectric layer (15) on the surface of this capacitor electrode layer (14) as shown in FIG. A step of forming a fifth polycrystalline semiconductor layer over the entire surface and patterning it to form a counter electrode (16) is performed.

[Effect]

As described above, according to the method for manufacturing a semiconductor device of the present invention, an opening, that is, a capacitor contact window, is not necessarily formed in the first sidewall (6S) formed on the side surface of the gate electrode (4). Since there is no need for over-etching, the voltage resistance is improved, and the second capacitor contact window (12B) can be formed after forming the second sidewall (12S). From what is done, the first sidewall (6S
) can maintain sufficient pressure resistance.

Furthermore, a contact window (12B) between the capacitor electrode (14) and the first source/drain region (7A) is formed in the first source/drain region (7A).
SΔC using the second sidewall (12S) provided on the sidewall (6S) as a mask
Since the contact windows are formed by a method, it is possible to form contact windows with a spacing smaller than the transport limit of photolithography technology, for example. This makes it possible to reduce the area of one memory element and increase the capacity of semiconductor devices. It can be measured.

Furthermore, even if over-etching is performed when forming this capacitor contact window (12S), the first sidewall (6S) is protected by the second sidewall (12S), so its breakdown voltage characteristics are It also has the characteristics of the Helirad contact method described above without any deterioration.

Furthermore, according to the manufacturing method of the present invention described above, the capacitor electrode (
14) are the second and fourth polycrystalline semiconductor layers (9) and (1
Since the multiple fin structure according to 3) is adopted, it is possible to increase the capacitance of the capacitor per 1 memory element.

In addition, when removing the second insulating layer (1, 0) and the second sidewall (], 2S) in forming the capacitor electrode (14) having such a fin structure,
Since the second polycrystalline semiconductor layer (9) completely covers the base layer and the base (1), the base layer, that is, the first insulating layer (8)
There is no need to protect the element isolation layer (2) and the like with another insulating layer such as SiN. Therefore, it is not affected by stress caused by such an insulating layer,
Capacitor electrodes can be stably formed, and productivity can be improved.

〔Example〕

An example of a method for manufacturing a semiconductor device, particularly a DRAM, according to the present invention will be described in detail below with reference to the manufacturing process diagrams of FIGS. 1A to 1G.

In this example, as shown in FIG.
When one source/drain region of a second conductivity type, for example, n-channel MO3, constituting a pair of memory cells is formed in common on a base region of a first conductivity type, for example, p-type, of a substrate (1) made of a single crystal. shows.

(2) consists of a Sing formed by thermal oxidation, for example, and is an element isolation layer so-called L that isolates each memory cell.
a cos, (3) is a gate insulating layer made of a thin SiO2 film formed, for example, by thermal oxidation, and (4) is a gate electrode formed by patterning, for example, a low resistivity polycrystalline 5iJl into a desired pattern. Using this Day 1 electrode (4) as a mask, an n-type impurity such as As is ion-implanted to form the first and second lightly doped source/drain regions (
5^) and (5B) are formed.

Next, as shown in FIG. 1B, a thick insulating layer made of, for example, SiO□ is deposited over the entire surface of the gate electrode (4) by CVD.
After formation by a method such as a method, a first site "wall (6S) is formed on the side surface of the gate electrode (4) by performing anisotropic etching such as RIE. In this case, each source/drain region (58) and Since some insulating layer may remain on (5B), over-etching is not required to form the first sidewall (6S). Using the gate electrode (4) and □ element isolation layer (2) as a mask, an n-type impurity such as P is added.
ions are implanted to form first and second source/drain regions (7A) and (7B).

As shown in FIG. 1C, the first insulating layer (8) is entirely made of, for example, a SiO□ thin film and is made of, for example, a highly dense Si film made of TE01 (tetraethyl orthosilicate).
After forming the O□ layer, a second polycrystalline semiconductor layer (9) made of, for example, a low resistivity polycrystalline Si layer is deposited over the entire surface.

Next, as shown in the first diagram, the second polycrystalline semiconductor layer (9) is entirely covered with SiO! A second insulating layer consisting of (
After forming a third polycrystalline semiconductor layer (11) made of, for example, a low resistivity polycrystalline Si layer, the second insulating layer (10) and The third polycrystalline semiconductor layer (11) is patterned into a desired pattern to form a first capacitor contact window (12Δ). Then, a second sidewall (12S) made of an insulating layer, for example, 5in2, is formed within the first capacitor contact window (12A). This second sidewall (12S) is entirely made of Si, including, for example, the inside of the first capacitor contact window (12^).
After depositing the O□ layer by CVD or the like, anisotropic etching such as RIE is performed until the surface of the third polycrystalline semiconductor layer (11) is exposed.

Then, as shown in FIG.
After removing the second polycrystalline semiconductor layer (9) in 2A),
Subsequently, the first insulating layer (8) is light etched to form a second capacitor contact window (12B). This etching removes the third polycrystalline semiconductor layer (11). Then, a fourth polycrystalline semiconductor layer (13) made of low resistivity polycrystalline Si or the like is deposited over the entire surface including the inside of this second capacitor contact window (12B).

At this time, the second capacitor contact window (12B) is designed so that its width l is smaller than the width of the first sidewall 6S).

Then, as shown in FIG. 1F, a fourth polycrystalline semiconductor layer (
13) into a desired pattern by applying photolithography, and further removing the second insulating layer (10) and the second sidewalls (1, 23) by isotropic etching, the second polycrystalline The semiconductor layer (9) is
The fourth polycrystalline semiconductor layer (13) and the second
A capacitor electrode (14) having a so-called double fin structure is formed by forming a polycrystalline semiconductor layer (10).

Next, as shown in FIG. 1G, after a dielectric layer (15) made of, for example, 5iN-5iO□ is deposited on the entire surface, a fifth polycrystalline semiconductor layer (15) made of a low resistivity polycrystalline Si layer ( 1,6
After coating A) on the entire surface, it is patterned into a desired pattern to form a counter electrode (16).

After an insulating layer (17) made of, for example, As-doped low-melting glass is deposited on the entire surface, a via contact window is formed on the second source/train region (7B) to connect the pin I-line. (18) is drilled by anisotropic etching such as RIE. Furthermore, the insulating layer (17) is melted at a low temperature to smooth the corners of the bit contact window (18), and then the bit contact window (18) is formed by sputtering or the like.
18) Be sure to embed the inside! Wiring layer (19
) to obtain a semiconductor device (30).

In the semiconductor device (30) thus formed, since the first sidewall (6S) is not subjected to over-etching by RIE, it is possible to configure a MOS having sufficient breakdown voltage.

In addition, the second capacitor contact window (12B) is connected to the SAC
As shown in FIG. 1G, the convergence p of the second capacitor contact window (12B) can be
can be reduced to approximately 0.2 μm, which is much smaller than 0.6 μm in the case of conventional contact windows formed by photolithography, for example. The area can be reduced.

Further, according to the present invention, as described above, a capacitor electrode (14) having a fin structure can be obtained, and even if the area of the memory element groove is small, sufficient electric capacitance can be maintained.

Furthermore, after forming the upper fin of this capacitor electrode layer (14), the second insulating layer (10) and the second insulating layer (10) below this are formed.
The etching stopper when removing the sidewall (125) by etching is the second polycrystalline semiconductor layer (125).
9). Therefore, the capacitor electrode (14) having a fin structure can be formed without straining the underlying layer, such as the base or the element isolation layer (2).

〔Effect of the invention〕

As described above, according to the method for manufacturing a semiconductor device of the present invention, there is no need to over-etch the first sidewall (6S) formed on the side surface of the gate electrode (4) during its formation. , since the improvement of the voltage resistance is hindered and the second capacitor contact window (12B) is formed after forming the second sidewall (12s), the J-th sidewall (6S) can maintain sufficient pressure resistance.

Furthermore, since the contact window (12B) between the capacitor electrode (14) and the first source/train region (7A) is formed by the so-called SAC method, the contact window can be formed with a spacing that is below the limit of photolithography technology, for example. As a result, the area of one memory element can be reduced, and the capacity of the semiconductor device can be increased.

Furthermore, even if over-etching is performed when forming this capacitor contact window (12S), the first sidewall (6S) is protected by the second sidewall (12S), so 2. It also has the characteristics of the Veri-Rad contact method described above without deteriorating its breakdown voltage characteristics.

Furthermore, when removing the second insulating layer (10) and the second sidewall (125), since the second polycrystalline semiconductor layer (9) completely covers the base layer and the base, The underlying layer, that is, the first insulating layer (8), the element isolation layer (2), etc., is not affected by stress etc. (The capacitor electrode with the fin structure can be stably formed. It is possible to maintain a sufficient electric capacity per memory element and to improve productivity.

[Brief explanation of drawings]

1A to 1G are manufacturing process diagrams showing a method for manufacturing a semiconductor device according to the present invention, and FIGS. 2A to 2G are manufacturing process diagrams showing a conventional method for manufacturing a semiconductor device. (]) is a substrate, (2) is an element isolation layer, (3) is a gate insulating layer, (4) is a gate electrode, (5A) and (5B) are first and second low concentration source/drain regions, (6S) is the first sidewall, (7A) and (78) are the first and second source/drain regions, (8) is the first insulating layer, and (9) is the second polycrystalline semiconductor layer. , (10) is the second insulating layer, (11) is the third polycrystalline semiconductor layer, (12^) is the first capacitor contact window, (1,23) is the second sidewall, (1, 2B) is the second capacitor contact window, (13) is the fourth polycrystalline semiconductor layer, (14)
is a capacitor electrode layer, (15) is a dielectric layer, (16) is a counter electrode, (17) is an insulating layer, (18) is a bit contact window, (19) is a wiring layer, (35A) is an insulating layer, ( 3
5B) is an insulating layer, (35C) and (35D) are openings, (
35S) is a side wall, and (30) is a semiconductor device.

Claims (1)

[Claims] A step of forming a gate insulating layer, a step of forming a gate electrode using a first polycrystalline semiconductor layer, a step of forming a low concentration source/drain region using the gate electrode as a mask, and the gate electrode. forming a first sidewall made of an insulating layer on a side surface of the gate electrode; forming a source/drain region using the gate electrode and the first sidewall as a mask; a step of forming a first insulating layer over the entire surface of the sidewall; a step of forming a second polycrystalline semiconductor layer over the entire surface of the first insulating layer; and the second polycrystalline semiconductor layer. a step of forming a second insulating layer over the entire surface; a step of forming a third polycrystalline semiconductor layer over the entire surface of the second insulating layer; forming a second sidewall made of an insulating layer around the inner periphery of the first capacitor contact window; A second capacitor contact window communicating with the first capacitor contact window is formed in the second polycrystalline semiconductor layer in the first capacitor contact window having a wall and the first insulating layer thereunder. forming a fourth polycrystalline semiconductor layer over the entire surface including inside the first and second capacitor contact windows; and patterning the fourth polycrystalline semiconductor layer into a desired pattern. and removing the second insulating layer and the second sidewall, patterning the second polycrystalline semiconductor layer into a desired pattern, and combining this with the patterned fourth polycrystalline semiconductor layer. forming a dielectric layer on the surface of the capacitor electrode layer; forming a fifth polycrystalline semiconductor layer entirely through the dielectric layer; A method for manufacturing a semiconductor device, comprising the steps of patterning and forming a counter electrode.