JPH0469950A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to estimate the capacitances of wirings accurately, by providing a conductor layer having a constant potential between an n-th wiring layer from the side of a semiconductor substrate and an (n+1)-th wiring layer. CONSTITUTION:A conductive layer having a constant potential is provided between an n-th wiring layer from an m-th one of m wiring layers and an (n+1)-th one (where 2<=n<=m-1, n is an integer). The wiring layers are shielded from each other electrically by the conductor layers. For example, on a substrate 105, from the side of the substrate, a first layer wirings 101, a grounded shield layer 107, a second layer wirings 102, the grounded shield layer 107, a third layer wirings 103, etc., are formed in the described order. The respective layers are isolated electrically from each other by insulators 106, and if necessary, are connected electrically with each other by a through hole 104 between 1-2 layers, etc. Capacitances, 111, 113 between the second layer wiring and the shield layers are constant, regardless of the wiring patterns and the potential states of the upper and lower layers thereof, and come into the values proportional to the area of the second layer wiring 102. Therefore, by considering a capacitance 112 between the two adjacent second layer wirings together with the capacitances 111, 113, the capacitances of the second layer wirings 102 can be calculated from only the layout pattern of the second layer wirings 102.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a gate array semiconductor device having multilayer wiring.

[Conventional technology]

Conventionally, when this type of gate array semiconductor device has three-layer signal wiring, as shown in FIG.
It has a first layer wiring 301, a second layer wiring 302, and a third layer wiring 303 that are electrically separated by a wire 06, and has a through hole 304 that electrically connects each layer.

When configuring a logic LSI using the wiring structure shown in FIG. 3, the capacitance parasitic to the wiring is, taking the second layer wiring as an example, ■ the capacitance between the second layer wiring and the board Ji311,
There are three types of capacitance: capacitance 310 between the second layer wiring, and capacitance 312 between the second layer wiring and the third layer wiring. Since it changes depending on the potential state of the upper and lower layers, it is extremely difficult to accurately estimate the capacitance from the layout pattern. In particular, in the case of a random logic LSI, since the combinations of wiring patterns are random, a huge amount of calculation is required to design accurate delay values. Also, in the figure, 307
is the capacitance between the first layer wiring and the board, 308 is the capacitance between the 1Nth wiring, 309 is the capacitance between the first layer wiring and the second layer wiring, 31
3 is the capacitance between the third layer wiring, 314 is the capacitance between the third layer wiring and the first layer wiring R, and 315 is the capacitance between the third layer wiring and the substrate.

[Problem to be solved by the invention]

In this conventional semiconductor device, the wiring layers are not electrically shielded, so when calculating the parasitic capacitance of the signal wiring, the layout pattern of the wiring in the upper and lower layers must be considered, and the potential state of the wiring in the upper and lower layers must be considered. must also be taken into account, which requires a huge amount of calculation. In particular, in the case of a random logic system such as a gate array, it is virtually impossible to accurately estimate the glabella capacitance because the combination of wiring patterns cannot be specified.

An object of the present invention is to provide a semiconductor device that allows accurate estimation of wiring capacitance.

[Means to solve the problem]

In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device having m wiring layers (m≧2, m is an integer), and has an nth (1≦1) wiring layer from a semiconductor substrate m1.
n≦m−1. A conductor layer to which a constant potential is applied is provided between the wiring layer (n is an integer) and the (n+1)th wiring layer.

[Effect]

Between the n-th wiring layer and the n+1-th wiring layer from the bottom among the m wiring layers (2≦n≦m-1, n is an integer), there is a conductive layer given a constant potential, and the wiring Shielding electrical influences between layers.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

(Example 1) FIG. 1 is a sectional view showing Example 1 in which the present invention is applied to a semiconductor chip having three-layer wiring.

In the figure, a first layer wiring 101, a grounded shield N1107, a second layer wiring 102, a grounded shield layer 107, and a third layer wiring 103 are placed on a substrate 105 on which transistor elements and the like are formed. The layers are formed in sequence, and each layer is electrically isolated by an insulator 106, and electrically connected by a 1-2 layer through hole 104 or the like as necessary.

In this embodiment, taking the parasitic capacitance of the second layer wiring 102 as an example, the capacitance between the second layer wiring and the shield layer 111, 1
13 is constant regardless of the wiring pattern and potential state of the upper and lower layers, and has a value proportional to the area of the first layer wiring 10102. Therefore, together with the capacitance 112 between the second layer wiring, the second layer wiring 102 It becomes possible to calculate the wiring capacitance from the layout pattern.

Consider a case where the second layer wirings 102 are arranged in parallel with the minimum line width and minimum pitch. 2nd N in practical level! Minimum wiring width 1.8 μm, fi small spacing 1.2 μm, thickness 0.8 μm,
Assuming that the distance between the second layer wiring and the shield layer is 0.4 μm and the dielectric constant of the insulator is uniform, the capacitance between the second layer wiring and the shield layer per unit length is 111 and 113, whereas the capacitance between the second layer wiring and the shield layer is 1
than 12 [(1,810,8) x (1,210,4) ]
x2g13 times as large, so in practice, the wiring capacitance can be estimated by (capacitance between the second layer wiring and the shield layer per unit length) x wiring length, ignoring the capacitance 112 between the second layer wiring. This means that the capacitance 108 between the first layer wiring and the board,
The same applies to the capacitance 109 between layer wirings, the capacitance 110 between the first layer wiring and the shield layer, the capacitance between the third layer wiring and the shield layer, and the capacitance 115 between the third layer wiring.

(Example 2) FIG. 2 is a sectional view showing Example 2 in which the present invention is applied to a semiconductor chip having four-layer wiring.

In the figure, on a substrate 206 on which transistor elements etc. are formed, from the substrate side, first layer wiring 201, grounded shield layer 208, second layer wiring 202, grounded shield layer 208, third layer wiring 203 , grounded shield layer 208, fourth layer distribution kj! , 204 are formed in this order, and each layer is electrically isolated by an insulator 207 and electrically connected by a 1-2 layer through hole 205 or the like as necessary. In addition, in the figure, 209 is the capacitance between the first layer wiring and the board;
210 is the capacitance between the first layer wiring, 211 is the capacitance between the first layer wiring and the shield layer, 215.217 is the capacitance between the third layer wiring and the shield layer, 216 is the capacitance between the third layer wiring, 218
is the capacitance between the fourth layer wiring and the shield layer, and 219 is the capacitance between the fourth layer wiring.

In this embodiment, to calculate the capacitance of the second layer wiring, it is sufficient to consider the capacitances 212 and 214 between the second layer wiring and the shield layer, and the capacitance 213 between the second layer wiring, and the capacitance 213 between the second layer wiring and the board. There is no need to consider the effects of capacitance and potential between the first layer interconnects, between the third layer interconnects, and between the fourth layer interconnects.

This also applies to the calculation of the capacitance of the wiring layer.

(Effects of the Invention) Hereinafter, the present invention eliminates the electrical influence between wiring layers, so The effect that the estimate becomes -ii + ability is
do.

[Brief explanation of drawings]

Fig. 1 is a sectional view showing a solid line example 1 of the present invention, Fig. 2 is a sectional view showing a second embodiment of the invention.
There are cross-sectional views ζ and ′. 101°201, 301...1st N! ! Wiring 102
, 202 , 302 . . . second layer wiring 103 , 20
3, 303...Third layer wiring 204...Fourth layer wiring 104, 205, 304...1-2 layer through holes 105, 206, 305... 1 on the board 106,
2O7, 30f3... Insulator 107, 20B...
Shield M (ground) 108, 209, 307...
Container 109, 210, 3OS between first layer wiring and board
. . . Receptacles 110 and 211 between the first layer wirings . . .
Capacitance between layers between layer wiring and seal 1 111.113 212 214 . . . Capacitance between second layer wiring and shield layer 112,
213, 310... Reservoir 114 between the second M wirings,
215, 217... Capacity 1115 between the 37th t11 wiring and the shield layer
, 216, 313... Receptacle 218 between the ``3M'' wires
... Capacity between the fourth layer wiring and the shield layer 219 ... Capacity between the fourth M wiring 309 ... Capacity between the first layer wiring and the second layer wiring 311
... Receptacle 312 between second layer wiring and substrate ... Second layer wiring - third layer wiring 204314 ... Receptacle 31j1 between third layer wiring and first layer wiring ... Third layer wiring - Applicant for storage permit between boards: II Hondenki Co., Ltd. ,,
-L-,,,,,,,,,,,,,,,,,-,,,
, -/ , 2r - Figure 16

Claims (1)

[Claims] (1) A semiconductor device having m wiring layers (m≧2, m is an integer), the nth layer (1≦n≦) from the semiconductor substrate side.
1. A semiconductor device comprising a conductor layer to which a constant potential is applied between a wiring layer (m-1, n is an integer) and an (n+1)th wiring layer.