JPH046967A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To attain read at fast speed with high S/N, to improve the sensitivity and to reduce smear by setting a signal line subjected to be read to an initial level in advance before the read. CONSTITUTION:A photodetector D, a signal charge amplifier means Ta and a signal charge reset means TR are provided to each picture element 1 and picture elements are arranged in a matrix. A signal line 1. is set to an initial level in advance before a signal is read from the signal line lS. Since no level fluctuation on the signal line lS. due to charge storage thereon and on a video line VL due to invasion of an undesired light is caused, it is not required to make the level constant at the output side. As a result, a margin is caused in the frequency characteristic of the output side with respect to the capacitance of the signal line lS and the readout at a fast speed with high S/N is attained. Since high speed readout is attained, a margin is provided to the allowable range in the wiring resistance of the signal line lS and the sensitivity is improved and smear is reduced by making the size of the signal line lS thin and increasing the aperture rate of the picture element.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a solid-state image sensor in which a plurality of pixels are arranged in a matrix, and in particular to an internal amplification type image sensor in which optical signal charges are amplified within each pixel. Related to solid-state imaging devices.

[Summary of the invention]

The present invention provides a solid-state imaging device in which each pixel has a light receiving element, an amplification means for amplifying a signal charge from the light receiving element, and a reset means for resetting the signal charge, and these pixels are arranged in a matrix. By configuring the signal line for a read operation to be set to an initial level in advance before the read operation, it is possible to read out at high speed and with a high S/N ratio, and also to improve sensitivity and improve sensitivity. It is also possible to reduce smear.

[Conventional technology]

As the resolution of image sensors increases, research is being conducted on internal amplification type solid-state image sensors that have an amplification function for each pixel.
Regarding such technology, for example, "Amplified face-shaped image sensor AM I (Ampli4ied MO3Inte
lligent Imager) J, ``Television Society Journal'' pp. 1075-1082, Vol 41. l'
hll, 1987.

Here, an example of a simple amplification type solid-state imaging element (so-called AMI
), the circuit configuration of the device is an XY address system, and the device has pixels arranged in a 7-trix pattern, as partially omitted in Figure 2, and each pixel is a light-receiving element. (11), vertical switching transistor (
12), an amplification transistor (13), and a reset transistor (14). A first vertical scanning circuit (15) for vertical scanning is installed around the image area consisting of pixels arranged in a matrix.
A second vertical scanning circuit (1G) for resetting, and a horizontal scanning circuit (17) for horizontal scanning are provided. The horizontal scanning circuit (17) includes a horizontal switching transistor (
18), and its horizontal switching transistor (18) is provided to control the connection between the video line S and each vertical signal line (l,). The first vertical scanning circuit (15) and the second vertical scanning circuit (16) respectively control the vertical switching transistor (12) and the reset transistor (14) of each row, and common control is performed for the pixels of each row.

FIG. 3 is a waveform diagram when reading this element. Assuming that the row formed by the first vertical scanning circuit (15) is selected, the signal ΦH from the horizontal scanning circuit (17)
Accordingly, the horizontal switching transistor (18) is turned on and off, and a signal ΦS appears on each video line S in turn.

[Problems to be Solved by the Invention] By the way, by selection from the horizontal scanning circuit (I7), the vertical signal line (l) that supplies information of each pixel to the video line S
, ) are all open, ie, irradiated with incident light, except when selected by the horizontal scanning circuit (17). Therefore, when increasing the sensitivity to support HDVS (high-definition imaging bag W), the vertical signal line (l,)
It is necessary to increase the aperture ratio of the pixel by forming it thinly.

However, in conventional solid-state imaging devices, when the vertical signal line (l,) is thinned, the time constant RC due to the capacitance C of the vertical signal line (!,) and the wiring resistance R increases, and the response speed (readout speed) decreases. HD has the inconvenience of being slow.
There may be cases where it cannot be made compatible with VS. As described above, in the conventional case, there is a limit to increasing the aperture ratio of a pixel by narrowing the vertical signal m (ls), and it is impossible to achieve readout with high speed and high S/N and improve sensitivity. Ta.

Furthermore, as mentioned above, since the vertical signal lines (!,) are open, smear generation also becomes a problem. This kind of inconvenience occurs not only with the above-mentioned IDVS but also with the NTSC camera for photographing the degree of collision.

The present invention has been made in view of these points, and its purpose is to enable high-speed and high S/N readout,
An object of the present invention is to provide a solid-state imaging device that can improve sensitivity and reduce smear.

[Means to solve the problem]

In the present invention, each pixel (1
) and in which these pixels (1) are arranged in a matrix, a signal 41 (I!i) for performing a readout operation is connected in advance to the signal line ( l,) is configured to set it to an initial level.

[For production]

According to the configuration of the present invention described above, since the signal 1 (7!s,) is set to the initial level in advance before reading the signal from the signal line (l,), the initial setting is performed on the output side. There will be no need. In other words, the signal line (r
, ) does not cause fluctuations in the potentials of the signal lines (I!, S 2 ) and the video line VL due to the accumulation of charges on the output side, so there is no need to stabilize the potentials at a constant level on the output side. As a result, there is a margin in the frequency characteristics on the output side with respect to the capacitance of the signal line (l,), and high-speed and high S/N readout becomes possible. In addition, since high-speed readout becomes possible, there is a margin in the tolerance range of wiring resistance in the signal line (!,), and the aperture ratio of the pixel (1) is increased by forming the signal line (1,) thinner. It becomes possible to improve sensitivity. In addition, since the signal line (l,) is set to the initial level, it is possible to sweep out the charge accumulated on the signal line (1,) due to the intrusion of light, etc., and eliminate the smear caused by the accumulated charge on the signal line (1,). The occurrence can be reduced.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to FIG.

FIG. 1 shows that the solid-state image sensor according to this embodiment, in particular, the pixel structure has a MOSFET (MO5 type field effect transistor) that converts the potential based on the optical signal charge generated in the photodiode.
FIG. 2 is a circuit diagram showing an amplification type solid-state image sensor (A) of a type in which current is amplified by applying current to the gate of the image sensor (A). This solid-state image sensor (A) is configured to output signals for two pixels in parallel by one selection from the horizontal scanning circuit, thereby reducing the horizontal scanning frequency.

Each pixel (1) of this solid-state image sensor (A) includes a photodiode (D), an amplification transistor (T, ) each composed of an MO5FET, a vertical switching transistor (T, ), and a reset transistor (T, ), and these pixels (1) are arranged in a matrix to form an image section (2) of the solid-state image sensor (A).

Also, around this image part (2), there are a first vertical scanning circuit (3a) for vertical scanning, a second vertical scanning circuit (3b) for resetting, and a horizontal scanning circuit (3b) for horizontal scanning. 4) is provided.

Therefore, in this example, two video lines VL,
and VL. Then, two vertical signal lines (1
sl) and (f!, SZ) are one set, and each vertical signal line (I!, il) and (psi) of each set connects two horizontal switching transistors (T, ) and (T x □), respectively. The video lines VL and VL are connected to the corresponding video lines VL and VL through the video lines VL and VL. In addition, each gate of the horizontal switching transistor (TXI) and ("rxz) in each group is connected by a first gate line (ffi*+), and each group selection line < ex > are connected to the first gate line (f*+) of each set.By configuring in this way, the 1
The two horizontal switching transistors (Tx+) and (Txz) are controlled simultaneously by one group selection signal ΦH.

Further, the first vertical scanning circuit (3a) and the second vertical scanning circuit (3b) respectively control the vertical switching transistor (T) and the reset transistor (T8) in each row. If, for example, n rows are selected by the row selection signal Φ■ from the first vertical scanning circuit (3a), then the horizontal switching transistor ( TXI) and (TI
I2) are turned on and off at the same time, and accordingly, in the illustrated example, the output currents of the two pixels (1) in, for example, row 0 and group m are made to appear on video lines VL and V L z, respectively. In addition, each video line VL, and VL,
Amplifiers (5a) and (5b) are connected to the rear ends of the amplifiers (5a) and (5b), respectively.

Next, to explain the configuration of each pixel (1), each pixel (1)
One terminal of the photodiode (D) is connected to the gate of the amplification transistor (T,), and a potential based on the optical signal charge generated in the photodiode (D) is applied to the gate of the amplification transistor (T,). It is made to be done. Further, a vertical switching transistor (T, ) is connected in series to the amplifying transistor (T, ), and the gate of the vertical switching transistor (Ty) is connected to a row selection signal from the first vertical scanning circuit (3a). line(
A vertical signal line (ZS+) from a horizontal switching transistor, for example (TX,), is connected to the drain of this vertical switching transistor (T,). In addition, one terminal of the photodiode (D) is connected to the amplification transistor (T, ) as well as a reset transistor (T, ), and the gate of this reset transistor (T+t) is connected to the A reset line (2m) from the second vertical scanning circuit (3b) is connected.

A power supply voltage Vdd common to all pixels is applied to each drain of the amplification transistor (T1) and the reset transistor (TR).

Furthermore, in this example, each amplifier (5a
) and (5b), a bypass line (!,) fixed to the same potential as the input potential is wired in the horizontal direction, and this bypass line (
zm ) and each set of vertical signal lines (i, □) and (fsz
) and two bypass switching transistors (
T□) and (T*z), and
Each bypass switching transistor (TI, ) and (
Each gate of T□) is connected with a second gate line C1, □), and the set selection line (42K) from the horizontal scanning circuit (4) is connected to the second gate line (p, z) of each set. Connect to. In the illustrated example, for example, the m&u-th selection line (1,) is connected to the first gate line B, +) related to mM and the second gate line (I!, , 2) between the m+1 set. Therefore, for example, if m sets are selected, each of the m-th horizontal switching transistors (TXl) and (T!- are turned on, and
Each m+1m bypass switching transistor (T
1) and (To) are turned on, and the potential of each vertical signal line (lsl) and (J!sz) of m+1 & Il is
) and (5b) are fixed at the input potentials (initial levels).

Next, the operation of the solid-state image sensor (A) according to this example will be explained.

First, in an initial state, the photodiode (D) of each pixel (1) is set to an initial value νdd via a reset transistor (Tll). In the subsequent light reception period, the row selection signal Φ from the first vertical scanning circuit (3a)
When, for example, n rows are selected in (2) and further, for example, ml is selected by the group selection signal ΦH from the horizontal scanning circuit (4), the vertical switching transistor (T, ) in each pixel (1) in the n rows is turned on. , m sets of two horizontal switching transistors (Txl) and (TR2) are turned on. By turning on these transistors, each output current from two pixels (1) corresponding to horizontal m&tl among each pixel (1) in n rows is transferred to two vertical signal lines (j!S, ) and ( 4
1! sz) corresponding two video lines VL,
and V L Z respectively. video line VL,
and V L t are outputted in parallel as output signals S and S2, respectively, via corresponding amplifiers (5a) and (5b). Thereafter, these output signals S1 and S2 are serially converted (order corrected) using, for example, a multiplexer (not shown), and then supplied to a subsequent signal processing system. When selecting this m set, m+1&g
One bypass switching transistor each of ) and (
``r m z ) is also turned on, the m+1 sets of vertical signals m(lsl) and (/!sz) are fixed to each input potential of the amplifiers (5a) and (5b), and during the light reception period,
Vertical signal lines (lsl) and (1-5
2) The charges accumulated in 2) are swept out.

Next, when the next set, that is, the m+1 set, is selected in the horizontal scanning circuit (4), two pixels (1) corresponding to the horizontal m+1#Jl out of each pixel (]) in the n rows are selected. The respective output currents are supplied to corresponding video lines VL and VL, respectively, and taken out as output signals Sl and S2 from respective amplifiers (5a) and (5b), respectively. At this time, m+2
Each vertical signal line (lsl) and (is□) of the set is fixed to the input potential of the amplifiers (5a) and (5b). Then, sequentially, all the sets are selected by the horizontal scanning circuit (4) and 1
When output signals S1 and s2 from all pixels (1) in one row (n row) are extracted, the first vertical scanning circuit (3a) selects the next row, that is, the n+1 row, and the second vertical scanning circuit ( In step 3b), cent is performed for each pixel (1) of the row (n row) that has just been successively produced.

That is, the reset signal φR from the reset line (1m) turns on the gate of the reset transistor (TR) in each pixel (1) in that row, thereby resetting the photodiode (D) to the initial value Vdd. Of course, the selection of the row to be read and the selection of the row to be reset are performed by the first vertical scanning circuit (3a) and the second vertical scanning circuit (3b), respectively.
Therefore, the lines outside the hitting plate that have just been successively appeared may be reset, and the line to be reset can be selected independently of the line to be read.

Then, by repeating this series of operations sequentially, the image part (2
) is sequentially supplied to the subsequent signal processing system.

In the above example, the first vertical scanning circuit (3a) selects and reads frames one row at a time, but in other cases, the first vertical scanning circuit (3a) simultaneously selects and reads two rows at a time, for example. n
Rows and (n+1) rows may be selected and read at the same time. In this case, the output current for two pixels in rows n and n+1 is 1
Since the signal flows through two vertical signal lines (fflsl) or (42sz), the sensitivity is twice as high as in the case of frame readout. Further, in this two-row simultaneous readout (field readout), four pixels can be read out at the same time, and the horizontal scanning frequency for continuous field readout can be reduced to two.

Therefore, it is effective for devices with a high horizontal scanning frequency, such as high-definition imaging devices (10 νS).

As mentioned above, according to this example, the vertical signal line (I!, sl)
and (ZSZ), the vertical signal M(
Ns+) and (j2sz) are connected to amplifiers (5a) and (5b
) is fixed at the input potential, that is, set to the initial level, so that the vertical signal line (lS
+) and (j!sz) and video lines VL and VL
The second potential fluctuation no longer occurs. As a result, the amplifier (
It is no longer necessary to stabilize the potential at a constant potential at the input points of 5a) and (5b), and the vertical signal lines (ZS+) and (f!
With respect to the capacity of sz), there is a margin in the frequency characteristics on the output side, and high-speed and high S/N reading is possible. In addition, since high-speed reading is possible, vertical signal H (42s+)
(Lz) There is more room in the tolerance range for the ridiculous wiring resistance, and by forming the vertical signal lines (ps+) and (ZSZ) thinner, it is possible to increase the aperture ratio of the pixel (1) and improve the sensitivity. .

In addition, since the initial levels of the vertical signal lines (es+) and (fsz) are set as described above, charges accumulated in the vertical signal lines (t!s+) and (132) due to light intrusion can be swept out. Vertical signal line (ZS+) and (l s
It is possible to reduce the occurrence of smear due to the accumulated charge of z).

In addition, in this example, two vertical scanning circuits (3a) and (3b) are arranged around the image section (2), and the second vertical scanning circuit (3b) is used to connect a transistor for each pixel (1). Since (T, ) is controlled independently on a row-by-row basis, reading and resetting can be performed independently. Therefore, in addition to frame readout, field readout is possible, and since the horizontal scanning frequency can also be reduced, sensitivity can be improved, and when applied to high-definition imaging devices, the handling of the horizontal scanning frequency can be improved. Regarding this, it becomes possible to provide a margin in the circuit. It also becomes possible to provide the function of an electronic shutter.

(T m , ) and (Tll) are bypass switching transistors.

〔Effect of the invention〕

According to the solid-state imaging device according to the present invention, high S/N ratio can be continuously output at high speed, and sensitivity can be improved and smear can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a solid-state image sensor according to this embodiment, FIG. 2 is a circuit diagram showing a conventional solid-state image sensor, and FIG. 3 is a waveform diagram showing its operation.

Claims (1)

[Claims] A readout operation is performed in a solid-state imaging device in which each pixel has a light-receiving element, an amplification means for amplifying a signal charge from the light-receiving element, and a reset means for resetting the signal charge, and these pixels are arranged in a matrix. A solid-state imaging device in which a signal line is set to an initial level in advance before a read operation thereof.