JPH0468819A - Pll frequency synthesizer - Google Patents

Abstract

PURPOSE:To decrease the lower limit of pull-in time by respectively equivalently arranging one VCO in respective divided output frequency ranges and using these VCOS, while switching them corresponding to an output frequency. CONSTITUTION:A sub phase locked loop is composed of a VCO 11, variable frequency divider 22, phase comparator 23, integral filter 24 and reference component removing filter 25. An MVCO is composed of this sub phase locked loop and a VCO 16. A main phase locked loop is composed of the sub phase locked loop, VCO 16, variable frequency divider 12, phase comparator 13, integral filter 14 and reference component removing filter 15. The sub phase locked loop controls the input voltage of the VCO 11 so that the output of the VCO 16 can be coincident with the output phase of the variable frequency divider 22. the main phase locked loop controls the input voltage of the VCO 16 so that the output of a reference frequency oscillator 17 can be coincident with the output phase of the variable frequency divider 12.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention is directed to shortening the pull-in time in a frequency synthesizer using a phase-locked loop (hereinafter abbreviated as PLL frequency synthesizer. This invention relates to a method that makes it possible to reduce fluctuations in output frequency.

[Prior Art] A conventional PLL frequency synthesizer will be described with reference to the drawings. In FIG. 1, the output of a voltage controlled oscillator 1 becomes the output of the PLL frequency synthesizer and is simultaneously connected to the input of a variable frequency divider 2. . The output of the variable frequency divider 2 is connected to the input 31 of the phase comparator 3. The output of the reference frequency oscillator 6 is connected to the input 32 of the phase comparator 3 to supply the reference frequency. The output of the phase comparator 3 is connected to the input of the integral filter 4, the output of the integral filter 4 is connected to the input of the reference component removal filter 5, and the output of the reference component removal filter 5 is connected to the input of the voltage controlled oscillator 1. Ru.

The integral filter 4 includes an integral capacitor 41 and a gain setting resistor 4.
2, and a stabilizing resistor 43.

The phase comparator 3 is a charge pump type phase comparator, and its output supplies a current proportional to the phase difference between the inputs 32 and 31 to the integrating capacitor 41, and the integrating capacitor 41 integrates this current and holds the charge. (For charge pumps, see, for example, Hideo Tsunoda, PLL Basics and Applications, Chapter 3 (Tokyo Denki University Press)). The gain setting resistor 42 is
This resistor determines the conversion gain from the phase difference between the inputs 32 and 31 to a current value. The stabilizing resistor 43 is a resistor for stabilizing the operation of the loop. Reference component removal filter 5
is a filter for removing fluctuation components included in the output of the integral filter 4. The voltage controlled oscillator 1 is an oscillator that oscillates at a frequency proportional to the input voltage.

In the following description, the circuit consisting of the voltage controlled oscillator, variable frequency divider, phase comparator, and filter configured as shown in FIG. 1 will be referred to as a phase-locked loop.

Furthermore, in Fig. 1, the input of the phase comparator to which the reference frequency oscillator is connected is called the reference input of the phase locked loop, and the voltage controlled oscillator is called the reference input of the phase locked loop.
(abbreviation for lled oscillator).

Therefore, the voltage controlled oscillator 1 will be referred to as VCOL hereinafter.

A state in which the oscillation frequency of vCOl continues to maintain a constant value is called a synchronous state. In the synchronous state, the input voltage of the VCOI is constant, and the phase of the output of the variable frequency divider 2 and the phase of the output of the reference frequency oscillator 6 match. At this time, the oscillation frequency of vCol is determined by dividing the frequency division ratio of the variable frequency divider 2 by N
Then, the output of the reference frequency oscillator 6 is N times. Therefore, if it is possible to change the value of N in steps of 1, it is possible to change the oscillation frequency of the VCOI in steps of the reference frequency.

[Problem to be solved by the invention] In the synchronous state, the phase of the output of the variable frequency divider 2 and the phase of the output of the reference frequency oscillator 6 match, so the output of the phase comparator 3 does not supply current. , integral filter 4
There should be no fluctuating components in the output. but,
A leakage current flows in the circuit connected to the integrating capacitor 41, and the integrating capacitor 41 itself also flows a self-leakage current.
The output of the phase comparator 3 operates to compensate for these leakage currents, and a fluctuation component is generated. This fluctuation component changes the oscillation frequency of vCol. Since the output of the phase comparator 3 intermittently supplies current at a period determined by the reference frequency, the fundamental wave component of the fluctuation component becomes the reference frequency. Integrating capacitor 41
If the value of is increased, the fluctuation component will be reduced. However, since the self-leakage current of a capacitor increases with the capacitance value of the capacitor, if the capacitance 1 of the integrating capacitor 41 is increased and the self-leakage current of the integrating capacitor 41 becomes dominant, even if the capacitance value is increased further, the fluctuation component does not decrease. usually,
The upper limit of the capacitance value is about 10 μF.

The reference component removal filter 5 is for attenuating this fluctuation component, and the lower the cutoff frequency of the reference component removal filter 5, the greater the attenuation.

The cutoff frequency of the reference component removal filter 5 must be set to about 10 times or more the natural frequency of the loop, which will be described later, in consideration of the stability of the loop. Therefore, in order to attenuate the fluctuating component, the cutoff frequency of the reference component removal filter 5 must be lowered, and the natural frequency of the loop must be lowered accordingly.

However, lowering the natural frequency of the loop increases the pull-in time. The pull-in time is the time it takes to enter a synchronized state from an unsynchronized state.

As described above, since the self-leakage current of the integrating capacitor 41 increases with its capacitance value, there is a limit even if an attempt is made to reduce the fluctuation component by increasing the capacitance value. Therefore, there is a problem in that the fluctuation component must be reduced by lowering the natural frequency of the loop, that is, increasing the pull-in time, and lowering the cutoff frequency of the reference component removal filter. Since the fluctuation component increases as the reference frequency is lowered, this problem becomes more severe as the reference frequency is lowered.

Next, as a preparation for showing the effects of the present invention, the above relationship will be explained using mathematical expressions. The conversion gain of VCOI is Kv[ra
d/(5-V) co, the phase comparison gain of phase comparator 3 is
Kp[V/rad], the Laplace transform of the transfer function of the integral filter 4 is set to 2, the phase of the output of the reference frequency oscillator 6 is input, and the phase of the output of the variable frequency divider 2 is the output. Letting G be the following relationship. However, since the cutoff frequency of the transfer function of the reference component removal filter 5 is set sufficiently high compared to the natural frequency of the loop, its contribution is ignored.

G=KKF/(S+KKF) 1st formula However, K
=KvKP/NS The complex variable of S=Niraplus conversion is expressed as follows.

K, = (τ, s+ 1)/τ, S Second formula, where τ, = CR, τ2 = CR2, C is the integrating capacitor 4
1, the capacitance value [F], R, is the resistance value of the gain setting resistor 42 [
Ω], and R2 is the resistance value [Ω] of the stabilizing resistor 43. When using a charge pump type phase comparator,
The phase comparator and gain setting resistor 42 are integrated and operate as a constant current circuit. The value of the constant current is approximately given by φK p/R1. φ[rad] is the phase difference between the input 32 and the input 31 of the phase comparator 3. When this constant current flows through the series circuit of the stabilizing resistor 43 and the integrating capacitor 41, the output voltage of the integrating filter 4 is generated.

The second equation is obtained from this relationship.

From the first and second equations, the transfer function G is as follows.

G=(sKτ2/τ1+/τ1)/(S”+SKτ,
/τ1+ to /τ,) In the third equation 22, ω, = (K/τ,)1/2 Fourth
Formula ζ=τ, (K/τ,)1/2/2 ω9 shown in the fifth formula is called the natural angular frequency [rad/S], and ζ
is called the damping factor. ζ is set to ζ#1 from the viewpoint of loop stability and responsiveness.

The pull-in time is determined from the step response of the transfer function G, and the waveform of the step response is determined by ω and this value. Here, assuming that ζ'=1, 'racs' given by the following equation is defined as the pull-in time. (For example, Hideo Tsunoda, PLL
Basics and Applications (see Chapter 1 (Tokyo Denki University Press)).

Ts=1/ω9=(τ,/K)I/2 Equation 6 Next, the fluctuating voltage, which is the fluctuating component due to the leakage current, is determined. The fluctuating voltage is generated by compensating for the outflow of charge due to steady leakage current at a period determined by the reference frequency. Therefore, the fluctuating voltage is ETl[V], and the leakage current is 1. L
[A, and the reference angular frequency is ω*[rad/S]
Then, E is shown below.

However, E represents the range of fluctuation.

E, = 2πIL/ωRC Equation 7 It is assumed that the reference component removal filter 5 is composed of a first-order low-pass filter, and its cutoff angular frequency is ωc[rad/
S ], the reference component removal filter 5 gives attenuation shown by the following ω to the acid component of R5. however,
ω. =10ω9.

L″”t(t)c/ωm= 10 (IJN/ω6
Equation 8 Therefore, if the variation in the oscillation frequency of VCol due to ER is F o [rad/S ], Fo becomes as follows.

However, F represents the width of fluctuation.

F, = KvL E, = 20πKvr LωN/ωll
'C Equation 9 When T is determined from Equation 6 and Equation 9, T becomes as follows.

T, = 20πKvIL/FDω-C Equation 10 In a state where the self-leakage current of the integrating capacitor 41 is dominant, when the value of C is increased, ■ increases in proportion to the value of C, and lL/C remains a constant value. Therefore, Equation 10 is an equation that gives the lower limit of Ts when Fo and ω6 are given. The product of the input voltage range of Kv and vCO determines the output frequency range of the PLL frequency synthesizer, so by lowering the value of Kv, Ts
It is impossible to lower this using conventional methods.

The present invention makes it possible to lower the value of Kv without reducing the output frequency range by introducing a means to compensate for the decrease in the output frequency range due to lowering the value of Kv, thereby lowering the lower limit of the pull-in time. is intended to provide. In the case of fixing ω6 and Ts in the 10th equation, it also provides a method of lowering the lower limit of Fo.

[Means for Solving the Problems] In order to achieve the above object, the PLL frequency synthesizer of the present invention divides the output-wavenumber range, and equivalently provides one vCO for each divided output frequency range.
The Kv value of each VCO is lowered, and these VCOs are switched and used according to the output frequency of the PLL frequency synthesizer.

Specifically, the PLL frequency synthesizer of the present invention is composed of a double phase-locked loop consisting of a main phase-locked loop and a sub-phase-locked loop, and a first vCO and a second vCO
has. The secondary phase-locked loop is included within the main phase-locked loop and operates as part of the main phase-locked loop's vCO. In the following explanation, vC of the main phase-locked loop
O is called MvCO. The MVCO consists of a first vCO and a secondary phase-locked loop. The second vCO is the vc'o of the secondary phase-locked loop. The input of the first VCO is M
The input of the VCO, and the output of the second VCo is the output of the MVCO. The sub-phase locked loop uses the output of the first vCo as a reference input. A reference frequency oscillator is connected to the reference input of the main phase-locked loop to supply a reference frequency.

The MVCO configured in this way outputs different frequencies depending on the value of the division ratio of the variable divider in the sub-phase locked loop, so by changing this division ratio, the MVCO
is equivalent to a vCo that operates by switching a large number of vCOs.

[Operations] The operations of the PLL frequency synthesizer configured as described above will be described below. In the synchronous state, with respect to the main phase-locked loop, if the angular frequency of the MVCO output is ω, [rad/S], the following relationship holds true.

ω = ωRN1 Equation 11 where ω is the angular frequency of the output of the reference frequency oscillator, and N1 is the division ratio of the variable frequency divider of the main phase-locked loop.

Equation 11 shows that the field frequency ω of the output of the PLL frequency synthesizer is determined by N1. Further, in the synchronous state, regarding the sub-phase locked loop, if the angular frequency of the output of the first VCO is ω1, the following relationship holds true.

ωu=ω1N! Equation 12 Here, ω1 is the angular frequency [rad
/S ], and N2 is the frequency division ratio of the variable frequency divider of the sub-phase locked loop.

From the 11th and 12th equations, the following relationship holds true.

ω1=ω*N1/N* Equation 13 Here, let ω, >ω8, and Nl>Nl. Equation 13 shows that the angular frequency ω1 of the output of the first VCO is determined by N, /N2, and the value of N is determined according to the value of N1 so that the value of N, /N* is as constant as possible. This shows that if determined, it is possible to reduce the change in ω due to a change in the value of N1. Therefore, we introduce a constant R: Nl/R)-1/2≦N,
<(N,/R)+1/2 Determine the integer N from N so as to satisfy Equation 14.

Assuming N1>>R, transforming Equation 14 yields RR”/
2Nt<Nt/N*≦R+R”72N□ Equation 15 is obtained. Since N is an integer obtained from Equation 14, N,
When , the value of N, /N changes within the range shown by Equation 15. Therefore, ω due to changing N1
, let Δω be the amount of change in
From Equation 5, it is shown as follows.

Δω1=ω, R''/N, Equation 16 This change in ω changes ω due to the operation of the sub-phase locked loop.

Letting Δω be the amount of change in ω due to Δω1, Δω is expressed as follows from Equation 12.

Δω, = Δω1N2#ωaR”N!/N, 17th
Since Equation N1>>R, from Equation 15 N, /N, #R Equation 18, and by substituting Equation 18 into Equation 17, the following equation is obtained, ΔωM#ωIIR Equation 19 By substituting the 18th equation into the 13th equation, the following equation is obtained.

ω1#ωRR Equation 20 Also, let the input voltage range of the first vCO be Ec [V],
The conversion gain of MVCO is KM [rad/(5-V)]
Then, K1 can be determined from Equation 19 as follows.

KM=ΔωJEc=ωRR/ECEquation 21By the way, the conversion gain of the VCO in the conventional system is expressed as KA[
rad/(S − V)], it becomes as follows.

KT=ωaΔN1/Ec Formula 22 However, ΔN
, represents the varying width of N. Therefore, KJK, = R/
A N is Equation 23, and if R is chosen so that R is ΔN1, KM can be lowered below 1, and the lower limit given by Equation 10 can be lowered.

[Embodiment] An embodiment in which the output frequency range is 10 MHz to 20 MHz and the step frequency is IKHz will be explained with reference to the drawings. In FIG. is connected to the input of the device 22. However, the step frequency refers to the frequency interval between adjacent frequencies with respect to the frequencies generated by the PLL frequency synthesizer. The output of the variable frequency divider 12 is connected to the input 131 of the phase comparator 13, and the output of the phase comparator 13 is connected to the input of the integral filter 14.
The output of is connected to the input of the reference component removal filter 15. The reference frequency oscillator 1 is connected to the input 132 of the phase comparator 13.
7 outputs are connected. Input 132 is a reference input.

The output of the reference component removal filter 15 is connected to the VCO 16 .

The integral filter 14 is composed of an integral capacitor 141, a gain setting resistor 142, and a stabilizing resistor 143.

The output of VCO 16 is connected to input 232 of phase comparator 23. Input 232 is a reference input. Variable frequency divider 22
The output of is connected to the input 231 of the phase comparator 23. The output of the phase comparator 23 is connected to the input of the integral filter 24, and the output of the integral filter 24 is connected to the reference component removal filter 2.
The output of the reference component removal filter 25 is connected to the input of the VCOll.

VCOll, variable frequency divider 22, phase comparator 23, integral filter 24, and -reference component removal filter 25 constitute a sub-phase locked loop. Secondary phase-locked loop and V
CO16 constitutes the MVCO.

The sub phase-locked loop, VCO 16, variable frequency divider 12, phase comparator 13, integral filter 14, and reference component removal filter 15 constitute a main phase-locked loop. The sub-phase locked loop controls the input voltage of the VColl so that the output of the VCO 16 and the output of the variable frequency divider 22 match in phase. The main phase-locked loop is connected to the VCO 1 so that the output of the reference frequency oscillator 17 and the output of the variable frequency divider 12 match in phase.
Controls the input voltage of 6.

Note that in this embodiment, R=100. The frequency division ratio of the variable frequency divider 12 corresponds to N1 in Equation 11, and is N,=10.
OoO ~ 20,000. The frequency division ratio of the variable frequency divider 22 corresponds to N in Equation 12.

The value of N2 is from formula 14: N2# 100~200
It is set within the range of . The frequency of the output of the reference frequency oscillator 17 is IKHz, and ω1 is 2π×1os.

vCOll is set to oscillate in the frequency range from 10 MHz to 20 MHz, and VCO 16 is set to oscillate at ω1 given by Equation 20, that is, approximately 100 KHz.
It is set to oscillate in a frequency range of Δω3 given by Equation 16, that is, approximately IKHz, with Δω3 as the center frequency. Therefore, the conversion gain of vColl is Kv□
[rad/(S-V)] Then, KV2 is set as Kv□=2πX107/EC=2π×106 Equation 24. However, EC is the input voltage range of VCOII and VCO16, and EC=10V.

The conversion gain KM[rad/(5-V)co] of the MVCO is determined from Equation 21 as follows.

K, = 2πx10"x100/Ec = 2πx104
The 25th formula ■C011 uses a resonant circuit with a coil and a capacitor, and the VCO 16 is made using a ceramic resonator. The phase comparison gains of phase comparators 13 and 23 are each 1.

The natural frequency of the main phase-locked loop is 15 Hz, the cut-off frequency of the reference component removal filter 15 is 150 Hz, the natural frequency of the sub-phase locked loop is 300 Hz, and the cut-off frequency of the reference component removal filter 25 is 3 KHz. The natural frequency of the secondary phase-locked loop is 20 times the natural frequency of the primary phase-locked loop, and the influence of the secondary phase-locked loop on loop stability and pull-in time is ignored.

[Effects of the Invention] The present invention will be described in detail by specifically determining the pull-in time in this embodiment and the pull-in time in the conventional method and comparing the two.

The lower limit of the pull-in time is given by Equation 10.

In Equation 10, F=1, and L/C as a critical value, IL/C=10-1, then the lower limit of the pull-in time in this embodiment is as follows.

Ts=20πKMIL/FDω-C=10-' Equation 26 On the other hand, from the design values in this example, using Equations 7, 8, and 9 to find the variation in the oscillation frequency of VCOII, the following is obtained. It becomes like this.

Fo=ni, LE.

;2πX1G'X(150/10sXl0-"/10"
-1 Equation 27 Therefore, this embodiment satisfies the condition F,=1 for realizing the lower limit given by Equation 26. In other words, the natural frequency 1 of the main phase-locked loop is expressed in Equation 6.
T obtained by substituting 5Hz = 17 (2π x 15) -
This means that the pull-in time of 1O-2 Equation 28 is realized under the condition of F=1. By the way, FD=1
This fluctuation in the oscillation frequency generates spurious components at frequencies of IKHz above and below the oscillation frequency of VCOI 1, each having a voltage ratio of approximately 10 −4 times the output of VCO II.

Note that in Equation 27, the integral filter 2 of the sub-phase locked loop is
Although the influence of the fluctuating voltage due to the leakage current in 4 is ignored, if the influence is found in the same way as Equation 27, then FD=KV! LER = 2 x x 10' x (3 x 10"/10')
X 10-1710'ζ0.2
It can be seen that it becomes Equation 29 and can be ignored. , Next, find the pull-in time when configured using the conventional method. The conversion gain of vCO in the conventional method is 24th
Kv given by the formula! becomes the same as '. Therefore, from Equation 10, the lower limit of the pull-in time is F o = 1 and I
Assuming that L/C=10-', it becomes as follows.

Ts=20ff Kv* I t/FDct>t”c=
1 Equation 30 As can be seen by comparing Equations 28 and 30, the pull-in time of 1 second in the conventional method has been shortened to 10 milliseconds in the present invention, an improvement of 100 times. I understand.

Note that the reference component removal filter 15 and the reference component removal filter 25 have been explained using first-order low-pass filters, but this is just to show the principle and what will happen if the stability of the loop is ensured. It may be a filter. However, in this case, the present invention can be applied although the form of equation 8 changes. For example, it is possible to employ a second-order low-pass filter or add a band-rejection filter as long as the stability of the loop is not impaired. Further, the reference component removal filter 15 and the reference component removal filter 25 are omitted if the fluctuation components in their respective inputs are sufficiently small.

The configurations of the integral filter 14 and the integral filter 24 illustrate the principle, and a circuit for correcting the phase or adjusting the gain may be added in order to improve the stability of the loop, but the present invention It is possible to apply For example, in order to improve the high-frequency characteristics of the loop, a capacitor may be connected in parallel to the stabilizing resistor 143, or an amplifier having a series circuit of the stabilizing resistor and the integrating capacitor may be connected to the stabilizing resistor 143 and the integrating capacitor 14 in the feedback circuit.
Even if the functions of 1 are replaced, the effect of applying the present invention does not change. Furthermore, the circuit systems of the phase comparator 23 and the integral filter 24 do not matter, since they are not directly involved in realizing the effects of the present invention.

The 14th formula is the frequency division ratio N1 of the variable frequency divider of the main phase-locked loop.
This is the formula for determining the layer division ratio N of the variable frequency divider of the sub-phase locked loop from The conversion formula is not limited to the 14th formula. For example, a conversion formula may be considered in which N1 is expressed in binary and the upper n bits are expressed as N2.

n is a fixed value.

If the oscillation frequency of the VCO 16 is low, a crystal or ceramic oscillator cannot be used as the oscillator of the VC016.

In such a case, oscillate with a crystal or ceramic oscillator, divide its output with a frequency divider, and convert the divided output to V.
It is possible to output the C016.

It is also possible to increase the amount of improvement by further multiplexing the sub-phase locked loops. For example, a sub-phase-locked loop is further configured within the sub-phase-locked loop to triplex the loop. It is also possible to further increase the amount of improvement if the frequency division ratio of the variable frequency divider of the added sub-phase locked loop is set to N8 and N3 is determined so that N2/N8 approaches a constant value.

This is an effective means when the step frequency is low.

In the above explanation, the effect of improving the pull-in time T8 when the fluctuation value FD of the output frequency of the PLL frequency synthesizer and the reference can frequency ω8 are fixed has been clarified. However, as is clear from Equation 10, the amount of improvement is determined by the pull-in time T8, the fluctuation value FD, and the reference can frequency ω.
It is possible to allocate each to 7. That is, the variation value F0 can be improved by fixing the pull-in time T and the reference can frequency ω, or the variation value F0 can be improved by fixing the reference can frequency ωa, although the amount of improvement in each decreases.
It is possible to improve both at the same time. Furthermore, it is also possible to lower ω6, that is, the step frequency, by fixing the pull-in time T8 and the fluctuation value Fo.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional PLL frequency synthesizer, and FIG. 2 is a diagram of a PLL frequency synthesizer representing an embodiment of the present invention. 1.11.16...VCO (voltage controlled oscillator)
, 2.12.22... variable frequency divider, 3.13.
23... Phase comparator, 4.14.24...
...Integral filter, 5.15.25...Reference component removal filter, 6.17...Reference frequency oscillator, 31.32.131.132.231.232 Phase comparator input , 41.141... Integrating capacitor, 42.14
2...Gain setting resistor, 43.143...
・Stabilizing resistor, / 6 reference frequency oscillation magazine

Claims (1)

[Claims] 1. It consists of a main phase-locked loop and a sub-phase-locked loop included in the main phase-locked loop, and has first and second voltage-controlled oscillators, and the first voltage-controlled oscillator and the sub-phase-locked loop are part of the main phase-locked loop. a voltage controlled oscillator, the second voltage controlled oscillator serves as a voltage controlled oscillator of a sub-phase locked loop;
The main phase-locked loop uses the reference frequency as a reference input, and the sub-phase-locked loop uses the output of the first voltage-controlled oscillator as a reference input, and the division ratio of the variable frequency divider of the main phase-locked loop and the variable frequency of the sub-phase-locked loop A PLL frequency synthesizer in which a frequency division ratio of a variable frequency divider of a sub-phase locked loop is determined so that a value of a frequency division ratio of the frequency divider is approximately constant.