JPH0468390A - Display device - Google Patents

Abstract

PURPOSE:To enable sufficiently fast writing operation without any hindrance to reading operation by dividing one stage into five timing parts, and utilizing four timing parts for reading and the remaining one timing part for writing. CONSTITUTION:This device is provided with a display unit 8 which displays an image with a dot matrix and an image memory 4 which correspond to display dots. The timing of access to the image memory 4 consists of five clocks T1 - T5; and four out of the five clocks are used to read the image memory 4 and one clock is not used. When there is a request to write data in the image memory 4, one of the five clocks are used as write clocks and four clocks are used as read clocks. Consequently, the reading operation and writing operation are performed simultaneously and a sufficient speed is obtained as the writing speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a display device, and more particularly to a display device having a display device that displays an image in a dot matrix and a memory corresponding to the display dots.

2. Description of the Related Art A display device having a conventional memory includes a write control circuit 31 and a read timing circuit 32, as shown in FIG.
, a selection circuit 33, an image memory 34, a dot conversion circuit 35, a column electrode drive circuit 36, a row electrode drive circuit 37, and a dot matrix display 38. The readout timing circuit 32 generates readout position information of the image memory 34 and necessary timing for the dot conversion circuit 35, column electrode drive circuit 36, or row electrode drive circuit 37. Selector circuit 3 for read position information of image memory 34
3 to the image memory 34;
The display information is read out and the dot conversion circuit 35 converts the
The information is converted into information and transferred to the column electrode drive circuit 36, and the selected intersection dot of the display 38 is lit by the row electrode drive circuit 37. By sequentially scanning the row electrodes, the display 38
The display information of the image memory 34 is displayed.

When rewriting the information in the image memory 34, the write control circuit 31 supplies the position information of the image memory 34 to be rewritten to the image memory 34 by switching the selector circuit 33, and transfers the rewritten data to the image memory 34. .

Problems to be Solved by the Invention However, since this conventional display device cannot perform read and write operations simultaneously, either a read-priority method or a write-priority method is adopted.

In the case of read priority, writing is performed using the read pause timing, so the writing speed is slow, and there is a problem that it takes time to rewrite the entire screen in a display device with a large display capacity.

Furthermore, if writing is prioritized, the writing speed becomes faster, but there are problems such as the display being blurred or the brightness of the display changing.

The present invention has been made in view of the above-mentioned conventional situation,
Therefore, an object of the present invention is to provide a novel display device that can solve the above-mentioned problems inherent in the conventional technology.

Means for Solving the Problems In order to achieve the above object, the display device according to the present invention sets the access timing of the image memory to 5 clocks as 1 timing, and during the read operation, uses 4 clocks out of 5 clocks and 1 The clock is used as a standby clock, and during a write operation, 4 out of 5 clocks are used for reading and 1 clock is used for writing.

EXAMPLES Below, preferred embodiments of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment according to the present invention.

Referring to FIG. 1, reference number 1 indicates a write control circuit;
11 is a write flip-flop (hereinafter abbreviated as FF), 12 is an address select circuit, 13 is a write clock circuit, 14 is a data register, 15 is an address register, 2 is a read timing circuit, 21 is a clock generation circuit, 22 is a timing generation circuit, 23 is T1 to T
4 timing circuit, 24 T55 timing path, 25 read address counter, 3 select circuit, 4 image memory, 5 dot conversion circuit, 6 column voltage IFf! A drive circuit, 7 is a row electrode drive circuit, and 8 is a dot matrix display.

Next, this first embodiment will be explained with reference to the timing section of FIG.

In FIG. 2, stages S1 and S2 are the timings when image data is read out, and stages S3 and S4 are the timings when a write request is made. When there is no write request, the clock generated by the clock generation circuit 21 in FIG.
sent to. The T5 timing circuit 24 is in a rest state. During this time, address data for determining the position of the image memory 4 is supplied from the read address counter 25 to the image memory 4 through the select circuit 3. The image data from the image memory 4 is outputted bit by bit by the dot conversion circuit 5. At timing T5 of the pause period, the previous data remains the same. Stages S1 and S2 in FIG. 2 show this situation.

On the other hand, if there is a write request 10, the write F
-Fil is set, and at the next timing, that is, stage S3 in FIG. 2, there is a write request at timing T2, so the read clock at timing T3 is paused, and at this time, the address select circuit 12 in FIG. The select circuit 3 is switched to output the address information in the address register 15 to the image memory 4 through the select circuit 3. At the same time, the write clock circuit 13 supplies a write clock to the image memory 4 and acts on the T1-T4 timing circuit 23 to suspend the read clock at the T3 timing. The data register 14 outputs information to be written to the image memory 4 in accordance with the output of the write clock circuit 13. When writing is completed, the reading operation returns at the next timing T4. In the read operation at this time, it is checked whether the write F-Fil is set at timing T5, and if it is set, T1 to T
Since there was a write request in period 4, T5
The timing circuit 24 is activated to output a read clock at timing T5. Stage S3 in FIG. 2 shows this situation. Stage S4 is a case where a write request occurs at timing T3, and the operation is the same as stage S3.

The data obtained at such timing is converted into a desired voltage by the column electrode drive circuit 6 and the row electrode drive circuit 7, and is displayed on the dot matrix display 8.

FIG. 3 is a block diagram showing a second embodiment of the invention. FIG. 4 is a timing diagram of FIG. 3.

Referring to FIGS. 3 and 4, stages S1 and S2 are equivalent to stages S1 and S2 of FIG. 2, as can be seen from the timing diagram of FIG. In stages S3 and S4, write requests are generated at the same timings T2 and T3 as in FIG. 2, but the write operation is always performed at timing T5. By doing this, there is no need to change the read clock, so you can check the write F-FIL only at timing T5, and if it is set, perform the write operation, so the timing shown in Figure 2 is used. The circuit configuration is simpler than that of the first embodiment. However, the write request is from timing T1 to T4.
Since the time to complete the write differs depending on where the write occurs, the data register 14
, it is necessary to hold data and addresses in the address registers 15, respectively.

As described in detail, according to the present invention, one stage is T1
~ T5 is divided into 5 timings, and 4 timings are used for reading and the remaining 1 timing is used for pausing or writing, so it is possible to perform sufficiently fast write operations without hindering read operations, and there is no flickering during writing. It is possible to provide a display device that does not cause such problems. In the case of the present invention, image data is read out one bit at a time (corresponding to one dot on the dot matrix display 8), resulting in 8 bits, that is, 1 byte of data, in two stages. On the other hand, since one byte can be written at a time, one byte can be rewritten in one stage. In other words, it is possible to rewrite two screens while displaying one screen, and the writing speed is sufficient.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a timing chart of the embodiment of FIG. 1, FIG. 3 is a block diagram showing a second embodiment of the present invention, and FIG. This figure is a timing chart of the embodiment shown in FIG. 2, and FIG. 5 is a block diagram of a configuration example according to the prior art. 1.31... Write control circuit, 10... Write request signal, 11... Write FF, 12... Address select circuit, 13... Write clock circuit,
14...Data register, 15...Address register, 2.32...Read timing circuit, 21...
・Clock generation circuit, 22...timing generation circuit,
23...T1-T4 timing circuit, 24...T5
Timing circuit, 25... Read address counter, 3.33 Select circuit, 4.34... Image, memory, 5.35... Dot conversion circuit, 6.36... Column electrode drive circuit, 7. 37. Row electrode drive circuit, 8.38.
・Dot matrix display

Claims (1)

[Claims] In a display device that displays an image in a dot matrix and an image memory corresponding to the display dots, the access timing of the image memory is set to 5 clocks as one timing, and when only reading the image memory is performed, the access timing of the image memory is set to 5 clocks.
1 using 4 clocks as read clock
A display device characterized in that the display device waits for a clock period, and when there is a write request to the image memory, one clock out of five clocks is used as a write clock and four clocks are used as a read clock.