JPH0467682A - Mis type semiconductor device - Google Patents

Abstract

PURPOSE:To restrain a MIS type semiconductor device from deteriorating in breakdown strength due to impact ionization so as to improve it in reliability by a method wherein a second conductivity type semiconductor region isolated from a channel region is provided coming into contact with a first conductivity type source region. CONSTITUTION:A second conductivity type semiconductor region 28 isolated from a channel region 27 is provided coming into contact with a first conductivity type source region 25. A distance WN between the second conductivity type semiconductor region 28 and the channel region 27 or the width of the source region 25 is set smaller than the diffusion length of minority carriers in the source region 25, whereby minority carriers are lessened in effective length of diffusion in the source region 25. At the same time, the second conductivity type channel region 27, the first conductivity type source region 25, and the second conductivity type semiconductor region 28 constitute a bipolar transistor structure. Therefore, a current induced by impact ionization inside the channel region 27 is made to flow out through the source region 25 and the metal layer 28.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to a so-called SOI (silicon on 1n) in which a semiconductor thin layer is formed on a substrate with an insulating layer interposed therebetween.
M is applied to the semiconductor thin layer using a
The present invention relates to a MIS type semiconductor device formed by forming a semiconductor element with an IS structure.

[Summary of the invention]

The present invention provides an MIS type semiconductor device in which a semiconductor layer is formed on an insulating substrate, and a gate electrode is formed on this semiconductor layer via a gate insulating film, in which a channel region is in contact with a source region of a first conductivity type. By providing a semiconductor region of the second conductivity type separated from the semiconductor region, it is possible to suppress a drop in breakdown voltage due to impact ionization, which is a drawback of MIS semiconductor devices formed on a Sol substrate, and to improve the performance of this type of MIS semiconductor device. This is intended to increase the multiplication rate.

Further, the present invention provides a semiconductor layer formed on an insulating substrate,
In an MIS type semiconductor device in which a gate electrode is formed on this semiconductor layer via a gate insulating film, a high concentration region and a low concentration region are provided below the high concentration region as a source region of the first conductivity type, and the low concentration region of this source region is By providing a second conductivity type semiconductor region in contact with the channel region and separated from the channel region, the breakdown voltage drop due to impact ionization, which is a drawback of MIS type semiconductor devices formed on SOI substrates, can be further suppressed. This is intended to increase the multiplicity of the MIS type semiconductor device.

The present invention also provides an MIS type semiconductor device in which a semiconductor layer is formed on an insulating substrate, and a gate electrode is formed on this semiconductor layer via a gate insulating film, in which a semiconductor layer is formed in contact with a drain region of a first conductivity type. By providing a semiconductor region of the second conductivity type separated from the channel region, a decrease in breakdown voltage due to impact ionization, which is a drawback of MIS type semiconductor devices formed on SOT substrates, can be suppressed, and this type of MIS type This is intended to increase the multiplication efficiency of the semiconductor device.

[Conventional technology]

Recently, many advantages have been reported regarding so-called thin film Sol devices using SOI substrates. For example, it has a high degree of freedom in setting the impurity concentration in the channel region, has high alpha ray resistance, is latch-up free, and can achieve high speed by reducing the parasitic capacitance between the substrate and the silicon thin film that is the element formation region. It has advantages such as:

For this reason, research on thin film Sol elements is currently being actively conducted, and their development is progressing.

For example, a MIS field effect transistor (hereinafter abbreviated as MISFET) using an SOI substrate is manufactured by bonding a silicon substrate (
1) Using a Sol substrate (4) on which an island-shaped silicon thin film (so-called Sol film) (3) is formed via a SiO□ film (2), a source of the first conductivity type is applied to the silicon thin film (3). A region (5) and a drain region (6) are formed, and a gate insulating film (eg, a polycrystalline film such as SiO It is constructed by forming a gate electrode (8) made of silicon. (9) is a source electrode, and (10) is a drain electrode.

[Problem to be solved by the invention]

However, the old 5FET using SOIi board (4)
In (11), there is a drawback that the source-drain breakdown voltage, that is, the source-drain breakdown voltage is low.

This is the MISFET (11) as shown in Figure 24.
, from the source region (5) to the channel region (12)
The minority carriers (electrons) e injected into the drain region (
6), and these electrons e are impacted by the high electric field region (13) generated at the drain end under the gate electrode (8).
Ionization occurs and electron-hole pairs are generated, of which the holes flow into the channel region (12). That is, normal bulk type MI
In SFET, holes h (so-called hole current IP) flowing into the channel region escape as substrate current through the substrate, but in this SOI substrate, the silicon thin film (3) is
Since it is surrounded by the O□ film (2) and is not structured to allow holes to escape, the holes accumulate in the channel region (12) near the source region (5).

These accumulated holes lower the energy barrier between the source and the channel, and as a result, the source acts as an electron emitter, in addition to the normal flow of electrons (channel current c) flowing into the channel region (12). The above-mentioned bipolar-operated electron current (2) is generated. This electron current air again causes a positive feedback phenomenon in which a hole current 1p is generated in the high electric field region (13), causing a rapid increase in the drain current ll1l, resulting in a decrease in the source-train breakdown voltage. .

Various methods have been proposed in the past to suppress the reduction in source-drain breakdown voltage caused by such impact ionization.

For example, the MrSFET (14) shown in FIG. 25 is constructed by increasing the film thickness of the silicon thin film (3) in the portion corresponding to the drain region (6) to weaken the electric field at the drain end. This is intended to reduce current generation and improve source-drain breakdown voltage. However, this method has disadvantages in that the structure is complicated and difficult to manufacture, and the effect is insufficient. Also, gate l5FET (15
), the source region (5) and the drain region (6) are formed to be shallower than the silicon thin film (3), and the source region (5) is made shallower than the silicon thin film (3).
) outside the source region (5) and a channel region (1
By forming a semiconductor region (16) of the same conductivity type as 2) and deriving an electrode (17) from it, the hole current IP generated by impact ionization can be released through the semiconductor region (16). , the source-drain breakdown voltage is improved. This method uses a silicon thin film (
3) becomes larger and the parasitic capacitance between it and the region (12) becomes larger, making it difficult for MISFE using a Sol substrate to
Since the advantage of T is lost and the thickness of the silicon thin film (3) becomes substantially large, short channel effects are more likely to occur, and to prevent this, the channel concentration is inevitably increased, resulting in carrier There is a disadvantage that the advantage of the MISFET using the Sol substrate, which is that the mobility can be increased, is lost.

On the other hand, a structure shown in FIG. 27 has been considered as one that is rational in terms of manufacturing method and structure. The MISFET (18) shown in FIG. 27 has a semiconductor region (16) of the same conductivity type as the channel region (12) formed in contact with the outside of a shallow source region (5), and a source electrode (9). By sharing the two terminals, it can be used as a normal three-terminal element. In the case of this MISFET (18) as well, since the hole current IP generated by impact ionization can be released through the semiconductor region (16) and the source electrode (9), the drain breakdown voltage can be improved. However, in the MISFET (18), a semiconductor region (19) of the same conductivity type as the semiconductor region (16) is formed outside the drain region (6) in consideration of the symmetry of the device structure, as shown in FIG. If the semiconductor region (
19) into the channel region (12) flows into the semiconductor region (16) on the source region (5) side (second
(In FIG. 8, the Hall current is expressed as 1 pp). For example, during non-operation, short-circuiting and conduction occur between the source and the drain, which is a problem.

Therefore, this structure cannot be applied to a switching element such as an access transistor of a static RAM cell in which the source and drain are alternately used, and there is a drawback that the range of application as a circuit element is limited.

In view of the above-mentioned points, the present invention is an MIS type semiconductor that can suppress the drop in breakdown voltage caused by impact ionization, increase the multiplier performance of the semiconductor device itself, and expand the range of application as a circuit element. It provides equipment.

[Means to solve the problem]

The present invention is shown in FIG. 1 (and also in FIGS. 2 and 3).

Figure 4, Figure 5, Figure 6, Figure 8, Figure 9, Figure 10,
As shown in FIG. 11), a semiconductor layer (23) is formed on an insulating substrate (22), and a gate electrode (30) is formed on this semiconductor layer (23) via a gate insulating film (29). The MIS type semiconductor device is configured to have a second conductivity type semiconductor region (28) in contact with a first conductivity type source region (25) and separated from a channel region (27).

Further, as shown in FIG. 16 (and other FIG. 17), the present invention also provides a semiconductor layer (23) formed on an insulating substrate (22), and a gate insulating film (29) on this semiconductor layer (23). )
In an MIS type semiconductor device in which a gate electrode (30) is formed through a gate electrode (30), a source region (25) of the first conductivity type has a high concentration region (25a) and a low concentration region (25c) below the high concentration region (25a).
), and includes a semiconductor region (28) of a second conductivity type that is in contact with a low concentration region (25c) of a source region (25) of a first conductivity type and is separated from a channel region (27). .

Further, as shown in FIG. 13, the present invention provides an insulating substrate (
22) In an MIS type semiconductor device in which a semiconductor layer (23) is formed on the semiconductor layer (23) and a gate electrode (30) is formed on the semiconductor layer (23) via a gate insulating film (29), a second conductivity type semiconductor region (47) in contact with the drain region (26) and separated from the channel region (27);
It consists of:

[Effect]

In the first invention, for example, as shown in FIG. 1, the channel region (25) is in contact with the source region (25) of the first conductivity type.
By providing the second conductivity type semiconductor region (28) separated from the second conductivity type semiconductor region (27), the distance of the source region (25) between the second conductivity type semiconductor region (28) and the channel region (27) is
By taking width) WN smaller than the diffusion length LP of minority carriers in the source region (25),
The effective diffusion length of the minority carriers within is reduced. At the same time, a channel region (27) of the second conductivity type, a source region (25) of the first conductivity type, and a semiconductor region (28) of the second conductivity type
) forms a bipolar transistor structure.

Therefore, by applying a required potential to this second conductivity type semiconductor region (28) or by commonly connecting the second conductivity type semiconductor region (28) and the source region (25), the channel region (27
), a source region (25), and a second conductivity type semiconductor region (2
8) operates as a bipolar transistor, and the minority carrier current (for example, hole current in the case of an n-channel MISFET) generated in the channel region by impact ionization is transferred to the source region (25) of the first conductivity type and the source region (25) of the second conductivity type. Semiconductor region (can escape through two layers).

Therefore, it is possible to maintain the advantages of MISFET using an SOI substrate and prevent a decrease in source-drain breakdown voltage, and also to prevent short circuits and conduction phenomena when the element structure is made symmetrical, and It is possible to improve the reliability of the device itself and the range of application as a circuit element.

Further, in the second invention, a low concentration region (25c) is provided below the high concentration overhead (25a) as the source region (25) of the first conductivity type, and a channel is provided in contact with the low concentration region (25c). By providing the semiconductor region (28) of the second conductivity type separated from the region (27), the effective diffusion length of minority carriers in the source region, that is, its low concentration region (25c) can be increased as in the first invention. becomes small, and the second conductivity type channel region (27), the low concentration region (25c) of the first conductivity type source region, and the second conductivity type semiconductor region (
28) operates as a bipolar transistor, and the impact
The minority carrier current generated in the channel region by ionization is transferred to the low concentration region (25c) of the source region.
) and the second conductivity type semiconductor region (28). Moreover, since the low concentration region (25c) is used, the minority carrier current generated in the channel region by impact ionization easily flows into the second conductivity type semiconductor region (28), which further reduces the source-drain breakdown voltage. Therefore, it is possible to maintain the advantages of MISFET using a Sol substrate and prevent a decrease in source-drain breakdown voltage, and also to prevent short circuits and conduction phenomena when the device structure is made symmetrical. Therefore, it is possible to improve the reliability of the semiconductor device itself and the range of application as a circuit element.

Further, in the third invention, the drain region (26) of the first conductivity type, which is close to the source of generation of electron-hole pairs due to impact ionization, is in contact with the drain region (26) and is separated from the channel region (27). 2 conductivity type semiconductor region (47)
By setting the potential of this semiconductor region (47) to the source potential or a potential near it, the minority carrier current generated by impact ionization is transferred from the drain region (26) to the second conductivity type semiconductor region (47).
7). Therefore, 301
Maintaining the advantages of MISFET using a substrate, the source
It is possible to prevent the drain-to-drain breakdown voltage from decreasing.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings. In each embodiment, the present invention is applied to an n-channel old 5FET, but it goes without saying that the present invention can also be applied to a p-channel MISFET.

FIG. 1 shows an example of the invention. In this example, a Sol substrate (24) is used, which is formed by forming, for example, a silicon thin film (23) insulated into islands on a silicon substrate (21) via a 5iOz film (22). This Sol substrate (2
4) In the silicon thin film (23) made of p-type, a source region (25) and a drain region (26) of the first conductivity type, that is, n-type, are formed so as to reach the 5iO7 film (23) at the bottom. At the same time, a channel region (2) is formed on the outside of the source region (25) and in contact with the source region (25).
A p shadow region (28) of a conductivity type opposite to that of the source region (25) is formed so as to be separated from the source region (25). The distance (width) WN of the source region (25) between the p shadow region (28) and the channel region (27) is selected to be smaller than the diffusion length Lp of minority carriers, that is, holes, in the source region (25). A gate electrode (30) made of, for example, polycrystalline silicon is formed on the channel region (27) between the source region (25) and the drain region (26) via a gate insulating film (29) made of, for example, SiO□. Then, a source region (25), a drain region (
26) and the P shadow region (28), respectively, with a source electrode (31).
, a drain electrode (32) and an extraction electrode (33) are formed to constitute an n-channel M15FET (34).

2 to 4 show modifications of FIG. 1. In Figure 2, n
In the case where a shaped source region (25) and drain region (26) are formed to reach the bottom SiO□ film (22), and a p-type shadow region (28) is formed within the n-type source region (25). It is. In Figure 3, an n-type source region (2
5) and drain region (26) on the bottom SiO□ film (2).
2), and this n-type source region (2) is formed to a depth that does not reach 2).
This is the case where a P shadow area (28) is formed within 5).

Furthermore, FIG. 4 shows a case where a p-shade region (28) is formed in a part of an n-type source region (25) when viewed in plan.

Each M15FET (34
) to (37), a required voltage, such as a ground voltage, is applied to the extraction electrode (33) of the P shadow area (28).

According to this configuration, the p shadow region (28) is in contact with the n-type source region (25) and is separated from the p-type channel region (27).
) by having a P-type channel region (27), n
A pnp bipolar transistor structure is constructed in which the source region (25) and the shadow region (28) serve as emitter, base and collector, respectively. As a result, holes h (hole current IP), which are minority carriers generated by impact ionization occurring at the drain end, are taken out from the channel region (27) via the source region (25) and the P shadow region (28). This escapes to the electrode (33) side, making it possible to suppress a decrease in source-drain breakdown voltage due to impact ionization.

Although each side is a four-terminal element, the source region (25)
A three-terminal element can be constructed by externally connecting the and P shadow region (28) using an electrode metal or the like.

FIG. 5 shows an example of a three-terminal MISFET using the configuration shown in FIG.
A source electrode (31) straddles both so as to be commonly connected to the
This is the case where it is configured by forming. This 3-terminal M in Figure 5
FIG. 7 shows the simulation results of the source-drain breakdown voltage characteristics of ISFET (3B). Curve (n) is the characteristic of M15FET (38) according to this example, curve (1)
shows the characteristics of the conventional MISFET (11) in FIG. Here, each sample has a p-type channel region of 5×1
0110l5', the n-type source and drain regions have an impurity concentration of IXIO"cm-'. The impurity concentration of the P shadow region (28) according to this example is IXIO"cm-'.
It is o-3.

In addition, the thickness of the silicon thin film is 1000 mm, and the S of the Sol substrate is
The iO□ film thickness (bottom) was 1 μm, n゛ polycrystalline silicon was used as the gate electrode, and the gate voltage ■9 was set to -0.5■.

From this simulation result, the MISFE according to this example
T (38) is recognized to have improved source-drain breakdown voltage compared to MISFET (11) of conventional structure.

In the configurations shown in FIGS. 1 to 5 on the upper side, the P shadow area (2
8) on the source region (25) side and the drain region (26) side.
It is possible to arrange them symmetrically on the sides.

Figure 6 shows a three-terminal structure and L D D (Lightl
An example of a y doped drain structure is shown below. In this old 5FET (39), the high concentration region (25a) (
A source region (25) and a drain region (26) corresponding to the outside of the source region (25) and drain region (26) having the low concentration region (26a) and the low concentration region (25b) (26b), respectively.
P shadow regions (28A) and (28B) which are in contact with the channel region (27) and separated from the channel region (27) are formed.
5) and the P shadow region (288) are commonly connected by the source electrode (31), and the drain region (26) and the P shadow region (288) are connected in common by the source electrode (31).
B) are commonly connected by a drain electrode (32). In this case as well, the effective distance (width) WN of the symmetrical source region (25) and drain region (26) is the diffusion length of holes, which are minority carriers, in the source region (25) and drain region (26). Select smaller than LP. Incidentally, the drain electrode (32) and the source electrode (31) are connected to the power supply voltage Vdd and the ground voltage ■. is applied.

Here, for example, boron-doped polycrystalline silicon is used as the gate electrode (30), the thickness d of the silicon thin film (23) is 800, and the impurity concentration of the channel region (27) is 1.
The impurity concentration of the low concentration regions (25b) and (26b) of the source and drain regions is about 0110l4'.
About 110l7', high concentration area (25a) and (26a
) is set at about 10"cm-", and the p shadow region (28
The impurity concentration of (8) and (28B) can be set to about 10"cm-3.

In this way, according to the MISFET of each of the embodiments described above, it is possible to suppress a decrease in the source-drain breakdown voltage due to impact ionization. and,
Source area (25) and newly created P shadow area (28)
It can be used as a normal three-terminal element by externally connecting them in common using electrode metal or the like.

Furthermore, since this p shadow region (28) can be formed symmetrically on the source region (25) side and the drain region (26) side, it can also be used as a switching element such as an access transistor of a static RAM cell, for example. , it becomes possible to expand the range of application in circuit elements.

Further, the structure is simple as it is only necessary to form the P shadow region (28) outside the source region or outside the source and drain regions, and manufacturing is also facilitated.

Moreover, the advantages of elements using SOI substrates such as small parasitic capacitance, high degree of freedom in setting the impurity concentration in the channel region (27), resistance to alpha rays, and resistance to latch-up are not lost.

Next, in the aforementioned M15FET (34) of FIG. 1, the P shadow region (28) was formed in the silicon thin film (23), but as shown in FIGS. 8 to 11, the source region (25) ) on the source region (25) and separated from the P-type channel region (27) (
(41,)(4h)(413)(4L)].

Since the other configurations are the same as those in FIG. 1, corresponding parts are given the same reference numerals and detailed explanation will be omitted. P shadow area (41)
The distance WN between the source region (25) and the channel region (27) is selected to be smaller than the diffusion length LP of holes, which are minority carriers. Note that FIG. 8 shows an example in which the P shadow region (41,) is formed of single crystal silicon, and FIG. 9 shows an example in which the P shadow region (41□) is formed of polycrystalline silicon. In addition, FIGS. 10 and 11 show P-type regions (41,) and (41,)(
The P shadow region (413) is formed of polycrystalline silicon (with different widths w,, w,).

This is an example in which (41,) is used as a wiring, and when used as a wiring, it can be used in a three-terminal structure.

In the M15FETs (42) to (45) having such configurations, the p-type channel region (27), the n-type source region (25), and the p-shade region (41) ((41,) (41
□)(413)(41,)) to form a pnp bipolar transistor structure, the hole current 1p generated by impact ionization
can be released to the extraction electrode (33) through the P shadow region (41), thereby improving the source-drain breakdown voltage.

Figure 12 shows the source of MISFET (42) in Figure 8.
The simulation results of drain-to-drain breakdown voltage characteristics are shown.

The curve (DI) is the characteristic of the old 5FET (42) according to this example, and the curve (I) is the characteristic of the conventional MISFET (11) in Fig. 24.
shows the characteristics of

The sample is the same as the sample shown in FIG. 7 described above, except that the impurity concentration in the p shadow region (41) in this example is IXIO"cm-3. From the simulation results shown in FIG. The MISFET (42) according to the example has a conventional structure.
It is observed that the source-drain breakdown voltage is improved compared to SFET (11).

In addition, MISFETs (42) to (4) in FIGS. 8 to 11
5), the source region (25) and p shadow region (41
) can be used as a normal three-terminal element by connecting them externally using metal electrodes or the like. Furthermore, it is possible to form the P shadow region (41) symmetrically on the source region (25) side and the drain region (26) side.

Furthermore, the advantages of using the Sol substrate are that it is easy to manufacture like the upper side, has small parasitic capacitance, has a high degree of freedom in setting the impurity concentration in the channel region, is resistant to alpha rays, and is resistant to latch-up. It has the following effects.

FIG. 13 shows another example of the invention. In this example, S
For example, an n-type silicon thin film (
23), an n-type source region (25) and a drain region (
A channel region (27) is formed outside the drain region (26) in contact with the drain region (26).
A separate P shadow area (47) is formed. P shadow area (4
7) and the drain region (26) between the channel region (27)
The distance (width) WN is selected to be smaller than the diffusion length L2 of holes of minority carriers. Then, Si is placed on the channel region (27) between the source region (25) and the drain region (26).
A gate electrode (30) made of, for example, polycrystalline silicon is formed through a gate insulating film (29) made of n, etc., and a source region (25), a drain region (26), and a p shadow region (4
7) have a source electrode (31) and a drain electrode (32), respectively.
and an extraction electrode (48) to form MISFET (4
9). Here, the potential of the P shadow region (47) needs to be set not to the train potential but to the source potential or a potential near it. That is, as shown in the potential diagram of FIG. 15A (that is, the potential diagram on the X-X line of the configuration of FIG. 15B), the potential Pb of the p shadow region (47) is greater than the potential P1 of the channel region (27). It is also necessary that the

In the old 5FET (49) with such a configuration, a P shadow region (47) is formed on the drain region (26) side near the source of electron-hole pairs caused by impact ionization. The generated holes can be extracted from the drain region (26) through the P shadow region (47), and the source-drain breakdown voltage can be improved. FIG. 14 shows simulation results of the source-drain breakdown voltage characteristics of MISFET (49) according to this example. curve(
IV) is the characteristic of the MISFET (49) according to this example, and curve (1) is the characteristic of the conventional MISFET (49) in FIG. The curve (I[) shows the characteristics of the 1ISFET (11) and the characteristic of the old 5FET (34) in FIG. In addition, the sample has an impurity concentration of 1×1018CTll in the P shadow region (47) of this example, and
The sample is the same as the sample shown in FIG. 7 above, except that the potential of ) is set to 0■, which is the same as the source potential. From this simulation result, the MISFET (49) according to this example has a conventional structure.
It is observed that the source-drain breakdown voltage is improved compared to SFET (11).

The structure of this MISFET (49) is similar to that shown in Fig. 1 except that it cannot be made into a three-terminal structure.
This provides the same effect as T(34).

FIG. 16 shows still another example of the present invention. In this example, a low concentration region (22) reaching the bottom SiO□ film (22) is formed under the high concentration region (25a) and (26a) in the silicon thin film (23) of the n-type, for example, of the Sol substrate (24).
an n-type source region (25c) and (26c);
5) and a drain region (26), and a high concentration region (25a) and a low concentration region (25a) of this source region (25).
pY3 separated from the channel region (27) in contact with 5c)
A region (28) is formed. Si is formed on the channel region (27) between the source region (25) and the drain region (26).
A gate electrode (30) made of, for example, polycrystalline silicon is formed through a gate insulating film (29) made of O□, etc.
), and a drain electrode (32) is formed in the high concentration region (26a) of the drain region.
is formed to constitute a MISFET (51). Here, the high concentration regions (25a) and (26a) are for lowering the source resistance and drain resistance, respectively, and the low concentration region (25c) is for reducing the hole current generated by impact ionization, which will be described later, into the P shadow region. (28
) to make it easier to flow. Low concentration area (25
The width WH of c) is selected to be smaller than the diffusion length of the minority carrier hole.

According to this configuration, the P-type channel region (27), n
The low concentration region (25C) and the p shadow region (28) of the shaped source region (25) operate as a pnp bipolar transistor, which serves as the emitter, base and collector, respectively, and as in the case of FIG. Hole h of generated minority carrier (hole current 1p
) escapes from the channel region (27) to the source electrode (31) side via the p shadow region (28), making it possible to suppress a decrease in source-drain breakdown voltage due to impact ionization. Moreover, in this example, by providing the low concentration region (25c), holes flow more easily than in FIG. 1, and therefore, it is possible to further improve the source-drain breakdown voltage.

In other words, the channel current of the MISFET using the SO■ substrate is 12
, if the electron current when the channel potential is higher than the source potential and bipolar operation is 17, then the drain current is ■.

is 1,=L+1. + IP---(1).

The hole current Tp generated by the channel current IC and the electron current I7 is expressed as follows, where the generation ratio is K(Vo): 19 = K(Vn)(IC+I, ,) ・
...(2) becomes.

Also, Ip=S (qDpn,”/NoWH)(e”In””
'S (QDnn;"/Na-L) (e"...(3)...(4) where, Dp: hole diffusion coefficient S: junction area n,: intrinsic carrier concentration ND: source low concentration Donor concentration WH in the region (25c): Width D7 of the source low concentration region (25c): Electron diffusion coefficient NA: Acceptor concentration L in the channel region (27): Length V of the channel region (27): Source and channel The potential difference between them is based on the above equations (1) to (4).

Therefore, the concentration ND of the low concentration region (25C) of the source region
The smaller the width WN is, the smaller the drain current ID becomes and the higher the drain breakdown voltage becomes.

Furthermore, in the configuration shown in FIG. 16, the silicon thin film (23
) is insulated from the substrate (21) by the SiO□ film (22), so there is no substrate effect and the MISFET (51
) can increase the current drive capability of the device. In addition, minority carriers generated by α rays can also escape to the source region side, making it even more resistant to α rays.This example also has the advantage that the source and train can be made symmetrically, and manufacturing is easy. It has the same effects as shown in Figure 1, such as small parasitic capacitance, high degree of freedom in setting channel impurity concentration, resistance to alpha radiation, and resistance to latch-up, which are the advantages of using an SOI substrate. be.

FIG. 17 shows an example in which the source region side and the drain region side are symmetrical. In this example, a P-type silicon thin film (23
) with high concentration regions (25a) and (26a) and LDD, respectively.
(7) n having low concentration regions (25b) and (26b)
In addition to forming a shaped source region (25) and drain region (26), high concentration regions (25a) and (26a) are formed.
), each having a low concentration region (27) in contact with the channel region (27).
25c) and (26c) are formed. Then, the respective low concentration regions (25c) and (26c) and high concentration region (25a)
) and (26a) to form P shadow regions (28A) and (28B) that are separated from the channel region (27).

The source region (25) and the p shadow region (28A) are commonly connected by the source electrode (31), and the drain region (2
6) and the P shadow region (28B) are commonly connected by a drain electrode (32). Here, for example, phosphorus-doped polycrystalline silicon is used as the gate electrode (30),
The thickness d of the silicon thin film (23) is about 1500. The impurity concentration of the 1 channel region (27) is about 10"ClO-3, and the high concentration regions of the source and drain regions (25a).
The impurity concentration of (26a) was set to about 10"cm-3, L
The impurity concentration of the low concentration regions (25b) and (26b) of the DD is set to about 10"cm-", and the low concentration regions (25c) and (26b) of the DD are
The impurity concentration of 26c) can be about 10'5 to 10"cm-".

Since the source and drain can be formed symmetrically in this way, it can be used as a switching element such as an access transistor of a static RAM cell.

In addition, in Fig. 16, the 3-terminal structure is used, but as in Fig. 1, the 4-terminal structure is used.
It can also have a terminal structure.

Next, in the old 5FET according to the present invention described above, when the source region (25) and the p shadow region (28) are commonly connected and used as a three-terminal element, the source region (25) and SiO across the P shadow area (28)
□A window hole (55) is formed in the membrane (54), and the bicephalic area (
25) and (28), a common metal electrode such as M
An electrode (31) will be formed. in this case,
Considering the minimum dimension l of the window hole (55), 1 = xp m
in + Xn m=n +2 A. Here, X
p*in and Xnm1. are the required minimum dimensions of contact with the P-type region (28) and the N-type source region (25), respectively, and are determined by the contact resistance and window hole dimensional accuracy (photolithography accuracy, etching accuracy). A
is the overlay accuracy of the photoresist, which involves two photoresist steps: one to determine the p"-n" junction, and the other to determine the position of the window hole (55) in the 5in2 film (54). And χpmin l Xn min and A
If the contact window holes (55) are each 0.2 μm, the minimum dimension of the contact window hole (55) is 0.8 μm, which has a distortion that makes it unsuitable for highly integrated devices.

FIG. 18 shows an embodiment that improves this point. Although this example will be described with reference to the case where it is applied to the configuration shown in FIG. 6 described above, it can also be applied to the other embodiments described above.

First, as shown in FIG. 18A, an n-type source region (25) and a drain region (26) of an LDD structure are formed on the silicon thin film (23) of the Sol substrate (24), and P shadows are formed symmetrically on the outside thereof. After forming regions (28A) and (28B) and forming a gate electrode (30) made of polycrystalline silicon via a gate insulating film (29), a film (57) of a high melting point metal such as T is deposited on the entire surface. Form.

Next, as shown in FIGS. 18B and 18C, heat treatment is performed to silicide the T and other Ts except for the silicide film (58).
, removing the membrane (57). The T, silicide film (58) covers a portion spanning the source region (25) and the P shadow region (288), a portion spanning the drain region (26) and the P shadow region (28B), and the surface of the gate electrode (30). It is formed.

After that, as shown in Figure 18, a SiO□ film (
54), and contact window holes (55) are formed respectively through a photoresist, and then, for example, a source electrode (31), a drain electrode (32), and a gate lead-out electrode are formed by M through a barrier metal as necessary. (30A) to obtain the desired MISFET (59).

According to M15FET (59) with such a configuration, T,
Since the p shadow region (28A) and the source region (25) or the p shadow region (28B) and the drain region (26) are connected to each other by the silicide film (58), there is no window for the next M contact. The hole (55) can be formed by forming a contact window with a minimum pattern determined by the resolution of the photoresist, and the minimum dimension of the contact window hole (55) is smaller than that shown in FIG. 19. Therefore, it becomes possible to miniaturize elements and make highly integrated devices possible.

On the other hand, in the configuration shown in FIG. 1, the short channel effect does not occur because the silicon thin film (23) can be formed with a relatively thin film thickness.However, the low concentration regions (25c) and (26c) in FIG. In a structure having a silicon thin film (23), the thickness of the silicon thin film (23) becomes large, which causes a short channel effect (that is, the controllability by the gate voltage becomes weak), which causes an increase in leakage current, etc. To counteract the effect, the channel region (27) needs to be heavily doped.

Further, when phosphorus-doped polycrystalline silicon is used as the gate electrode (30), the channel concentration, particularly the concentration at the channel surface, is increased in order to control the threshold voltage V. - As an example, the concentration of the channel region (27) is 10"c as explained above in FIG.
The concentration of the low concentration regions (25c) and (26c) of the source and drain regions (10I S
~ l Q I 6 cm -3) is higher than the channel region (27).
The M 15FET (52) shown in the figure is difficult to manufacture using conventional techniques.

FIGS. 20 and 23 show this M 15FET (52
) is shown below.

The example shown in FIG. 20 will be explained. First, as shown in FIG. 20A, a gate electrode (30) made of phosphorus-doped polycrystalline silicon is formed on a silicon thin film (23) via a gate insulating film (29).
is formed, and using this gate electrode (30) as a mask, an LD
N-type low concentration regions (25b) and (26b) for D are formed.

Next, as shown in FIG. 20B, the gate electrode (30) is
After forming the iO2 sidewalls (61), the channel region is approximately 10"CIl+-' (for example, the bottom part is 10"
A p-type impurity, such as boron (64), is ion-implanted so that the surface is approximately 016C13 cm-3 or more. Here, this ion implantation serves both to control the threshold voltage and to prevent the short channel effect.

In this ion implantation, an ion implantation peak (64) appears near the bottom of the channel region (27) through the gate electrode (30).
This is done so that the concentration profile exists.

FIG. 21A shows the concentration profile on line A-A passing through the channel region (27) after ion implantation and activation annealing, where (62) is the concentration profile of boron, and (63)
) is the concentration profile of the gate electrode (30) made of n+ polycrystalline silicon. Therefore, the ion implantation peak (6
42) enters the underlying SiO□ film (22), and the boron concentration is extremely low. In other words, the n-type low concentration region (25
c) The concentration is lower than that of (26c).

FIG. 21B shows the concentration profile on the line B--B passing through the source region (25) (or drain region (26)), and (62) is the concentration profile of boron.

(65) is a concentration profile of a high concentration region (25a) (or (26a)) and a low concentration region (25c) (or (26c)) of the source region (or drain region), which will be described later.

Thereafter, as shown in FIG.
n-type low concentration region of ln-' level (25c) (26c)
Then, a high concentration n-type impurity (67) is ion-implanted to form high concentration regions (25a) and (26a) of, for example, 102102O' on the n-type low concentration regions (25c) and (26c). Form.

Here, source regions (25) are formed in regions (25a) (25b) (25c), and regions (26a) (26
b) At (26c) a drain region (26) is formed.

Next, as shown in Figure 20, a photoresist mask (6
8), a P-type impurity such as boron (69) is ion-implanted through the source region (25) and drain region (26).
Outside the channel region (27) and separated P shadow region (
28A) and (28B) are formed. After that, a source electrode and a drain electrode are formed, and the MISFET (
52) is obtained. According to this manufacturing method, the gate electrode (30)
Since it is possible to increase the concentration only in the channel region (27) by ion implanting boron (64) using the film thickness of Low concentration areas (25c) and (26c)
can be formed. Therefore, the MISFET (52) of FIG. 17, which prevents the short channel effect, can be manufactured easily and with high precision on a self-aligned line.

In addition, this type of MI has a gate electrode of phosphorus-doped polycrystalline silicon, which requires high concentration in the channel region because the threshold voltage needs to be controlled.
SFET can be easily formed.

In addition, when the concentration difference between the n-type low concentration regions (25c), (26c) and the channel region (27) is made larger, 5iO is deposited on the gate electrode (30) as shown in FIG.
An insulating film (71) such as Z is provided to increase the step height, and boron (64) is ion-implanted in this state. After ion implantation, the insulating film (71) is removed. In this configuration, the boron concentration in the source region (25) and drain region (26) becomes even lower, and the n-type low concentration region (25c) (
The concentration of 26c) can be lower.

Next, the example shown in FIG. 23 will be explained. First, as shown in FIG. 23, a 5iOz film (74) is deposited on the main surface of the silicon thin film (23) by the CVD method, and then a film corresponding to the channel region is formed through a photoresist mask (not shown). A portion of the Sin film (74) is selectively removed by RIE (reactive ion etching) to form an opening (75).

Next, in order to remove damage caused by RIE, sacrificial oxidation is performed to form a sacrificial oxide film with a thickness of about 20 nrrl. After removing the sacrificial oxide film by wet etching, a gate oxide film (29) is formed on the surface corresponding to the channel region.

Next, as shown in FIG. 23B, using the SiO□ film (74) as a mask, boron (64
) For example, ions of BF2" are implanted. As a result, the channel region (27) becomes, for example, about 10" cm.

Next, as shown in FIG. 23C, polycrystalline silicon (76
) is deposited so as to fill the opening (75), and is etched back and planarized. Then, as shown in Figure 23, after depositing and forming a PSG (phosphosilicate glass) film (77), a phosphorus-doped polycrystalline silicon film (76) is diffused from the PSG film (77) to form a phosphorous-doped polycrystalline silicon film (76). A gate electrode (30) made of crystalline silicon is formed.

Next, PSG film (77) and CVD5i (h film (74)
is removed by RI, and then the surfaces corresponding to the source and drain regions and the surface of the gate electrode (30) made of polycrystalline silicon are respectively oxidized to form a SiO□ film (78).

Next, as shown in FIG. 23G, using the gate electrode (30) as a mask, a low concentration n-type inert substance (79) is ion-implanted to form LDD On-type low concentration regions (25b) (26b). . Next, CVD5iO is applied to the side surface of the gate electrode (30).
A side wall (61) is formed using □, and a relatively low concentration n-type inert substance (66) is ion-implanted with high energy using the gate electrode (30) and side wall (61) as a mask to form a lower part. n-type low concentration region (25c) and (2
6c) and a relatively high concentration of n at low energy.
By ion-implanting a shapeless substance (67), n-type high concentration regions (25a) and (26a) are formed in the upper part, and an n-type source region (25) and drain region (26) are formed therein. .

Next, as shown in FIG. 23G, for example, a P engraving blunt (69) is ion-implanted into the outside of the source region (25) and drain region (26), respectively, through a resist mask (80). Regions (28A) and (28B) are formed. Thereafter, a SiO□ film (81) is formed, a window hole for contact is formed, and a source electrode (31) and a drain electrode (32) are formed therein to form the intended MISFET (82).

Also in this manufacturing method, MI having n-type low concentration regions (25c) (26c) with lower concentration than the channel region (27)
SFET can be easily formed. In this embodiment of FIG. 23, the boron (64) implant is in the channel region (
27), so ultimately the channel region (2
7) and the low concentration regions (25c) and (26c) is possible even if the difference in concentration is large.

In the manufacturing method shown in FIGS. 20 and 23, the source electrode (31) and drain electrode (32) can also be formed using the silicide film shown in FIG. 18.

〔Effect of the invention〕

According to the present invention, MIS formed using a Sol substrate
without sacrificing the advantages of type semiconductor devices.
A decrease in breakdown voltage due to ionization can be suppressed, and the reliability of the MIS semiconductor device itself can be improved. Further, it is possible to use the device as a normal three-terminal device, and it is also possible to form the source side and the drain side symmetrically, thereby widening the range of applications as a circuit device.

[Brief explanation of drawings]

1 to 3 are block diagrams showing embodiments of the invention, FIG. 4 is a plan view showing another embodiment of the invention, and FIGS. 5 and 6 are diagrams showing still other embodiments of the invention. FIG. 7 is a diagram showing the source-drain breakdown voltage characteristics of the MISFET shown in FIG. 5. FIGS. 8 and 9 are diagrams showing still other embodiments of the present invention. 11 are plan views showing still other embodiments of the present invention, and FIG. 12 is an MI of FIG. 8.
Diagram showing the source-drain breakdown voltage characteristics of SFET, 1st
3 is a block diagram showing still another embodiment of the present invention, FIG. 14 is a diagram showing its source-drain breakdown voltage characteristics, FIG. 15 is a potential diagram, and FIGS. 16 and 17 are respectively diagrams showing still another embodiment of the present invention. 18A to 18D are manufacturing process diagrams showing still another embodiment of the present invention, FIG. 19 is a sectional view for explaining the present invention, and FIGS. 20A to 20D are block diagrams showing another embodiment. A manufacturing process diagram showing another manufacturing method example of an MTS type semiconductor device according to the present invention, FIGS. 21A and 21B are impurity concentration profile diagrams of important parts during the manufacturing process, and FIG. 22 is a manufacturing process diagram showing still another manufacturing method according to the present invention. 23A-H are manufacturing process diagrams showing still another manufacturing method example according to the present invention, FIGS. 24 to 26 are configuration diagrams showing a conventional example, and FIG. 27 and FIG. 28 are configuration diagrams showing a proposed example. (21) is a silicon substrate, (22) is a SiO2 film, (2
3) is a silicon thin film, (24) is an SOI substrate, (25)
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Claims (1)

[Claims] 1. An MI in which a semiconductor layer is formed on an insulating substrate, and a gate electrode is formed on the semiconductor layer with a gate insulating film interposed therebetween.
An S-type semiconductor device comprising a second conductivity type semiconductor region in contact with a first conductivity type source region and separated from a channel region. 2. MI in which a semiconductor layer is formed on an insulating substrate, and a gate electrode is formed on the semiconductor layer via a gate insulating film.
In the S-type semiconductor device, the source region of the first conductivity type has a high concentration region and a low concentration region below the high concentration region, and is in contact with the low concentration region of the source region of the first conductivity type and is separated from the channel region. A MIS type semiconductor device comprising a semiconductor region of a second conductivity type. 3. MIS in which a semiconductor layer is formed on an insulating substrate, and a gate electrode is formed on the semiconductor layer via a gate insulating film.
A MIS type semiconductor device comprising a second conductivity type semiconductor region in contact with a first conductivity type drain region and separated from a channel region.