JPH0467670A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To enable a semiconductor memory to be shortened in manufacturing process and lessened in level deference and to protect a voltage drop preventing aluminum wire against disconnection at a step and short circuits by a method wherein adjacent gate electrodes are made to constitute electrodes of a capacitor. CONSTITUTION:A trench is provided to a silicon substrate 1, and a diffusion layer 2 connected to a bit line and a diffusion layer 2a serving as a counter electrode of a capacitor electrode are formed. Word lines 4a and 4b of polysilicon serving also as a capacitor electrode are formed through the intermediary of a capacitor oxide film 3a, and the trench is filled with a polysilicon 5. At the same time, word lines 4b and 4c of polysilicon are formed through the intermediary of a gate oxide film 3. Furthermore, a bit line 7 of tungsten silicide is formed through the intermediary of an interlaminar insulating film 6. In the equivalent circuit concerned, transistors Q1 and Q2 are connected to the intersections of the bit line 7 extending longitudinally with the word lines 4 extending laterally respectively, the transistors Q1 and Q2 are connected to capacitors C1 and C2 through the intermediary of the diffusion layer 2a, and the C1 and C2 are connected to capacitor electrodes 4a and 4b which serve also as word lines.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a memory cell of a semiconductor memory.

[Conventional technology]

Regarding a semiconductor memory according to the prior art, FIG. 2(a) is a plan view, and FIG.
This will be explained with reference to b).

A trench is formed in a silicon substrate 1, in which a diffusion layer 2 connected to a bit line and a diffusion layer 2a serving as a counter electrode of a capacitor electrode are formed.

A capacitor electrode 8 made of polysilicon is formed via a capacitor oxide film 3a, and the trench is further filled back with polysilicon 5.

Word lines 4a, 4b, 4C24d made of polysilicon are formed with gate oxide film 3 interposed therebetween.

In this way, apart from the capacitor electrode 8, the gate electrodes 4a, 4b,
It had a two-layer electrode structure in which 4C14d was formed.

Further, a bit line 7 made of tungsten silicide is formed with a glabellar insulating film 6 interposed therebetween.

The equivalent circuit is shown in FIG.

Transistors Q1 and Q2 are connected to the intersection of the bit line 7 running in the vertical direction and the word line 4 running in the horizontal direction, and capacitors C1 and C2 are connected to each other via the diffusion layer 2a. It is connected to a capacitor electrode 8 maintained at a constant voltage of 2Vcc.

[Problem to be solved by the invention]

The memory cell has a two-layer electrode structure in which a capacitor electrode and an independent gate electrode are formed.

Therefore, there was a problem that the structure became complicated and the number of manufacturing steps increased.

Furthermore, because of the two-layer polysilicon structure, there is a disadvantage in that the number of steps increases and the bit line serving as the upper layer interconnection may be disconnected.

In addition, the aluminum lining wire used to reduce the resistance of the word line was prone to breakage and short circuits.

[Means to solve the problem]

In the semiconductor memory of the present invention, in a semiconductor memory cell consisting of one transistor and one capacitor, adjacent gate electrodes constitute a capacitor electrode of the capacitor.

〔Example〕

Regarding one embodiment of the present invention, the plan view of FIG. 1(a) and
This will be explained with reference to FIG. 1(b), which is a sectional view taken along the line AB in FIG. 1(a).

A trench is formed in a silicon substrate 1, in which a diffusion layer 2 connected to a bit line and a diffusion layer 2a serving as a counter electrode of a capacitor electrode are formed.

Word lines 4a and 4d made of polysilicon which also serve as capacitor electrodes are formed through the capacitor oxide film 3a, and the trenches are further filled back with polysilicon 5.

At the same time, word lines 4b and 4C made of polysilicon are formed with gate oxide film 3 interposed therebetween.

Further, a bit line 7 made of tungsten silicide is formed with a glabellar insulating film 6 interposed therebetween.

The equivalent circuit is shown in FIG. 3 by a bit line 7 running vertically.
Transistors Ql and Q2 are connected to the intersection of the word line 4 and the word line 4 running in the horizontal direction, and capacitors CI and C2 are connected through the diffusion layer 2a, respectively. It is connected to the.

Consider the case where a voltage is applied to the gate electrode 4b and data input from the diffusion layer 2 connected to the bit line 7 is stored in a capacitor constituted by 4a and 2a. All unselected gate electrodes are kept at a constant voltage, so
The opposite electrode of a capacitor is always at a constant voltage.

Next, assume that a voltage is applied to the gate electrode 4a in order to transfer data to/from another cell while charges are accumulated in the cell 2a.

In this case, since no voltage is applied to the gate voltage &4b, 2a remains isolated and no charge enters or exits from the outside.

Furthermore, when reading the data input to 2a, since the gate electrode 4a has returned to the same voltage as when it was input,
The same data as input appears on bit line 7.

〔Effect of the invention〕

By using the gate electrode instead of providing an independent capacitor electrode, the memory cell structure is simplified and the manufacturing process is shortened.

The number of polysilicon electrodes has been further reduced, reducing the level difference.

We were able to eliminate breaks and short circuits in the aluminum wires formed on the upper layer of bit lines and word lines to prevent voltage drops.

[Brief explanation of drawings]

FIG. 1(a) is a plan view showing the first embodiment of the present invention, FIG. 1(b) is a sectional view taken along the line A-B in FIG. 1(a), and FIG.
) is a plan view showing a semiconductor memory according to the prior art, FIG. 2(b) is a sectional view taken along line AB in FIG. 2(a), and FIG. 3 is an equivalent circuit diagram of the semiconductor memory. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Diffusion layer, 2a... Counter electrode of capacitor electrode, 3... Gate oxide film, 3a... Capacitor oxide film, 4 a, 4 b, 4 c, 4 d
- word line, 5... polysilicon, 6... interlayer insulating film, 7... bit line, 8... capacitor electrode.

Claims (1)

[Claims] 1. A semiconductor memory characterized in that, in a memory cell consisting of one transistor and one capacitor, adjacent gate electrodes serve as capacitance electrodes of the capacitor.