JP2000243928A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a memory cell of a dynamic type by using a mono-layer of polycrystalline silicon. SOLUTION: Plate electrodes 13 are arranged so as to overlap strip-shaped semiconductor regions 11 at their respective both ends. Gate electrodes 14 that cross the semiconductor regions 11 are arranged at a certain distance from the respective plate electrode 13. The plate electrodes 13 and the gate electrodes 14 are formed by a same mono-layer of polycrystalline silicon. Bit lines 15 are arranged along the respective semiconductor regions 11, crossing the plate electrodes 13 and the gate electrodes 14. Pieces of intermediate wiring, 17 and 18, are formed between the bit lines 15. The bit lines 15 are connected to the respective semiconductor regions 11, while the pieces of intermediate wiring, 17 and 18, are connected to the respective gate electrodes 14. Word lines 21 are arranged on the plate electrodes 13 and on the gate electrodes 14, crossing the bit lines 15, and are connected to the gate electrodes 14 via the pieces of intermediate wiring, 17 and 18, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a dynamic semiconductor memory device suitable for being integrated on a semiconductor substrate together with a logic circuit.

[0002]

2. Description of the Related Art FIG. 3 is a plan view showing a structure of a conventional dynamic type semiconductor memory device.

On one main surface of a P-type semiconductor substrate, a plurality of N-type semiconductor regions 1 are formed in a strip shape. This semiconductor region 1 extends in the column direction, and is evenly divided into an even column and an odd column.
They are arranged in a matrix so as to be shifted in pitch. The groove 2 is formed on one main surface of the semiconductor substrate so as to overlap both ends of the plurality of semiconductor regions 1. The plate electrode 3 is made of polycrystalline silicon, and is formed on the semiconductor substrate so as to overlap the groove 2 via an insulating film. The plate electrode 3 is disposed so as to straddle between two semiconductor regions 1 adjacent in the column direction. Thereby, the semiconductor region 1 is formed in the groove 2.
Then, a trench capacitor for retaining charges between the plate electrodes 3 is formed.

The word line 4 is made of polycrystalline silicon.
A plurality of the electrodes extend in the row direction so as to intersect with the semiconductor region 1 and are arranged in parallel on the plate electrode 3 via an insulating film. These word lines 4 function as gate electrodes for the semiconductor region 1 in one of the even columns and the odd columns. That is, when one of the word lines 4 is in contact with the semiconductor region 1 via the thin insulating film in the odd columns, the even line is in contact with the semiconductor region 2 with the plate electrode 3 interposed therebetween. It does not affect the semiconductor region 1. In an actual semiconductor memory device, the semiconductor region 1 is formed by implanting an N-type impurity using the word line 5 as a mask, so that the semiconductor region 1 is divided in the column direction by the word line 4. .

The bit line 5 is made of aluminum, extends in the column direction along the semiconductor region 1, and has a word line 54.
Are arranged via an insulating film. The bit line 5 is electrically connected to the semiconductor region 1 through a contact hole 6 at a gap between the word lines 4. The semiconductor region 1 to which the bit line 5 is connected is an island-like region separated from the trench capacitor by the word line 4, and electrically independently forms a drain region. This drain region is commonly used in memory cells adjacent in the column direction. As a result, the word line 4 is used as a gate electrode,
An N-channel memory cell transistor is formed using the semiconductor region 1 divided by the above as a source region and a drain region. Then, a dynamic memory cell is formed in which the trench capacitor connected to the source region is connected to the bit line 5 in response to the selection control of the word line 4, that is, the ON / OFF control of the memory cell transistor. .

In such a semiconductor memory device,
When one of the word lines 4 is selected, two memory cells adjacent in the row direction are not selected at the same time. That is, in a normal dynamic memory device, a dummy cell is connected to each bit line, and when a memory cell is selected on one of adjacent bit lines,
On the other hand, in order to be able to select a dummy cell, the configuration is such that a row address can be independently specified in memory cells adjacent in the row direction.

[0007]

With the increase in the number of functions of a semiconductor integrated circuit, it is desired to integrate various logic circuits and memory circuits into one chip. Generally, a logic circuit having a digital configuration is configured by insulated gate transistors. When the logic circuit is integrated, wiring between gate electrodes is formed on a polycrystalline silicon layer (one layer) serving as a gate electrode. Are laminated in two or three layers. On the other hand, in the case of the above-described memory cell, the plate electrode 3 and the word line 6 are arranged so as to overlap with each other. An eye polycrystalline silicon layer is stacked, and further, an aluminum layer serving as a wiring is stacked. Therefore,
In the case where the memory cell is formed into one chip simultaneously with the logic circuit, the wiring structure is different between the memory cell portion and the logic circuit portion, so that the respective wires cannot be formed in the same step.

Accordingly, it is an object of the present invention to provide a memory cell portion having the same wiring structure as a logic circuit portion so that a memory cell can be formed on the same substrate as a logic circuit in the same step.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is characterized in that a semiconductor region formed in a strip shape on one main surface of a semiconductor substrate is provided. A gate electrode disposed on the semiconductor substrate so as to intersect the semiconductor region and divide the semiconductor region into first and second regions; and a first electrode formed of the same layer as the gate electrode.
A plate electrode that is arranged to overlap with the first region and forms a capacitance with the first region; a plate electrode that is arranged on the gate electrode and the plate electrode along the semiconductor region; A bit line that is electrically connected, an intermediate wiring that is arranged on the same layer as the bit line so as to overlap the gate electrode, and that is electrically connected to the gate electrode;
A word line disposed on the bit line and the intermediate wiring so as to extend in a direction crossing the bit line, and electrically connected to the intermediate wiring, wherein the gate electrode and the plate electrode are the same. And the intermediate wiring and the bit line are formed in the same step.

According to the present invention, the plate electrode forming the capacitor and the gate electrode of the memory cell transistor are formed in the same layer so as not to overlap with each other, so that the memory cell can be formed using one polycrystalline silicon layer. Can be formed.

[0011]

FIG. 1 is a plan view showing the structure of a semiconductor memory device according to the present invention.

On one main surface of a P-type semiconductor substrate, a plurality of N-type semiconductor regions 11 are formed in a strip shape. The semiconductor region 1 extends in the column direction and is arranged with both ends aligned. The groove 12 is formed on one main surface of the semiconductor substrate so as to overlap both ends of the plurality of semiconductor regions 1. The plate electrode 13 is made of polycrystalline silicon, and is formed on the semiconductor substrate via the insulating film so as to be continuous with the groove 12 in the row direction. As a result, a trench capacitor that holds charges between the semiconductor region 11 and the plate electrode 13 is formed in the trench 12.

The gate electrodes 14 are arranged between the plate electrodes 13 so as to intersect the semiconductor region 11 at a predetermined distance of two each. The gate electrode 14 is formed independently in two columns and is formed in the same layer as the plate electrode 13 in the same step. The bit line 15 is made of, for example, aluminum, extends in the column direction along each semiconductor region 11, and is arranged on the gate electrode 14 via an insulating film. The bit line 15 is electrically connected to the semiconductor region 11 through the contact hole 16 between the gate electrodes 14. Semiconductor region 11 to which bit line 15 is connected
Are island-shaped regions separated from the trench capacitors by the gate electrodes 14, and electrically independently constitute drain regions. The intermediate wirings 17 and 18 are
Between the gate electrodes 14 and extend in the column direction. One intermediate wiring 17 is connected to the plate electrode 13.
The other intermediate wiring 18 is formed so as to extend up.
Are formed short enough to protrude slightly from the end of the gate electrode 14. The intermediate wirings 17 and 18 are connected to the bit line 1
5 is formed in the same layer and in the same process as the contact hole 1.
The electrodes 9 and 20 are electrically connected to the gate electrode 14, respectively.

The word line 21 is made of, for example, aluminum, extends in a direction crossing the bit line 15, and is arranged on the bit line 15 and the intermediate wiring 17 via an insulating film. The word line 21 is disposed on the plate electrode 13 and the gate electrode 14, is electrically connected to the intermediate wiring 17 through the contact hole 22 on the plate electrode 13, and is electrically connected to the intermediate wiring 18 through the contact hole 23 on the gate electrode 14. Is electrically connected to Therefore, each word line 21 is connected to the gate electrode 14 via the intermediate wirings 18 and 19.
And applies a selection signal to each gate electrode 14.

Here, every other word line 21 is connected to the gate electrodes 14 arranged on the same row. That is, the gate electrodes 14 arranged corresponding to the 4n columns (n is an integer) and 4n + 1 columns are commonly connected to the word lines 21 arranged in the 4n + 1 and 4n + 2 rows, respectively.
+2 columns and 4n + 3 columns have gate electrodes 14 arranged in 4n rows and 4n + 3 rows, respectively.
Are connected in common. Thereby, each word line 21 can be activated by selecting two memory cell transistors adjacent in the row direction as one set, and selecting every other set for each row.

In the above-described memory cell, the gate electrodes 14 are connected to the sense amplifier by combining columns separated from each other. That is, in a dynamic memory device, two adjacent bit lines are selected at the same time, a memory cell is connected to one bit line, and a dummy cell is connected to the other bit line. Are combined to form a column desense amplifier.
Incidentally, the dummy cell can be substituted by using the parasitic capacitance of the bit line.

FIG. 2 is a circuit diagram of a semiconductor memory device according to the present invention. This figure shows a configuration in which memory cells for two columns, dummy cells for one row, and sense amplifiers are added to the semiconductor memory device shown in FIG.

The memory cell transistor MT includes a gate electrode 14 and a semiconductor region 11 divided by the gate electrode 14, and a plurality of the memory cell transistors MT are arranged in a matrix. The capacitor MC includes a semiconductor region 11 formed in the trench 12 and a plate electrode 13 covering the semiconductor region. The capacitor MC is connected to the source of each memory cell transistor MT by sharing the semiconductor region 11.

The bit line 15 is arranged so as to correspond to each column of the memory cell transistors MT, and the drain of the memory cell transistor MT is connected to each column. Two word lines 21 are arranged for each row of the memory cell transistors MT, and the gates of the memory cell transistors MT in two consecutive columns are connected to one of the two via the intermediate wirings 17 and 18, respectively. That is, the gates of the memory cell transistors MT arranged in the 4n column and the 4n + 1 column are connected to one of the word lines 21 arranged in pairs via the intermediate wiring 17, and the other is connected to the 4n + 2 column and the 4n column.
The gates of the memory cell transistors MT arranged in the +3 column are connected via the intermediate wiring 18.

Dummy cell transistor DT has the same structure as memory cell transistor MT, and each bit line 1
5 is connected in parallel with the memory cell transistor MT. Dummy capacitors DC have the same structure as capacitor MC, and are connected to the sources of dummy cell transistors DT, respectively. As with the word line 21, two dummy word lines 24 are arranged for one row of dummy cell transistors DT, and two columns of continuous dummy cell transistors DT are commonly connected. Thereby, the dummy cell transistors DT are selectively activated in units of two columns.

The sense amplifier 25 is connected every two bit lines 15. At this time, each bit line 15 is a column connected to the same sense amplifier 25, and the word line 21 is shared and the memory cell transistors M selected simultaneously are selected.
A combination is selected such that T is not connected to each. That is, when the word line 21 is shared by the 4n and 4n + 1 columns and the word line is shared by the 4n + 2 and 4n + 3 columns, the bit lines 15 of the 4n + 1 and 4n + 2 columns
Are connected to the same sense amplifier 25, and 4n + 3 columns and 4
The n columns of bit lines 15 are connected to the same sense amplifier 25. Then, 2 connected to one sense amplifier 25
One of the bit lines 15 has a memory cell transistor MT
Is connected, the other is a dummy cell transistor D
T is connected. As a result, the sense amplifier 25 reads the difference between the storage contents of the dummy cell and the memory cell.

The dummy cell transistor DT and the dummy capacitor DC need not be arranged when the parasitic capacitance of the bit line 15 is used as a substitute for the dummy capacitor DC, and the dummy word line 24 is unnecessary.

In the above memory device, the same operation as that of the conventional memory device shown in FIG. 3 can be performed, and no special address designation is required.

[0024]

According to the present invention, since a gate electrode and a plate electrode can be formed in the same layer in the same step, a memory cell can be formed using a single polycrystalline silicon layer. become. Therefore, when the logic circuits are formed on the same semiconductor substrate, each wiring can be formed in the same step.

[Brief description of the drawings]

FIG. 1 is a plan view showing a structure of a semiconductor memory device of the present invention.

FIG. 2 is a plan view showing the structure of the semiconductor memory device of the present invention.

FIG. 3 is a plan view showing a structure of a conventional semiconductor memory device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 11 Semiconductor area 2, 12 Groove 3, 13, Plate electrode 4, 21 Word line 5, 15 Bit line 6, 16, 19, 20, 22, 23 Contact hole 14 Gate electrode 17, 18 Intermediate wiring

Claims (3)

[Claims] 1. A semiconductor region formed in a strip shape on one main surface of a semiconductor substrate, and disposed on the semiconductor substrate so as to intersect with the semiconductor region, and divide the semiconductor region into first and second regions. A gate electrode, a plate electrode that is arranged in the same layer as the gate electrode and overlaps the first region, and forms a capacitor with the first region; A bit line disposed along the semiconductor region and electrically connected to the second region; and a bit line disposed on the same layer as the bit line so as to overlap the gate electrode and electrically connected to the gate electrode. An intermediate wiring, and a word line disposed on the bit line and the intermediate wiring so as to extend in a direction intersecting the bit line and electrically connected to the intermediate wiring. And the above plate An electrode is formed in the same step, and the intermediate wiring and the bit line are formed in the same step. 2. The semiconductor memory device according to claim 1, wherein the first region has a trench structure, and wherein the plate electrode is formed along a side wall and a bottom surface of the trench. 3. The device according to claim 2, wherein said gate electrode and said plate electrode are made of polycrystalline silicon.
A semiconductor memory device according to claim 1.