JPH0467643B2 - - Google Patents

Description

[Detailed Description of the Invention] (Summary) This is a clock control method in which the system clock and CPU clock are generated from the same clock source, so that when the CPU waits while trying to access a peripheral device, the CPU clock is The aim is to extend the synchronization of the system clock for as long as necessary in units of one cycle of the system clock.

[Industrial application field]

The present invention relates to a clock control method for synchronizing computer systems using clocks.

There are synchronous and asynchronous methods for exchanging data between the CPU and its peripheral devices.

The synchronous method is a method in which the CPU and its peripheral devices are controlled by the same clock;
This is a method in which the controller and its peripheral devices are controlled by completely separate clocks, and data transfer is performed using a response confirmation method.

Among these methods, the asynchronous method is useful for absorbing the difference in processing speed between the CPU and peripheral devices, but the control method tends to be very complicated, and it may cause waveform distortion in the control signal for response confirmation. There are many problems such as malfunctions. In contrast, the synchronous method has a simple control method. This synchronization method is often used to exchange data between the CPU and peripheral devices.

However, the synchronization method requires that the period of the synchronization clock of the entire system be adjusted to the slowest of the processing speeds of the CPU, the processing speeds of peripheral devices, or the data transfer speeds between the CPU and peripheral devices. For this reason, a synchronization method with a simple control method and high processing efficiency is required.

The present invention relates to a clock control method in a computer system employing such a synchronization method.

[Prior Art] A conventional clock control system has been implemented based on FIGS. 6 to 9. Figures 6 to 9 are
System configuration diagram, memory access time chart, clock generation circuit, and
This shows a time chart of the clock generation circuit.

In Figure 6, the CPU that controls the system
1' is operated by two-phase clocks ACLK and BCLK generated by a clock generation circuit 2'. this
ACLK and BCLK are out of phase with each other by 180 degrees, as shown in FIGS. 7A and 7B.

CPU 1' fetches the instructions fetched from memory between one BCLK and the next BCLK from the next ACLK.
Execute until ACLK. However, instructions executed using the address and data buses, such as memory operand access, are executed between BCLK and BCLK after the fetch of the next instruction. CPU1' is
The memory access request signal MRQ2 for instruction fetch and operand access is used as an external interface signal and is sent before the memory access cycle.
It is output to the clock generation circuit 2' outside the processor between ACLK and BCLK (Fig. 7E).

[Problem that the invention seeks to solve]

In FIG. 6 of the above-mentioned prior art, in addition to the CPU 1', there are a DMA control circuit 4' and a refresh request control circuit 5', which access memory access requests MRQ1 and MRQ, respectively.
2 to the priority control circuit 3' (Fig. 7C,
D). Now, prioritize MRQ0>MRQ1>MRQ
In order of 2. In this case, priority control circuit 3'
accepts MRQ0, MRQ1, and MRQ2 in BCLK synchronization (Figure 7 B to E), prioritizes them in the above order, and issues permission signals MACK0, MACK1, and MACK2.
(FIG. 7 G to I) and controlled memory access rights.

For example, if MRQ0 and MRQ2 are input at the same time, MACK0 is first output between BCLK and BCLK (Figure 7G), the refresh address is sent to the memory (Figure 7J), and the next BCLK~
Output MACK2 with BCLK (I in Figure 7), and
1' address and data were sent to memory (Figure 7 J, K).

However, since memory access from the CPU 1' is made to wait during the refresh period, it is necessary to generate a signal MRQ2F in which MRQ2 is held at FF in order to hold the memory request signal. Also,
Since memory access of CPU1' is performed after refreshing (Fig. 7J), while waiting
The ACLK and BCLK pair was inhibited from being input to CPU 1' (Fig. 7A, B).

In this way, memory access by the CPU 1' normally takes only one cycle between BCLK and BCLK, but if it overlaps with other accesses, it takes more than two cycles.

Therefore, in the past, there was a problem that the access time of the CPU to the system memory was long and the processing speed of the CPU was reduced.

Furthermore, conventionally, memory access cycles are
According to the memory access cycle of CPU1',
Always BCLK for refresh and DMA
BCLK, depending on the timing at which the memory access request signal rises, there may be gaps in the memory access cycle as shown in Figure 7G and K, which causes the problem that the memory is not being used effectively. It was hot.

On the other hand, in the conventional technology, between ACLK and ACLK or
The cycle between BCLK and BCLK was set to 400 ns (Fig. 7A, B). This is because it depends on the cycle time of CPU 1' for executing one instruction. Also,
This is because this time of 400 ns matched well with the cycle time when accessing dynamic RAM. For example, 16Kbit dynamic
The access time of the RAM element itself is often around 150ns. If the address transmission time from the access source is 100 ns, and the time from when data is read, checked and corrected by the ECC circuit, and transferred to the access source is 150 ns, the memory access time for the access source will be 400 ns. Approximately CPU1'
cycle time.

However, with recent technological advances, LSIs are becoming more highly integrated and faster. Especially CMOS
The technological progress has been remarkable, and the conventional technology CPU
The cycle time of the microprocessor used in 1' was halved from 400ns to 200ns. However, although the integration density of dynamic RAM has increased 16 times from 16Kbit to 256Kbit, the access time of the element itself has not become much faster, and is still often 120ns to 150ns. This is because the address decoding time increases as the degree of integration increases. Also, the processing speed of peripheral devices for transferring addresses and data to memory has not become very fast. Therefore, the memory access time from the CPU is still around 400ns.

That is, although the CPU 1' itself can run in cycles of 200 ns, the cycle has to be set to 400 ns because the memory access time is slow. Therefore, conventionally there has been a problem that the throughput of the entire system is reduced.

[Means for solving problems]

An object of the present invention is to solve the above problems and improve the throughput of the entire system by increasing the processing speed of the CPU, improving the efficiency of memory use, and increasing the processing speed of peripheral speeds.

The means to do this are the system clock and CPU.
By generating the clock and the clock from the same clock source, the synchronization of the CPU clock can be extended for as long as necessary in one cycle of the system clock when a wait occurs when the CPU attempts to access a peripheral device.

[Effect]

As mentioned above, according to the present invention, the system clock that synchronizes the entire computer system is
Generates a CPU clock that synchronizes only the CPU,
CPU clock can be controlled appropriately.

Therefore, the time required for the CPU to access the system memory is reduced, thereby improving the processing speed of the CPU and the efficiency of memory usage. Also other CPU, DMA
As the processing speed of the above functions becomes faster, the throughput of the entire system also improves.

〔Example〕

The invention will now be explained by way of example with reference to the accompanying drawings.

Figure 1 is a system configuration diagram according to the present invention, Figure 2 is a time chart of the CPU used in the present invention,
FIG. 3 is a time chart of memory access according to the present invention, FIG. 4 is a clock generation circuit according to the present invention, and FIG. 5 is a time chart of the clock generation circuit according to the present invention.

The embodiment shown in FIG. 1 includes a CPU 1, a clock generation circuit 2, a priority control circuit 3, a DMA control signal 4, a refresh request control circuit 5, a clock source 6,
It consists of a CPU-dedicated local memory 7, a CPU address/data transfer control and ECC circuit 11, a DMA address/data transfer control and ECC circuit 41, and a refresh address sending control circuit 51.

In the figure, is the CPU address bus, is the CPU data bus, is the DPA address bus, is the DMA data bus, and is the refresh address bus.

What is different from the conventional system is the operation of the entire system (the third
(Fig. 4), the provision of a CPU-dedicated local memory 7, and the operation of the clock generation circuit (Fig. 4) (Fig. 5).
Figure).

The CPU-dedicated local memory 7 described above is composed of a high-speed static RAM, and is provided so that the CPU 1 can access it at high speed in a short cycle of 200 ns. On the other hand, CPU1 and circuits 4 and 5
The common memory is accessed in a long cycle of 500ns.

That is, the CPU-dedicated local memory 7 stores instruction codes and the like that are frequently accessed by the CPU 1, and is arranged near the CPU 1 so that the CPU 1 can access them in a cycle of 200 ns.
However, due to cost considerations, the capacity is kept to the minimum necessary, and data other than instruction codes and the like are stored in the above-mentioned memory of a system that is shared with other systems, as in the past.

The operation of the embodiment shown in FIG. 1 having the above configuration will be explained below. In this embodiment, the memory access request signals MRQ0, MRQ1, and MRQ2 are sampled in synchronization with the 100 ns clock SCLK, and access is immediately permitted when they are accepted (3rd
Figure A).

For this reason, in the past, when MRQ2 and MRQ0 overlapped, the CPU memory access time used to be 800ns (Fig. 7K). In this embodiment, since access is started at the time of acceptance by MRQ1 ( _t1 in Figure 3), CPU1 can access from 400ns later (A in Figure 3), and the waiting time is only 100ns.
From the CPU's perspective, it can now be accessed in 500ns (Figure 3 M).

ACLK and BCLK are normally set according to this operation.
The clock generation circuit 2 is controlled to extend the period of 200 ns to 500 ns (Fig. 3B and C).

In other words, the local memory 7 dedicated to the CPU is now
64KB, and MRQ2 is output only when an address exceeding 64KB is output, thereby accessing the shared system memory (Figure 1).
When MRQ2 is output from CPU 1, it is also input to clock generation circuit 2, and input to the ACLK and BCLK pairs to the CPU is temporarily interrupted (Figures 1, 3, B, C, G, and 4). figure). MRQ2 is accepted, MACK2 is turned on for 400ns, and the final
The input of ACLK and BCLK, which had been interrupted after 100 ns, is canceled and re-inputted to the CPU (Fig. 1, B, C, K in Fig. 3, Fig. 4). If there is a conflict with other memory access request signals MRQ0 and MRQ1, MACK2 will turn on after waiting each time.
The period of the ACLK and BCLK pair is extended as necessary from 400 ns to 100 ns (Fig. 3, B and C).

Next, the configuration and operation of the clock generation circuit 2 according to the present invention will be explained based on FIGS. 4 and 5.

In the same figure, FF1 and FF3, FF5 to FF7
Up to D type flip-flop, FF2 and FF
4 is a JK type flip-flop.

A feature of this circuit's operation is the way the BCLK pulse width is extended when an ECC error is detected.

In other words, CPU1 is an external common memory (Figure 1)
When reading data, if there is a correctable ECC error (ECCER) in the read data, circuit 11
After correcting the data using the ECC function of
However, the correction time usually takes about 100ns. In other words, if an ECC error occurs, the memory access cycle will be 500ns. Normally, the memory cycle time is not determined by taking into account the error correction time, but the cycle time when there is no error is set as the normal memory cycle time (400ns in this case).
The conventional clock generation circuit (FIG. 8) extends the access cycle time by 100 ms only when an ECC error occurs (FIGS. 9F and K).

However, since the ECC error is detected just before the CPU 1 takes in the read data using BCLK, this time is already after the leading edge of BCLK for data taking has risen, and the timing is such that it can no longer be suppressed. (When an ECC error occurs, 11
(When there is no error, the ECCER signal from the ECC circuit rises at the timing just before BCLK falls, and is turned on for more than one cycle of the source clock.) For this reason, conventionally, ACLK,
A clock with twice the frequency of BCLK (Figure 9B,
ACLK, BCLK by dividing the frequency using
Create a clock with a pulse width of α) in B), the pulse width of BCLK is extended by one cycle of CLK1 (β in FIG. 9F).

However, this method requires the pulse width of ACLK and BCLK as the period of the source clock. In the case of the present invention, the pulse width of ACLK and BCLK is
Since it is 50 ns, applying the conventional method would require an ultra-high frequency crystal oscillator with a frequency of 20 MHz, resulting in high costs.

In order to avoid this and use a crystal oscillator with a frequency of 10 HMz, the frequency of the source clock is reduced in the present invention.
It is possible to use a pulse width that is half the pulse width of ACLK and BCLK, that is, a source clock whose pulse width is the same as that of ACLK and BCLK (Fig. 5 A, E, and F).

In the present invention, as shown in FIG. 5, when an ECC error occurs, (ECCER) = "1", JK of FF2
Set the input to “0” as in the case of ACLK and BCLK suppression.
to prevent the output of FF2 from being inverted (a in Figure 5B), and by ORing the ECC error signal ECCR itself with a signal obtained by ANDing the Q2 output of FF2 and SCLK to obtain BCLK. The pulse width is extended by the period of the system clock SCLK by 100 ns, so that 50 ns is changed to 150 ns (b in Fig. 5E).

As mentioned above, according to the present invention, even if the CPU
1 always accesses the system memory, as can be seen by comparing the time chart of the prior art shown in FIG. 7 and the time chart of the present invention shown in FIG. Both the memory access time and memory usage efficiency of CPU1 have improved (Figure 3L,
M, Figure 7 J, K). Furthermore, according to the present invention,
When CPU1 uses local memory 7, the CPU
The cycle time of CPU 1 can be determined by the power of CPU 1, regardless of the system memory access cycle, and since the system memory is not used, the memory usage efficiency of DMA is also improved. This is especially useful when sharing system memory.

〔Effect of the invention〕

According to the present invention, as described above, the access time of the CPU to the system memory is reduced, and the CPU
In addition to improving the processing speed of the processor, the efficiency of memory use is also improved, and the processing speed of other processors, DMA, etc. is also increased, which is effective in improving the throughput of the entire system.

[Brief explanation of the drawing]

Figure 1 is a system configuration diagram according to the present invention, Figure 2 is a time chart of the CPU used in the present invention,
3 is a time chart of memory access according to the present invention, FIG. 4 is a clock generation circuit according to the present invention, FIG. 5 is a time chart of a clock generation circuit according to the present invention, and FIG. 6 is a system configuration diagram according to the prior art. FIG. 7 is a time chart of a memory access according to the prior art, FIG. 8 is a clock generation circuit according to the prior art, and FIG. 9 is a time chart of a clock generation circuit according to the prior art. DESCRIPTION OF SYMBOLS 1...CPU, 2...Clock generation circuit, 3...Priority control circuit, 4...DMA control circuit, 5...Refresh request control circuit, 6...Clock source, 7...
Local memory dedicated to the CPU.

Claims (1)

[Claims] 1. A system clock for synchronizing the entire computer system in a clock control method that synchronizes a computer system consisting of a CPU and its peripheral devices with a clock generated by a clock generation circuit. Synchronize only the central processing unit and the central processing unit.
When the system clock is generated from the same clock source as the CPU clock, the system clock is always kept at a constant cycle, and there is no wait when the CPU accesses a peripheral device, the CPU clock is generated from the system clock's natural clock source. In the case of an access that is held at a constant period several times higher than that and causes a wait, a specific signal indicating that a wait occurs is input to the clock generation circuit, and the clock generation circuit generates a clock inhibit signal using the specific signal. When turned on, it starts suppressing the generation of the CPU clock, inputs the specific signal to the priority control circuit that controls contention for access to peripheral devices, and outputs a response signal of the priority control circuit to the specific signal. By inputting the signal to the clock generation circuit, the clock suppression signal is turned off and the CPU clock generation suppression is canceled.
A clock control method characterized in that by regenerating the CPU clock, the CPU clock is extended in units of one period of the system clock only during the access cycle. 2 When extending the period of the CPU clock mentioned above,
If a wait is detected before the leading edge of the next clock pulse rises, the clock inhibit signal is turned on to keep the pulse width constant and prevent the generation of the next clock pulse in units of one system clock cycle. If a wait is detected after the leading edge of the next clock pulse has risen, the signal indicating the wait is ORed with the clock pulse to suppress the generation of the trailing edge of the clock pulse. At the same time, the signal indicating the wait is sent to the clock generator circuit.
By inputting this as the flip-flop reversal inhibiting condition that sets the synchronization of the CPU clock, the clock pulse width is extended in units of one system clock period according to the length of the signal indicating the wait, and only the trailing edge of the clock pulse is delayed. A clock control system according to claim 1, characterized in that: