JPH0467399A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To perform high-speed memory cell test without controlled by writing and reading timing by providing input terminal and input buffer, or output terminal and output buffer in a latch circuit string and directly inputting data from outside. CONSTITUTION:Input terminal 30 and input buffer 31 to which the data can be directly inputted from the outside or output terminal 33 and output buffer 32 from which the data can be outputted to the outside, are provided with a latch circuit group 24 equipped with a shift function connecting to the bit line. The data is directly inputted from the outside to the latch circuit string equipped with the shift function connecting to the bit line. Thus, the high-speed memory cell test can be performed without controlled by the timing such as a conventional DRAM, and the efficiency can be realized at the time of the test of the memory cell.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor memory device. [Prior Art] Fig. 3 shows a dynamic semiconductor memory device with a conventional line mode test function. FIG. 2 is a circuit diagram showing a configuration near a memory cell. The in-mode test shown here is
The test data inputted from the outside is stored once in the lunch, and the test data is used to test all the memory cells connected to the word line of the memory cells in row 2 at once.

The above line mode test [, 1989, IEEE
international 5solid-5tate
Diges of C1rcuitsConference
to of Technical Paper, p2
44 to p245, 9% selected, connected to the word line, and read out from the memory cells. The circuit diagram showing the configuration near the memory cell array in FIG. 3, and FIG. 5 are shown in FIG. 4. FIG. 2 is a circuit diagram showing a configuration near a latch circuit and a comparison circuit shown in FIG. In the figure, C1) is a word line, (2) is a bit line, and (3) is a word line.
) i4 bit line pair, (4) t11! I10 line, (5)
is Ilo, line, (6) is latch circuit, +73° (8),
(1G, 02.Qi, Q6~1211. million d
Nf Ya*lt 5y register, 19) ri sense amplifier, a
υ is a comparison circuit, α4°1119riF channel transistor, ■0ro, seagull is a switch, c12 is an input/output line, square is a detection line, and (2) is a memory cell.

In FIG. 3, memory cell c18 exists at the intersection of bit line +21 and word line (1). Human output line ■ and bit @
Between (2), there is a switch 0. and a switch, and a latch circuit (6
) and a comparison circuit oI) are installed. Further, the comparison result of the comparison circuit O is outputted to the detection line.

Next, the operation of the lie/mode test will be described with reference to FIG.

First, write the test data to the memory cell! I will explain about inclusion.

Testing of memory cells of a dynamic semiconductor memory device is basically performed by comparing data stored in the memory cells with an expected value. To the external z, 6 inputs t test data, the signal Yl - Yl '' from the column decoder through the 110 line (4) and Ilo @ (5)
Yi+2, . . . are fabricated to form a transfer gate (8), which is selected to turn on the N-channel transistor (8) and transmitted to the latch nodes NA, NB, where the data is transferred to the latch circuit (6). - degrees are accumulated.

The data accumulated in the launch circuit (6).

This is the expected value during testing. Also, at this time, the signal TRri
, is at the "L" level, and the N-channel transistor (7) ri forming the transfer gate t is in the off state, so data is not transmitted to the memory cell c!8@.

During the process of accumulating data in the latch circuit (6), a column decoder (not shown) selects the latch node NA.
, NBt - are further repeated in sequence.

In this way, test data is accumulated in the latch circuits (6) connected to all bit line pairs (3).

Next, I decided to raise the signal TR to "H" level.
Turn on the N-channel transistor (7) forming the transfer gate, and raise any word ii (11) selected by the lower decoder and word driver (not shown) among all the word lines f1 to the H'' level. Any selected word line (1)
The data accumulated in the latch circuit (6) is simultaneously written to all memory cells (to) connected to the latch circuit (6).

The process of writing data into the latch circuit (6) F memory cell is repeated by sequentially changing the selected word line t1) in the lower decoder and word driver (not shown). In this way, test data is written into the memory cells (to) connected to all bit line pairs (3).

Next, a description will be given of reading out the test data stored in the memory cell and comparing it with the expected value.

As shown in the figure, the lower decoder and word driver select the desired word line (1) to raise it to the afle level. The test data stored in the memory cell (to) connected to the bit line pair (3) is read out. This data is sent to the sense amplifier (
9) is amplified.

Next, the signal TR is set to ``L level, and the signal LTE is set to #H level.
When the data is raised to the level, the N-channel transistor forming the transfer gate turns on. The data stored in the comparator circuit 0η and the latch circuit (6) is transmitted via the nodes NA and NB.

In the comparison circuit (b), the data read out from the memory cell F is compared with the t data stored in the latch circuit (6), and the comparison result is detected by the LTS.

In Figure 5, the test data input from the outside is
Ilom(4) tl1041(5)tjll L TE:F LAA TE:y-Column decode signal Yid(), which is output once to DA, turns on the N-channel transistor (8) forming the transfer gate. In particular, EX1 is selected and transmitted to the latch node NA%NB. And a latch circuit (
6).

Also, during the test, when the signal TiL is raised to the H~ level while the signal TiL remains at the L'' level, the N-channel transistor (11) that forms the transfer gate is turned on, so the memory cell -19 is read out. The data is provided on each n focus line pair (3) and transmitted to the comparator circuit 0υ. For example, / -)'N A = H
If the node NB is at #L~level, the N-channel transistor 0ari is on.

N-channel transistor Qg is in an off state.

Further, the potential of the node NC is determined by inputting the signal LTRft and N
L is applied to turn on the channel transistor cln.
This is set in advance to 'L level.

The error detection line LTS is set to H level in advance.

When correct data is read from the memory cell (to), the node NE is at the "H# level" and the node NF is at the "L" level. , the node NC remains at the 1L level, and the N-channel transistor remains in the OFF state, and the node NDri#H# of the error detection line LTS remains at the level.

When incorrect data is read out from the memory cell 17s, the node NE is at the "L" level and the node NFij is at the "H" level, so that the data transmitted through the N-channel transistor α1 is different from the node NC. ['H'' level 5. To ensure that the N-channel transistor is turned on, the node N Dri of the error detection line LTS
'Descend to L-level.

This makes it possible to detect errors in memory cells.

Although FIG. 115 has been explained for one bit line bear (3), the above comparison operation is performed for all bit line bears (3) at once, so even one bit line bear may contain incorrect data from the memory cell ca. When read, the node ND of the error detection line LTS drops to the #L" level.

For example, a case will now be described in which a checker board pattern such as the one shown in FIG. 8 used for memory cell testing of a semiconductor memory device is written into a memory cell array. First, data of t, 0.1.0, . . . is written to the external column of latch circuits (6) shown in FIG. Writing to the column of latch circuit (6) is completed.
After that, the word lines (1) whose addresses are odd numbers are activated while incrementing the addresses one after another, and the data of the latch circuit (6) is transferred all at once to the memory cells (to) connected to the t-word (th). Write.

Next, 0, 1.0.1. After writing is completed to the column of 0 latch circuits (6) in which data is written, the word lines (1) whose addresses are even numbers are activated by sequentially incrementing the addresses. The data of the latch circuit (6) is written all at once to the memory cells (to) connected to the t word line (1).

Nijimemory cell (2) is used to perform the above-mentioned complicated operations.
6 is a schematic circuit diagram showing the configuration near the improved conventional memory cell array, and a circuit diagram of the circuit shown in FIG. In figure 0, C1) ~on, o~ro, seagull,
ω, (to) is equivalent to that shown in the conventional example shown in FIG. 3 and FIG. 4. @ is a four-way latch sequence. The circuit shown in Figure 6 and Figure 7 differs from the conventional examples shown in Figures 3 and 1Es in that the data launch circuit array (to) is bidirectional between each latch circuit (6). It has the function of shifting data.

Connect to any bit line (2) by raising an arbitrary column address through the data input/output I10 line [4] and I10 line (5) and turning on the N-channel transistor (8) corresponding to the column address. Latch concave M
(6) Ic is transmitted. I worked on changing the column address to launch], all bits! ! Writing of data to the latch circuit (6) connected to +21 is completed.

Thereafter, data is written from the latch circuit (6) to the memory cell array in the same manner as in the conventional example shown in FIG.

The latch circuit (6) in the circuit of FIG. 6 receives the signal ψl.

By inputting φ2 at an appropriate timing, the data at the nodes NA and NB of the latch circuit (6) corresponding to the one column address Yi can be shifted to the column address with the larger address. Also.

I decided to input the signals φ3%φ4 at an appropriate timing!
The data in the latch circuit (6) can be shifted by 7 feet to the smallest 5 column address.

At this time, when writing the checker board pattern shown in FIG. 8 to the memory cell array, in the conventional example shown in FIG. After that, it is necessary to rewrite the data in the latch circuit (6) before starting writing to the even numbered columns.

However, in the circuit diagrams shown in FIGS. 6 and 7,
When the word line address is incremented, the signal ψ1%ψ2 or 72. is the signal φ3. By inputting φ4, the data in the latch circuit (6) can be shifted, and the data can be used to write to the memory cell array. This operation will be explained in detail.

The 1, 0° direct, 0. Activate TR with the data of...

By raising word line (1) corresponding to the lowest address of word 11 (1), 1.0, 1 . O.

The data of the latch circuit (6) is inputted to the bit line address by making TRY inactive in the 0th order where data is written and inputting the clocks of the signal ψ2 and the signal φl alternately once each in the next state. 0 then activates TR and word iyj! By raising the word line corresponding to an address l greater than the lowest address of ill, all memory cells (to) connected to the word line (1) are 0.1. O, 1,...
... data is written. Next, by inputting the clock signals ψ4 and ψ3 alternately once with %TR inactive, the data in the Niji latch circuit (6) is shifted to 0, which is 1 smaller than the bit line address.
After this, by repeating the above explanation, it is possible to write the checker board pattern shown in FIG. Even when performing a batch parallel test for each memory cell (branch) connected to the word line (1), the test can be performed without rewriting the data stored in the launch circuit (6).

[Problem that the invention seeks to solve]

A conventional semiconductor memory device is configured as described above.
Therefore, in a parallel test of memory cells, writing information to the latch circuit requires the same operation as writing to a normal memory cell, which limits efficiency during testing.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor memory device that can improve efficiency when testing memory cells.

[Means for Solving the Problems] A semiconductor memory device according to the present invention has an input terminal and an input buffer that can directly input data from the outside to a group of latch circuits having a shift function connected to bits, or input data directly to the outside. It is equipped with an output buffer and an output buffer that can output .

[Effect]

The semiconductor memory device of the present invention is designed to directly input externally processed data to a latch circuit array with a shift function connected to a bit line, and is a high-speed memory device that is not controlled by the timing of conventional DRAMs. Cell test is possible.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram showing the periphery of the memory cell array of a dynamic semiconductor memory device and a signal system in parallel testing. it), t2
+, up to (to), and ■ are the same as those shown in the conventional examples shown in FIGS. 3 to 7, so their explanations will be omitted. ■ is the test data input terminal; ) is the test control terminal, (to) is CA S @+-
(to) is the address terminal, - is the mouse As buffer, and ) is W
E buffer, - is the CAS buffer, - is the address buffer, +44ri memory cell array, (4I9 is the lower decoder group, - Hasens amplifier group, @ is the comparison four-way group, and K is the column decoder group. The other signal systems that are not included are the same as those of a normal dynamic semiconductor memory device.

Memory cell array - Peripheral * or Fig. 6 Work No. 7 WJ
0 where the above TEX
E is a lower address strobe, CAS is a column address strobe, and WEd is converted into a write enable signal and becomes a signal for internal control of the semiconductor memory device. In addition, the address signal group is applied externally through the address terminal and converted into a detailed signal in the address buffer.The column address generated here is input to the column decoder group, and the lower address is input to the lower decoder group. 0 and each bit line pair of the memory cell array is connected to a sense amplifier group and a comparison circuit group. − each n comparison circuit $? = Each latch circuit in the latch circuit array ＼ is connected to the latch circuit array c! 4 has the function of shifting data as in the conventional example shown in FIGS. 111
Data can be directly written to the external L of the semiconductor memory device through the output buffer (to) and the data output terminal 8I for outputting data, and data can be output to the outside of the semiconductor memory device.

When performing a memory cell test (line mode test of a semiconductor memory device) in line t-1j, the external fabrication test control 774
child @, RASgll child m, CASgIA child al>z bi-
When a certain signal is input to the other terminal of t, which is the timing to start executing a memory cell test using a line mode test, the semiconductor memory device is controlled by the signal manually input from an external tester L to perform a line mode test. Start 0 Start line mode test In the semiconductor memory device, control by signals from the column decoder group @ by column address input is no longer transmitted to the memory cell array. Column system control is based on the signal input from the external tester and is generated by the Niji test system control signal generation circuit, which has a function of shifting the ratio signal and inputs the signal to the ratio latch circuit row (to). In Figure 2, when the line mode test is executed, the output of the column decoder (not shown) is always at L'' level, so the switch I2D between the data input/output Iw and the pin (12) is always OFF and not connected. In this state, data is input to the external F test data input terminal ω, the input buffer 13υ is used to control the nine-touch circuit array @t@ with a shift function, and the data is input to the false column address with the larger address. By sequentially inputting arbitrary data while shifting, writing to one latch circuit string (up to) is completed.After this, connect the switch I23t' to the latch circuit string □□□ and write to any word line (1). The data in the latch circuit array can be loaded all at once into the memory cells connected to any word line (1). Write data to the memory cell array after writing.

[See Figure 6'J? for comparison of data readout during L line mode test execution. The construction is similar to the conventional example shown in FIG.

The output vane 7A and the data output cap in Figures 1 and 2 are used to test the latch circuit array (to) in the above embodiment, and test data is input to the launch circuit array (2). 19.The latch circuit array (to) is tested by outputting the data output terminal C (3-digit test data) through the output buffer s2.In this case, the launch circuit array (to) is Since it is possible to transfer data in both directions, it is preferable to add the test data input terminal ω and the data output terminal trQf: to the input cover sofa example, and the output cover sofa (to) and data output terminal @ can also be omitted. .

Although the latch circuit array (to) in the above embodiment can transfer data in both directions, it is also possible to limit the transfer direction to one direction.

〔Effect of the invention〕

According to the above method, if this invention is implemented, the latch circuit array with a shift function connected to the bit line can be used as an input terminal that can input data directly from the outside, or as an input buffer, or can output data directly to the outside. Since the output terminal is equipped with an output buffer, it is possible to directly input external data to a latch circuit array with a shift function that connects to the bit line.
This has the advantage that it is possible to obtain a semiconductor memory device that is not controlled by write and read timings like conventional DRAMs and is capable of high-speed memory cell testing.

[Brief explanation of the drawing]

Figure 1 shows an embodiment of the semiconductor memory device according to the present invention.
Block diagram showing the periphery of the memory cell array of a dynamic semiconductor memory device and the signal system in parallel testing, Part 2
The figure is a circuit diagram showing the configuration near the memory cell array of the device shown in the exploded view, FIG. 3 is a circuit diagram showing the configuration near the memory cell array of a conventional dynamic semiconductor memory device, and FIG. 4 is the memory cell array in FIG. 3. Circuit diagram showing nearby configuration, #! Figure 5 is a circuit diagram showing the configuration near the latch circuit and comparison circuit shown in Figure 4. Figure 6 is a schematic circuit diagram showing the configuration around the memory cell array according to an improved conventional example. The circuit diagram of the circuit, FIG. 8, is a diagram showing a checker board pattern used for testing semiconductor memory devices. In the figure, C1) is a word line, (2) is a bit line,
. , the gull is the input/output line, @ is the latch circuit row, @ is the detection line,
csrz memory cell, ω is a test data input terminal. ((I is a manual buffer, @ is an output sofa, (To) is a data output terminal, @ is a test system control signal generation circuit, (A)
is the RAS terminal, (to) is the WE terminal, - is the test control terminal, (to) is the CAS control terminal, CII is the address terminal, and is the AS buffer % cheat υriWE buffer &&ga is the CAS
buffer. - is an address buffer, - is a memory cell array, - is a lower decoder group, - is a sense amplifier group, Ia) is a comparison circuit group, and @ is a column decoder group. In addition, the same symbols in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A configuration including a plurality of word lines, a plurality of bit line pairs, and a plurality of memory cells, and each of the bit line pairs or the plurality of bit line pairs includes a latch circuit capable of storing data other than a sense amplifier. In a semiconductor memory device, the latch circuit is capable of transferring data between adjacent latch circuits, wherein the latch circuit connected to the bit line directly transfers data from an input terminal from outside the semiconductor memory device. A semiconductor memory device characterized in that the latch circuit connected to the bit line can directly transmit data from an output terminal to the outside of the semiconductor memory device, or that both the former and the latter are possible.