JPH04205879A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To easily write certain data and another data having a fixed relation with the data by shifting the data written by means of a latch data shifting means in the direction of a word line and writing the shifted data in a memory cell connected with a word line which is different from the above-mentioned word line. CONSTITUTION:A data latch circuits row 24 is formed by connecting latch circuits 6 with each other in the direction of a word line WL. The data written by means of a data writing means are written in a memory cell MC connected with a desired word line WL through a data latching means. The data are then shifted in the direction of the word line WL and written in another memory cell connected with a word line which is different from the above-mentioned word line. Accordingly, the original data and their shifted data are not written separately, but written in a memory cell array. Therefore, the original data and the data having a fixed relation with the original data can be easily written.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which certain data and data having a certain relationship with the data can be easily written.

[Prior Art] FIG. 5 is a functional block diagram showing a configuration near a memory cell of a dynamic semiconductor memory device with a conventional line mode test function. The line mode test shown here stores test data input from the outside in a latch circuit, and then uses that data to test the memory cells on all memory cells connected to the word line. It is something to do. Traditional line mode testing is for example rA 60ns 3.3V 16MbD
RAMJ 1989, IEEE International
tional 5solid-StateCircui
Digest of ts Conference
Technical Papers, p244~
It is reported in 245 that a plurality or all pieces of information read from memory cells connected to a selected word line are tested at once.

Referring to FIG. 5, memory cell MC exists at the intersection of bit line BL and word line WL. The input/output line 22 and the bit line BL are separated by a switch 21 and a switch 23. A latch circuit 6 and a comparison circuit 11 are provided in the separated portion. Further, a switch 25 is provided between the comparison circuit 11 and the latch circuit 6. The comparison result of the comparison circuit 11 is output to the detection line 26. Note that the sense amplifier is omitted in this figure.

FIG. 6 includes a bit line pair BL and a pair of input/output lines 22 which are abbreviated in the functional block diagram of FIG. 5, and also includes a latch circuit 6 and a comparison circuit 1 according to the actual wiring configuration.
1 shows the connection state of No. 1. FIG. 7 is a circuit diagram expressing the connections around the latch circuit 6 and comparison circuit 11 at a transistor level.

The operation of the line mode test will be described below with reference to FIG. First, writing of test data to a memory cell to an IC will be explained.

Testing of memory cells to ICs of a dynamic semiconductor memory device is basically performed by comparing information stored in the memory cells to ICs with expected values. In the case of FIG. 6, the test data input from the outside is transmitted through the I10 line 4 and the I/'O line 5 (corresponding to the input/output line 22 in FIG. 5) to the signals Yi, Yi÷÷ from the column decoder. l, Yi+2.
By turning on the N-channel transistor 8 forming the transfer gate, the signal is transmitted to the selected latch nodes NA and NB. This transmitted information is once stored in the latch circuit 6. The information once stored in the latch circuit 6 becomes the expected value during testing.

Further, at this time, the signal TR is at "L" level, and the N-channel transistor 7 forming the transfer gate is
Since it is in the off state, information is not transmitted to the memory cell side.

In the process of accumulating information in the latch circuit 6, a column decoder (not shown) selects latch nodes NA and NB.
is changed sequentially and repeated. In this way, test data is accumulated in the latch circuit 6 connected to all bit line pairs.

Next, by raising the signal TR to the t+Hn level, the N-channel transistor 7 forming the transfer gate is turned on, and any word selected by the row recorder and word driver (not shown) among all the word lines is activated. The line is raised to the “H” level. As a result, the information stored in the latch circuit 6 is simultaneously written to all memory cells MC connected to the selected arbitrary word line.

The process of writing information from the latch circuit 6 to the memory cell MC is performed by a row recorder and a word driver (not shown).
The process is repeated by changing the selected word line in order. In this way, test data is written into memory cells MC connected to all bit line pairs.

Next, a description will be given of reading the test data stored in the memory cell MC and comparing it with the expected value.

By raising an arbitrary word line selected by a row recorder and a word driver (not shown) to the "H" level, the data accumulated in the latch circuit 6 for all memory cells connected to the selected arbitrary word line is Information is written all at once.

The process of writing information from the latch circuit 6 to the memory cell MC is performed by a row recorder and a word driver (not shown).
This process is repeated by sequentially changing the word line to be selected. In this way, test data is written into memory cells MC connected to all bit line pairs.

Next, a description will be given of reading the test data stored in the memory cell MC and comparing it with the expected value.

Low record not shown? By raising an arbitrary word line selected by the word driver to the "H" level, all memory cells MC connected to the selected arbitrary word line are connected to the bit line pair connected to the memory cell MC. Test data stored in cell MC is read out. This information is amplified by the sense amplifier 9.

Next, the signal TR remains at the “L” level and the signal LTE is set to the “H” level.
When raised to the ``level'', the N-channel transistor 10 forming the transfer gate is turned on. Therefore, the information read from the memory cell MC is transmitted to the comparison circuit 11 provided for each human line pair. The information stored in the latch circuit 6 is transmitted to the comparison circuit 11 via the node NA1 and the node NB.

In the comparison circuit 11, the information read from the memory cell MC and the information stored in the latch circuit 6 are compared, and the comparison result is detected as a signal LTS.

Column decode signal Y output by column decoder
i turns on the N-channel transistor 8 forming the transfer gate. Latch node NA where test data input from the outside is selected through I10 line 4 and I10 line 5.

It is transmitted to NB. and N-channel transistor 12
．． 13 and P channel transistors 14 and 15.

Further, during the test, the signal LTE is raised to the "H" level while the signal TR remains at the "L" level. Then, since the N-channel transistor 10 forming the transfer gate is turned on, the information read from the memory cell MC is transmitted to the comparison circuit 11 provided for each bit line pair. For example, if the node NG is at the "H" level and the node NH is at the "L" level, the N-channel transistor 33 is in the on state;
4 is in the off state. Further, the potential of the note NC is set to the "L" level in advance by inputting the signal LTR and turning on the N-channel transistor 35, and the error detection line LTS is set to the "H" level in advance. .

When correct data is read from memory cell MC, node NE is at "H" level and node NF is at "L" level. Due to the information transmitted through the transfer gate 10, the node NC remains at the "L" level, the N-channel transistor 36 is turned off, and the node ND of the error detection line LTS remains at the "H" level.

If incorrect data is read by memory cell MC,
Node NE is at "L" level and node NF is at "H" level. Due to the information transmitted through the transfer gate 10, the node NC becomes "H" level,
Since the N-channel transistor 36 is turned on, the node ND of the error detection line LTS falls to the "L" level. Thereby, errors in memory cells MC can be detected.

In FIG. 7, one bit line pair was explained, but
The above comparison operation is performed on all bit line pairs at once, so if even one memory cell reads incorrect data, the node ND of the error detection line LTS goes low.
descend to the level.

For example, a case will be described in which a checker board pattern as shown in FIG. 8 used for memory cell testing of a semiconductor memory device is written into a memory cell array. First, 1.
Data of 0.1.0, . . . is written. After writing to the column of the latch circuit 6 is completed, word lines with odd addresses are activated while sequentially incrementing the addresses, and memory cells MC connected to the activated word lines are activated.
The data of the latch circuit 6 is written all at once.

Next, from the outside, 0 is applied to the row of latch circuits 6 shown in FIG.
．． 1. Write the data of 0.1, . Latch circuit 6
After writing to the column is completed, the word lines with addresses or even numbers are activated while incrementing the address sequentially, and the data in the latch circuit 6 is transferred all at once to the memory cells MC connected to the activated word lines. Write.

By performing the above operations, a checker board pattern as shown in FIG. 8 can be written into the memory cell array.

[Problem to be Solved by the Invention] Since the conventional semiconductor memory device is configured as described above, for example, when writing a checker-hold pattern as shown in FIG. However, it was necessary to rewrite the data in the latch circuits for even and odd columns.

This invention was made to solve the above-mentioned problems, and provides a semiconductor memory device in which certain data and data having a certain relationship with that data, such as a checker board pattern, can be easily written. The purpose is to provide

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes a memory including a plurality of memory cells provided at the intersections of a plurality of bit line pairs and a plurality of word lines that intersect with the plurality of bit line pairs. an array of cells, a data latch means for latching data connected to each bit line pair, a data write means for writing data to the data latch means, and a data write means for latching the data written to the latch means. data writing means for writing to a memory cell located at the intersection of a bit line pair corresponding to the word line and a selected word line of the plurality of word lines; latch data shifting means for shifting in the direction.

[Operations] In the semiconductor memory device according to the present invention, data written externally by the data writing means is written into the memory cell connected to a desired word line through the data latch means. Next, the data written by the latch data shift means is shifted in the word line direction, and the shifted data is written into a memory cell connected to another word line different from the previous word line. Therefore, the original data and the shifted data are written into the memory cell array without being written separately.

[Example] Examples of the present invention will be described below.

FIG. 1 is a functional block diagram for explaining the invention in detail. Referring to FIG. 1, in the semiconductor memory device according to the present invention, latch circuits 6 for latching externally applied data are interconnected in the direction of word lines, and
They form a column 24 of data latch circuits. Data can be shifted bidirectionally between the respective latch circuits forming the column 24 of data latch circuits.

FIG. 2 is a diagram showing an application example of the data latch circuit shown in FIG. 1, and corresponds to FIG. 5 described in the related art. FIG. 3 is a circuit diagram showing details of FIG. 2. Hereinafter, a semiconductor memory device to which the present invention is applied will be explained with reference to FIG.

An arbitrary column address is raised through the data input/output lines I10 line and I10 line, and transfer gate 8 is turned off.
By setting the bit line to N, data is transmitted to a latch circuit connected to an arbitrary bit line. By changing the column address to be raised, writing of data to the latch circuit 6 connected to all bit lines is completed. Thereafter, data is written from the latch circuit 6 to the memory cell array in the same manner as in the conventional example.

The latch circuit 6 according to the present invention inputs the signals φ1 and φ2 at appropriate timing, so that each node NAS of the latch circuit 6 corresponding to the column address Yi is
The data in NB is shifted to the side with a larger column address. Furthermore, by inputting signals φ3 and φ4 at appropriate timings, data in the latch circuit is shifted to the side with a smaller column address.

Next, the details of this content will be explained. Figure 4 shows signals φ1, φ2, φ3 and φ4 when data is shifted.
This is a timing chart. When data is shifted from column address Yi to Yi+l, the clock shown in (1) of FIG. 4 is used. As shown in FIG. 4(1), in this case, the signals φ3 and φ4 are fixed at "L".

Referring to FIG. 4 (1), the signal φ is equal to the number of transfer steps.
2 and φ1 pulses are input. In this figure, data at column address Yi is transferred to Y1+1 at the first rising edge of signals φ2 and φ1, and from column address Yi+l to Yi−t− at the next rising edge.
Data is transferred to j.

Figure 4 (2) shows data transfer at column address Yi+2.
3 is a diagram showing a clock waveform when data is transferred in the direction from column address Yi+1. FIG. In this case, signals φ1 and φ2 are fixed at "L". In this case as well, the pulses of signals φ3 and φ4 are applied as many times as the number of transfer steps S, and at the rising edge of the first signal, data is transferred from column address Yl+2 to yi+1, and at the rising edge of the next signal, data is further transferred to column address Yi. be done.

At this time, when writing the checker board pattern shown in FIG. 8 to the memory cell array, in the conventional example, the data is different between the odd and even columns of the word line address, so writing is completed in the odd column. It was necessary to rewrite the data in the latch circuit before starting writing to the rear even-numbered columns. However, in the circuit diagram shown in FIG. 3, as the word line address is incremented, the signals φ1 and φ2 or the signals φ3 and φ4 are input, the data in the latch circuit 6 is shifted, and the data is used to transfer the data to the memory cell array. can be written. This operation will be explained in detail. 1, Oll, written externally into the column of the latch circuit 6
Data of 0, . Data of .1.0, . . . is written. Next, with signal TR inactive, signals φ2 and φ
By alternately inputting clocks of 1 once at a time, the data in the latch circuit 6 is shifted to the bit line address larger by 1. After that, by activating the signal TR and raising the word line corresponding to the address that is one higher than the lowest address of the word line, the memory cells MC connected to the word line are simultaneously 0.1.0.1 ,...
data is written. Next, by alternately inputting the clocks of the signals φ4 and φ3 one by one with the signal TR inactive, the data in the latch circuit 6 is shifted to the bit line address smaller by 1. Thereafter, by repeating the above explanation, the checker board pattern shown in FIG. 8 can be written.

More specifically, it is as follows. For example, when transferring data of column address Yi to Y1+1, signal φ
When the second clock is input, the data of Yi is transferred from the latch of Yi to the latch between Yi and Yi+l. When the latch data of Yi is “H”, the latch data between Yi and Yi is inverted by the inverter, so it becomes “H”.
Next, when the clock signal φ1 is input, the latch data between Yi and Y1+1 is transferred to the latch of Yi, but this is also inverted by the inverter and becomes "L" again. In this way, the latch data of column address Yi is transferred to the latch of Yi+l as the same data.

Therefore, the latch circuit 6 of Yi is set to “H” from the outside, and Y
When "L" is written to the i+l latch circuit, "H" is written to the Yi+2 latch circuit, the above data is first written to the memory cells connected to the even-numbered word lines. Next, when the clocks of signals φ2 and φ1 are input, the “L” of the latch of Yi-1 is input to the latch circuit of Yi.
+l latch is “H”, Yl+2 latch is “L”...
By writing this data into the memory cells connected to the odd-numbered word lines, the checker board pattern is completed.

In the above explanation, writing of data to memory cells has been explained, and even when performing a batch parallel test for each memory cell connected to a word line, the test can be performed without rewriting the data accumulated in the latch circuit. can be executed.

Further, in the above description, the CHI/Y card board pattern shown in FIG. 8 has been described, but the present invention can also be applied to other patterns. Further, in the above embodiment, the row of latch circuits is a bidirectional shift resist, but it may be shift resist only in one direction.

[Effects of the Invention] As described above, according to the semiconductor memory device according to the present invention,
Data written from outside by the data writing means is written into the memory cell connected to a desired word line through the data latch means. Next, data is shifted in the word line direction by the latch shift means, and the shifted data is written into a memory cell connected to another word line different from the previous word line. Therefore, the original data and the shifted data are written into the memory cell array without being written separately. As a result, a semiconductor memory device can be provided in which data having a certain relationship with the original data can be easily written.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram showing essential parts of a semiconductor memory device according to the present invention, and FIG. 2 is a functional block diagram showing an embodiment used in the semiconductor memory device according to the present invention.
FIG. 3 is a circuit diagram showing the main part of the functional block diagram shown in FIG. 2, FIG. 4 is a timing chart of clock signals for shifting data, and FIG. 5 is a diagram of a conventional semiconductor memory device. 6 is a wiring diagram showing details of FIG. 5, FIG. 7 is a circuit diagram showing details of FIG. 6, and FIG. 8 is a diagram showing a checker board pattern. It is. MC is a memory cell, BL bit line, WL is a word line, S
A is the sense amplifier, 4 is the I10 line, 5 is the I/'O line, 6
1 is a latch circuit, and 11 is a comparison circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A memory cell array including a plurality of memory cells provided at the intersections of a plurality of bit line pairs and a plurality of word lines intersecting the plurality of bit line pairs, and data latch means for latching data; data writing means for writing data to the data latch means; latch data writing means for writing into the memory cell located at the intersection of the bit line pair and a word line selected from the plurality of word lines; latch data shifting means for shifting the data in the direction of the word line.