JPH0467278B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a sense circuit, and particularly to a sense circuit used in a semiconductor memory.

[Technical background of the invention]

BACKGROUND ART The capacity and speed of semiconductor memories have been increasing year by year, and various methods have been devised. As the capacity of semiconductor memories increases, delays in memory cell sections due to parasitic capacitance of word lines, bit lines, and sense lines have become a serious problem. To improve this, it is common practice to reduce the logic amplitude of the bit lines and sense lines. However, in order to reduce the logic amplitude, a highly sensitive sense circuit is required, and a differential amplifier is generally used as such a sense circuit.

FIG. 1 shows a circuit diagram of a conventional EPROM sense circuit. Reference numeral 20 indicates a 1-bit memory cell, and although several cells are actually connected in parallel, only one bit is shown here for convenience of explanation. 30 is a dummy cell for reference. Memory cell transistor 1 is a floating gate type n-channel
It is a MOS transistor and has a bit line BL and a word line WL. This transistor 1 is turned on when a voltage is applied to the gate when no data is written, and when data is written, the threshold value becomes high and the transistor 1 is turned off or the amount of current flowing is reduced. becomes smaller. The dummy transistor 13 of the dummy cell 30 is the same transistor as the memory cell transistor 1, and
Data is always in an unwritten state. Here, the logic in the state where no data is written is expressed as "1", and the logic in the state in which data is written is expressed as "0". Transistor 2 is a transfer transistor switched by column decode signal CD, and transistor 12 is a corresponding dummy transistor. Transistor 3 is a transfer transistor whose gate is clamped to constant potential _VBB , and serves to prevent erroneous writing to memory cell 20 due to application of a high potential to the bit line. Transistor 11 is a dummy transistor corresponding to this. N-channel transistors are used for transistors 2, 3, 11, and 12. p channel
Transistors 4 and 10, which are MOS transistors, are load transistors for memory cell 20 and dummy cell 30, respectively, and transconductance gm of transistor 10 is larger than transconductance gm of transistor 4. Reference numeral 40 denotes a conventionally well-known current mirror type differential amplifier circuit, which is composed of n-channel MOS transistors 5, 6, and 7 and p-channel MOS transistors 8 and 9.

Next, the operation of the above circuit will be explained. Second
The figure is a graph showing the characteristics of memory cell transistor 1 and load transistors 4 and 10 when power supply voltage V _CC =5V. The horizontal axis is the potential of the sense axis SL
V _Sio or the potential V _R of the reference line RL is shown, and the vertical axis shows the current flowing through each transistor. The solid line shows the characteristics of memory cell transistor 1, the solid line marked "1" shows the characteristics when no data is written, and the solid line marked "0" shows the properties when data is written. represents the characteristics of Further, the broken line shows the characteristics of the load transistor 4, and the dashed line shows the characteristics of the load transistor 10. Since the mutual conductance gm of both load transistors is different, the two characteristics do not match. The characteristics of this load transistor are that V _Sio is
When the voltage decreases below V _CC −V _TH , the power supply increases. Here, V _TH is the threshold voltage.

Since the current flowing through the load transistor 4 is equal to the current flowing through the memory cell transistor 1,
The value of V _Sio is the voltage corresponding to the abscissa of the intersection A of the solid line “1” and the broken line when the memory cell is “1”.
V _A , and when the memory cell is “0”, the voltage corresponds to the abscissa of the intersection B of the solid line “0” and the broken line.
It becomes V _B. Therefore, the value of V _Sio takes V _A or V _B depending on the logic state of the memory cell.

On the other hand, since the logic state of the dummy cell is always "1", the potential V _R of the reference line RL becomes a voltage V _C corresponding to the abscissa of the intersection C between the solid line "1" and the dashed-dotted line.

The differential amplifier circuit 40 compares V _Sio with _VR , determines whether the logic state of the memory cell is "1" or "0", and outputs the result as V _Sput .

[Problems with background technology]

In the sense circuit according to the conventional technology described above, as the power supply voltage V _CC is increased, the value of V _Sio when the memory cell is in the "0" state, that is, V _B becomes smaller, and V _A to V _B
amplitude becomes smaller. This resulted in a disadvantage that the operating margin was reduced and stability was lacking.

Further, if the power supply voltage V _CC is further increased, V _B becomes smaller than the reference voltage V _C , and the relationship between V _B and V _C may be reversed, causing the device to become inoperable. This example is the third
As shown in the figure. FIG. 3 is a graph showing the characteristics of memory cell transistor 1 and load transistors 4 and 10 when the power supply voltage V _CC =7V. Each characteristic curve and each point are the same as in FIG. 2, so the same symbols are used. The attached explanation will be omitted. Since the power supply voltage V _CC has been increased, the relationship between V _B and V _C has been reversed, making it inoperable.

[Purpose of the invention]

Therefore, the present invention improves the maximum operating power supply voltage,
Moreover, it is an object of the present invention to provide a sense circuit that does not reduce its operating margin even when the power supply voltage becomes high.

[Summary of the invention]

A feature of the present invention is that in a sense circuit having a dummy cell having the same configuration as a memory cell, a first load transistor has a source connected to a power supply, a drain connected to a memory cell, and a gate connected to a gate of a second load transistor. and a second load transistor whose source is connected to the power supply, whose drain is connected to the dummy cell, and whose gate is connected to the gate of the first load transistor, and whose gate and drain are connected, and the first load transistor is connected to the first load transistor. Since the transistor and the second load transistor constitute a current mirror, the differential amplifier circuit that receives the drain of the first load transistor and the drain of the second load transistor as inputs has sufficient operating margin. It is possible,
Moreover, the maximum power supply voltage is improved.

[Embodiment of the Invention] A circuit diagram of an embodiment of the invention is shown in FIG. Here, the same elements as in Fig. 1 are given the same reference numerals.
The explanation will be omitted. Transistors 4' and 10' are p-channel MOS transistors and are load transistors for memory cell 20 and dummy cell 30, respectively. These load transistors are connected to form a current mirror. That is, the sources of both transistors are connected to the power supply, their gates are connected to each other,
The gate and drain of transistor 10' are connected. Each drain output is input to a differential amplifier 40. Note that the transistor 10'
The transconductance gm of is larger than the transconductance of transistor 4'.

Next, the operation of the above circuit will be explained. Fifth
The figure is a graph showing the characteristics of memory cell transistor 1 and load transistors 4' and 10' when power supply voltage V _CC =7V. The horizontal axis indicates the potential V _Sio of the sense line SL or the potential _VR of the reference line RL, and the vertical axis indicates the current flowing through each transistor. The solid line shows the characteristics of memory transistor 1. The solid line marked "1" shows the characteristics when no data is written, and the solid line marked "0" shows the properties when data is written. represents a characteristic. The dash-dotted line is the characteristic of the load transistor 10'. The above three characteristics are similar to the corresponding characteristic curves in FIG. 3. The broken line in FIG. 5 is the characteristic of the load transistor 4', which is different from the characteristic of the load transistor 4 shown by the broken line in FIG. This is because the circuit configuration of the load transistor 4' is made to be a current mirror with respect to the load transistor 10', so the characteristic of the load transistor 4 is a square characteristic, whereas the characteristic of the load transistor 4' is a triode. This is because it becomes a characteristic of the area.

As shown in FIG. 5, when the memory cell is "1", the value of V _Sio is a voltage V _{A corresponding to the abscissa value of the intersection point A between the solid line "1" and the broken line, and the memory cell is "1"} . In the state of "0", the voltage V _B corresponds to the abscissa of the intersection B of the solid line "0" and the broken line. Therefore, the value of V _Sio becomes V _A or V _B depending on the logic state of the memory cell.

On the other hand, since the logic state of the dummy cell is always "1", the voltage V _R of the afterglow line RL becomes a voltage V _C corresponding to the abscissa of the intersection C of the solid line "1" and the dashed-dotted line. As shown in FIG. 5, according to this embodiment, even when the power supply voltage V _CC =7V, a sufficient amplitude of V _A to V _B can be ensured, and operation is possible because V _A < V _C < V _B. It is.

Note that if the mutual conductances gm of load transistors 4' and 10' are equal to each other, points A and C in FIG. 5 overlap and the operation becomes impossible. 4' transconductance.

In the operation of the circuit according to the prior art shown in FIG.
Since the characteristics of both load transistors 4 and 10 are square-law characteristics, when the power supply voltage is set high, the operating margin decreases, and eventually the transistor becomes inoperable. However, in the operation of the circuit according to the present invention shown in FIG. 5, the reference voltage V _R is determined by the characteristics of the load transistor 10' which has square-law characteristics, but V _Sio is determined by the characteristics of the load transistor 4' which has characteristics in the triode region. Since it is determined by the characteristics of Although P-channel transistors are used as the load transistors 4' and 10' in this embodiment, N-channel transistors can also be used by changing the polarity of the power supply.

Next, the principle by which the operating margin of the circuit according to the present invention is improved compared to the circuit according to the prior art will be qualitatively explained. Load transistor 4 according to conventional technology
If the current flowing through is I, I is expressed by equation (1).

I=β(V _CC −V _TH −V _DS ) ² …(1) Here, V _CC is the power supply voltage, V _TH is the threshold voltage,
V _DS is the drain-source voltage of the load transistor 4, and β is a constant. Equation (1) corresponds to the characteristic equation shown by the broken line in FIG. Therefore, the value of V _B -V _A is approximately proportional to the differential coefficient of this characteristic curve (the slope of straight line PP' in FIG. 3). Therefore, by partially differentiating equation (1) with respect to V _DS , equation (2) is obtained.

∂I/∂V _DS = −2β(V _CC −V _DS −V _TH ) ...(2) On the other hand, if the current flowing through the load transistor 4' according to the present invention is I', then the load transistor 4' is 3
Since the operation is in the polar tube region, I' is expressed by equation (3).

I′=β{2(V _GS −V _TH )V _DS −V _DS ² } …(3) Here, V _TH is the threshold voltage, and V _GS and V _DS are the gate-source of the load transistor 4′, respectively. voltage between
It is the drain-source voltage. Equation (4) is obtained by partially differentiating this with respect to V _DS .

∂I′/∂V _DS = β{2(V _GS −V _TH )−2V _DS } ...(4) Since the gate of transistor 4' is connected to the drain, V _GS =
It becomes V _DS . Therefore, equation (4) becomes equation (5).

∂I′/∂V _DS = −2βV _TH ...(5) ∂I/∂V _DS expressed by equation (2) and ∂I′/∂V _DS expressed by equation (5) are These are quantities proportional to the value of V _B −V _A of the sense circuits according to the prior art and the present invention, ie, the slopes of the straight lines PP' and QQ'. To examine these magnitude relationships, use equation (5)
Subtracting equation (2) from ∂I′/∂V _DS −∂I/∂V _DS =2β{(V _CC −2V _TH )−V _DS } ...(6) Here, V _CC −2V _TH ＞ If V _DS , the right side of equation (6) is always positive, that is, ∂I′/∂V _DS > ∂I/∂V _DS . In reality, each transistor operates in a region where V _CC -2V _TH > V _DS . Therefore, from the slope of the straight line PP′, the straight line
The slope of QQ' is always gentler, and the value of V _B −V _A of the sense circuit according to the present invention is larger than that of the sense circuit according to the prior art.

[Effects of the Invention] As described above, according to the present invention, in the sense circuit, one of the load transistors is operated in the triode region, so that the maximum operating power supply voltage can be improved and the operating margin can also be improved. be able to.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a sense circuit according to the prior art.
Figure 2 shows the power supply voltage in the circuit shown in Figure 1.
A graph showing the characteristics of each transistor at 5V,
Figure 3 shows the power supply voltage in the circuit shown in Figure 1.
A graph showing the characteristics of each transistor at 7V,
FIG. 4 is a circuit diagram of an embodiment of the sense circuit according to the present invention, and FIG. 5 is a graph showing the characteristics of each transistor in the circuit shown in FIG. 4 when the power supply voltage is 7V. 1... Memory cell transistor, 2, 3... Transfer transistor, 4, 4'... Load transistor, 5, 6, 7, 8, 9... Differential amplifier circuit transistor, 10, 10'... Load Transistor, 11, 12...transfer transistor, 13...dummy transistor, 20...memory cell, 30...dummy cell, 40...differential amplifier circuit.

Claims (1)

[Scope of Claims] 1. A sense circuit for a semiconductor memory that detects a logic state of a memory cell, comprising: a dummy cell having a dummy transistor having the same characteristics as a memory cell transistor constituting the memory cell; a first load transistor having a drain connected to the memory cell, a gate connected to the gate of the second load transistor; a source connected to the power supply, a drain connected to the dummy cell, and a gate connected to the first load transistor; a second load transistor whose gate and drain are connected to each other, and whose inputs are the drain of the first load transistor and the drain of the second load transistor. A sense circuit for semiconductor memory characterized by comprising an amplifier circuit and the following.