JPH0467195A - Display controlling system, display controlling device, and display device - Google Patents

Abstract

PURPOSE:To make an appropriate half-tone display even when the contrast varies by expressing the half tone of display dots by making an intermittent display which changes the ratio of the displaying period to the nondisplaying period in accordance with a change in the driving voltage of a displaying section. CONSTITUTION:When a contrast (liquid crystal driving voltage) is raised, a level detection circuit 23 detects that a contrast value 20 is 'large' and outputs a half tone selecting signal 24 as 'large'. Since the signal 24 is 'large', a half tone signal selection circuit 25 outputs a half tone signal A151 as a half tone signal 15. When the contrast is lowered, the circuit 25 outputs a half tone signal C153 as a half tone signal 15, since the half tone selecting signal 24 is 'small'. Thus a linear half tone display is always realized even when the contrast is changed, since the effective voltage of the half tone display is controlled. There fore, an appropriate half tone display can be performed even when the contrast varies.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a display device, and particularly to a technique for displaying halftones thereof.

[Prior Art] As a technique for displaying halftones in a conventional display device, for example, a halftone display technique using high-speed blinking display on a liquid crystal display, which is described in Japanese Patent Laid-Open No. 58-57192, is known. ing.

This technique will be explained below using FIGS. 2, 3, and 4.

FIG. 2 shows the configuration of a conventional liquid crystal display device.

In the figure, 1 is an oscillator that generates a reference clock in units of 8 dots, 2 is a character clock that is the reference clock output from oscillator 1, and 3 is a display address generator that repeatedly generates display addresses for one screen according to character clock 2. 4 is a memory address that is a display address output from the display address generation circuit 3, and 51 and 52 are display memories that store display information.

The display memories 51 and 52 are 8-bit data memories, and display information consisting of 2 bits per dot is stored in parallel for each 8 dots, 1 bit each.

61.62 is read from display memory 51.52 8
This is display data of dot width, and each corresponding bit (2 bits) represents one dot.

When the two bits of the display data 61 and 62 for each dot are both "low", the display is OFF, when both are 1' high, the display is ON, and at other times, a halftone display is indicated. In addition, here, display ON means "display",
Display OFF is used to mean "non-display."

Reference numeral 7 indicates a timing signal generation circuit, 8 a frame signal, 9 a line signal, and 10 a data shift signal.The timing signal generation circuit 7 generates a frame signal 8, a line signal 9, and a data shift signal 10 in accordance with the character clock 2. do.

11 is a halftone control circuit; 12 is clocked by frame signal 8; II Q 7+, tt I II it 2"
13 is a frame count value which is the count value of the frame counter 12, 14 is a halftone signal generation circuit, 15 is a halftone signal, and the halftone signal generation circuit 14 is a halftone signal. ,
When the frame count value 13 is II OIT and PA2'', the halftone signal 15 is set to 'HIGH', and at other times it is set to PALOW'.

16 is a display control circuit, and 17 is 8-dot wide liquid crystal display data in which each bit represents ON or FF of each dot.

The display control circuit 16 uses the information in the display data 61 and 62 to display the state of the halftone signal 15 on the liquid crystal display, such as "Pa high" for normal display, "Low" for display OFF, and "Low" for half tone display. data]-7.

18 is an X that displays the liquid crystal display data 17 as visible information;
This is a dot xy line liquid crystal display panel.

19 is a contrast volume for adjusting the contrast; 20 is a contrast value indicating the adjustment value of the contrast volume 19; 21 is a voltage control circuit for controlling the contrast adjustment voltage; 22 is a contrast adjustment voltage output from the voltage control circuit 21; At the liquid crystal opening voltage, the voltage control circuit 21 reads a contrast value 20 that changes according to the contrast volume 19, and controls the liquid crystal display panel 1.
The liquid crystal drive voltage 22 applied to 8 is changed.

Now, in FIG. 2, the display information stored at the address indicated by the memory address 4 output from the display address generation circuit 3 is read out from the display memories 51 and 52.

Each piece of information read out is 8 bits and is given to the display control circuit 16 as display data 61 and 62. The display control circuit 16 sets the state of the halftone signal 15 to be 11 high for normal display and to be high twice every 4 frames for halftone display, depending on the state of each bit of display data 61 and 62. , and when the display is OFF, each state of "low" is output to the liquid crystal display panel 18 as 8-dot, 8-bit liquid crystal display data 17.

Therefore, since the display address generation circuit 3 generates memory addresses for one screen in j terms, the display data for one screen is sequentially given to the liquid crystal display panel 18 in units of 8 dots as the liquid crystal display data 17. .

The liquid crystal display panel 18 sequentially launches the liquid crystal display data 17 in accordance with the data shift signal 10, latches one line of data (X dots), and then launches one line per line.
It is displayed as visible information using a line signal 9 outputted as a clock.

This operation is repeated for y lines to display one frame.

Further, the beginning of the frame is indicated by frame signal 8,
When the frame signal is "high", the liquid crystal display panel 18
Displays from the first line.

By repeating the operations explained above, the liquid crystal display panel 18
The display information stored in the display memories 51 and 52 is displayed on the top.

FIG. 3 is an explanatory diagram showing the liquid crystal display data 17 of O to 3 frames and the display state of the liquid crystal display panel 18. A specific display example will be shown using this figure.

Now, the display memories 51 and 52 both store information representing the characters 1/A++, that is, display information in which the bit corresponding to the character tt A IT is Jl 1 p+.

Also, the bit corresponding to the character II B ++ is If
The display information of l+1 is stored only in the display memory 51. At this time, the bit in the display memory 52 corresponding to the character II B IT is .largecircle.''.

In this case, the display control circuit 16 outputs the signal A'' for each frame for IL A II, and outputs the state of the halftone signal 15 for KL B ++.

That is, as shown in FIG. 3, for 0.2 frames, the frame count value 13 output by the frame counter 12 is
Since 11 Q +1 , II 2 ++, the halftone signal 15 is also "high", and If A II , II 1
3++ both become "high" and are applied to the liquid crystal display panel 18, but in 1.3 frames, the halftone signal 15 becomes "high".
The character tL B TT is not given to the liquid crystal display panel 18 because it is low ''. Therefore, the characters tr B ++ are applied to the liquid crystal display panel 18 only twice every four frames.

Therefore, compared to the characters LL Al1 given every frame, the effective voltage on the liquid crystal display panel]8 is lower.
It becomes a halftone display.

FIG. 4 is an explanatory diagram showing the relationship between display brightness and effective voltage on the liquid crystal display panel 18.

The effective voltage vA is 71 A when the display is ON every frame.
The effective voltage corresponding to tt is the effective voltage, and the effective voltage v1 is the effective voltage corresponding to "B" which is displayed twice in 4 frames.
Effective voltage ■. indicates the effective voltage corresponding to the display OFF, and LA, LIB, and Lo are the effective voltages VA, VB,
■Display brightness relative to o, i.e. JIA”, 11 B
Display brightness corresponding to j+ and no display is shown.

Effective voltage of 11 B tl performing halftone display■1
is the intermediate value between the effective voltage of A'' when the display is ON (6) and the effective voltage (■) when the display is OFF, and the relationship is (VA
VO)+VO=VB''(1).At this VA, ■0, ■, display brightness LA, LB-
Assuming that the LO relationship is in a desirable state, the display brightness is logarithmic, so the relationship is 2(logL, -Log
Lo)+logLo=logLp (2).

[Problems to be Solved by the Invention] As described above, according to the prior art, halftone display can be realized.

However, there is no consideration given to the display brightness of the halftone display when the contrast is adjusted, and there is a problem that the relationship between the display brightness when one display is ON and when the display is OFF is not constant at each contrast point.

This problem will be explained using FIGS. 5 and 6.

FIG. 5 is an explanatory diagram showing the relationship between the effective voltage and the display brightness when the contrast is increased (in the prior art, the liquid crystal drive voltage is increased).
, 1 are the above-mentioned (1)6, (2)8, V, and 1-, respectively.

It corresponds to V,,1''= vA+a, VRl-=VB+α, V,1
=VC+α (α is a positive real number) Therefore, the relationship between VAI, V B1, and Vol is as follows, and the same relationship as in equation (1) holds true.

However, the relationship between each effective voltage and display brightness is generally not linear, as shown in the figure.

Therefore, in this case, the relationship between LA1, LB1, and Lol is as follows, which is different from the relationship in equation (2) described above.

Similarly, FIG. 6 is an explanatory diagram showing the relationship between effective voltage and display brightness when the contrast is lowered (in the prior art, the liquid crystal drive voltage is lowered).

In this case, V,, 2: V,, -β, V, 2=V, -β,
The relationship is V o 2 ” V s-β (β is a positive real number). Therefore, VA2, V B 2, VL:
2 is the same as equation (1), but L, 2, L
B2, L. The relationship between 2 is 4(1ogLA2-LogLO2)+1ogLo2>
1ogLB2, which is different from the relationship in equation (2).

As described above, according to the prior art, there is a problem in that when the contrast is changed, the relationship between the display brightness of the halftone display and the display brightness when the display is ON and when the display is OFF changes.

Therefore, the present invention provides the following advantages: Even when the contrast changes,
It is an object of the present invention to provide a display device that can perform appropriate halftone display.

[Means for Solving the Problem] In order to achieve the above object, the present invention provides a method for displaying a display by intermittent display in which the ratio of the display period to the non-display period is changed in accordance with changes in the drive voltage of the five display sections. Provided is a display control method for a display device characterized by expressing dotted intermediate tones.

Furthermore, in order to achieve the above object, the present invention is a display device that expresses halftones by intermittent display of display dots, and the display period and non-display period of the halftone display dots are adjusted according to changes in display contrast. A first display device characterized in that the proportion of a display period changes.

In particular, the present invention provides a liquid crystal display device with variable driving voltage, in which display dots to be displayed in halftones are intermittently applied to the liquid crystal display panel with variable driving voltage in order to achieve the above object. A display control device having a half-tone display means for displaying, the display control device including a detection means for detecting the above-mentioned dead voltage value, wherein the half-tone display means has a display period of 5 display periods according to the half-tone voltage value detected by the detection means. and percentage of hidden period,
A first display control device is provided which is characterized in that display dots to be displayed in halftone are intermittently displayed on a display panel.

Further, in the display control device of Sui-Tei 1, the halftone display means switches a plurality of timing patterns, which are prepared in advance, for defining a display period and a non-display period, in accordance with the drive voltage value detected by the detection means. By changing the ratio of the display period to the non-display period, the ratio of the display period to the non-display period is determined according to the liver motion voltage value detected by the detection means.
Display dots that should be displayed in halftones may be displayed intermittently on the display panel.

Note that switching between the display period and the non-display period may be performed in units of frame periods.

Further, in order to achieve the above object in a liquid crystal display device with a variable driving voltage, the present invention provides a display control device for controlling the display of a liquid crystal display panel with a variable driving voltage, the value of the opening voltage being m (m m is an integer of 2 or more); a frame counter that counts the number of display frames; and a frame counter that instructs display only when the count value of the frame counter is a predetermined value. a halftone signal generating section that generates halftone signals of m kinds (an integer number); and a halftone signal generator that selects one halftone signal from among the m kinds of halftone signals according to the type classified by the level detection circuit. A second display control device comprising a signal selection circuit and, for display dots to be displayed in a halftone, a control circuit that outputs a halftone signal selected by the halftone signal selection circuit to the display panel. I will provide a.

Note that in the display control device of Sui-Tei 2, the halftone signal generating section generates a halftone signal that instructs display only when the count value of the frame counter provided individually for each is a predetermined value. The configuration may include m halftone signal generation circuits.

Furthermore, in order to achieve the above object, the present invention provides a second display device comprising a liquid crystal display panel whose drive voltage is variable and the first or second display control device.

Note that the first and second display control devices may be built into a liquid crystal display panel.

Furthermore, it may be built into the display driver.

Note that in this case, the display driver uses TAB (Tape-
It is preferable to use automated bonding.

Additionally, the present invention provides a liquid crystal display panel with a variable drive voltage, the first or second display control device, or a liquid crystal display panel incorporating the display control device, and a liquid crystal display panel with a variable driving voltage. An information processing apparatus is also provided, characterized in that it has a central processing unit that generates display data including the information processing apparatus.

[Function] According to the display control method according to the present invention, the ratio between the display period and the non-display period is changed according to the change in the opening voltage of the display section,
By performing intermittent display, the display brightness of the halftone display can be set to an appropriate brightness, so the relationship between the halftone display brightness and the display brightness during display and non-display can be kept constant. .

Further, according to the first display device according to the present invention, the ratio of the display period to the non-display period of the halftone display dot changes according to the change in display contrast, so that as a result, according to the change in contrast, The relationship between the display brightness of halftone display and the display brightness during display and non-display changes.

Further, according to the first display control device according to the present invention, the halftone display means displays the halftone at a ratio of the display period to the non-display period according to the moving voltage value detected by the detection means. Since the display dots to be displayed are intermittently displayed on the display panel, the relationship between the halftone display brightness and the display brightness during display and non-display can be maintained appropriately.

Further, according to the second display control device according to the present invention, the halftone signal generation section generates m kinds of halftone signals that instruct display only when the count value of the frame counter is a predetermined value. The halftone signal selection circuit selects one halftone signal from the m types of halftone signals according to the type classified by the level detection circuit, and the control circuit selects one halftone signal from among the m types of halftone signals, and the control circuit selects one halftone signal to be displayed in halftones. For dots, the halftone display signal selected by the halftone signal selection circuit is output to the display panel.

As a result, the display panel intermittently displays the halftone display dots at a ratio of display period to non-display period depending on the drive voltage, so that the halftone display brightness and the display brightness during display and non-display are different. can maintain proper relationships.

(Margin below) [Example] An example of a display device according to the present invention will be described below, taking as an example the same liquid crystal display device as the conventional example.

FIG. 1 shows the configuration of a liquid crystal display device according to this embodiment.

In the figure, 1 is an oscillator that generates a reference clock in units of 8 dots, 2 is a character clock that is the reference clock output from oscillator 1, and 3 is a display address generator that repeatedly generates display addresses for one screen according to character clock 2. 4 is a memory address that is a display address output from the display address generation circuit 3, and 51 and 52 are display memories that store display information.

61.62 is read from display memory 51.52 8
This is bit-width display data, and each corresponding bit (2 bits) represents one dot.

7 is a timing signal generation circuit, 8 is a frame signal, 9 is a line signal, and 10 is a data shift signal, and the timing signal generation circuit 7 generates a frame signal 8, a line signal 9°, and a data shift signal 10 in accordance with the character clock 2. do.

16 is a display control circuit, and 17 is 8-bit liquid crystal display data, each bit representing ○N or OFF of each dot.

The display control circuit 16 uses the information in the display data 61 and 62 to display the state of the halftone signal 15 on the liquid crystal display: "high" for normal display, "low" for display ○FF, and "low" for halftone display. Output to data 17.

18 is an X that displays the liquid crystal display data 17 as visible information;
This is a dot xy line liquid crystal display panel.

19 is a contrast volume for adjusting the contrast, 20 is a contrast value indicating the adjustment value of the contrast volume 19, 2 is a voltage control circuit for controlling the contrast adjustment voltage, and 22 is output from the voltage control circuit 21. At the liquid crystal disturbance voltage of the contrast adjustment voltage, the voltage control circuit 21 reads the contrast value 20 that changes according to the contrast volume 19 and changes the liquid crystal active voltage 22 applied to the liquid crystal display panel 18.

Note that each of the above parts is the same as the part with the same reference numeral according to the prior art shown in FIG. 2 earlier.

11 indicates a halftone control circuit; 141 to 143 indicate halftone signal generation circuits A, B, and C; 1151 to 153 indicate halftone signals A, B, and C; 123 indicate a level detection circuit; 24 indicates a selection signal output from the level detection circuit A certain halftone selection signal, 2
5 is a halftone signal selection circuit.

The halftone signal generation circuit A141 has a frame count value of 1.
When 3 is II Q 7+, the halftone signal A151 is set to ``high'', and at other times, it is set to ``low''.

The halftone signal generation circuit B142 generates the halftone signal B15 when the frame count value is II OII, It 2 ++.
Set 2 to "high" and set to "low" at all other times.

The halftone signal generating circuit C143 sets the halftone signal C153 to "high" when the frame count value is II Q II, II II II, il 2 ++, and to 110-" otherwise.

The level detection circuit 23 sets the contrast value 20 to 11",
The detection is divided into three levels: "medium" and "small", and the results are output as the halftone selection signal 24.The halftone signal selection circuit 25 outputs the halftone signal A151 when the halftone selection signal 24 is "dog". If the value is "medium", the value of the halftone signal B152 is output as the halftone signal 15, and if it is "small", the value of the halftone signal C153 is output as the halftone signal 15.

Next, the operation of this liquid crystal display device will be explained.

Now assume that the contrast (liquid crystal active voltage) is standard.

At this time, the level detection circuit 23 detects a contrast value of 20
is detected to be "medium", and sends it to the halftone selection signal 24''
Outputs “medium”.

Then, the halftone signal selection circuit 25 receives the halftone selection signal 24.
Since it is "medium", the halftone signal B152 is output as the halftone signal 15.

Now, similarly to the example shown in the prior art, the display memory 51
．． 52, the information representing the character N A ++, that is, the bit corresponding to the character 11 A 11 is It I
++ display information is stored, and lr B P
It is assumed that display information in which the bit corresponding to the + character is "1'" is stored only in the display memory 51.

In this case, the display control circuit 16 outputs "high" for each frame for l(AIT, and outputs the state of the halftone signal 15 for 6B, so the frame counter 12 outputs the state of the halftone signal 15 for 6B). Frame count value 13 is 1
10 tl, l (because of 211, halftone signal B152 is "high", halftone signal 15 is also "high", RA"
, ``B'' are both ``high'' and applied to the liquid crystal display panel 18, but in 1.3 frames, the halftone signal B152 is ``low'' and the halftone signal 15 is also ``low''.
The characters ''' are not provided to the liquid crystal display panel 18.

Above, we have described the case where the contrast (liquid crystal active voltage) is standard, but the operation and operating state in this case are as follows.
This is exactly the same as the conventional example.

Therefore, the relationship between the effective voltage on the liquid crystal display panel 18 and the display brightness is the same as that shown in FIG. 4 shown above.

Next, a case where the contrast (liquid crystal active voltage) is increased will be explained.

In this case, the level detection circuit 23 detects a contrast value of 20
is detected to be "large" and sends "large" to the halftone selection signal 24.
Output.

Since the halftone selection signal 24 is "large", the halftone signal selection circuit 25 outputs the halftone signal A151 as the halftone signal 15.

In this case, the display control circuit 16 outputs "high" for each frame for "A'', and outputs the state of the halftone signal 15 for II B++, so the frame counter 12 outputs The frame count value 13 is ○
Therefore, the halftone signal A151 is "high", the halftone signal 15 is also "high", and both "A" and II B F+ are "high".
``high'' and is applied to the liquid crystal display panel 18, but 1
．． In frame 2.3, the halftone signal A151 is "low"
The halftone signal 15 is also "low", and the character l(B) is not applied to the liquid crystal display panel 18.

Therefore, the character 'B' is applied to the liquid crystal display panel 18 only once every four frames.

FIG. 7 shows the relationship between the effective voltage on the liquid crystal display panel 18 and the display brightness at this time. vB3 represents the effective voltage of it B H, L B 3 represents the display brightness of 18 B II, and parts corresponding to those in FIG. 5 shown above are given the same reference numerals.

11 A jl effective voltage VA1, II B Tl effective voltage ■l113, hidden effective voltage ■. The relationship of 1 is
becomes.

Therefore, the relationship between display brightness LA1, LA3, L,] is as follows.
It will look like this:

becomes.

In other words, the value of the effective voltage V n 3 is smaller than the relationship expressed by equation (3), but the display brightness can be made to have a relationship closer to that expressed by equation (4).

Next, a case where the contrast (liquid crystal drive voltage) is lowered will be explained.

In this case, the level detection circuit 23 detects the contrast value 20 as "small" and outputs "small" to the halftone selection signal 24.

Then, the halftone signal selection circuit 25 receives the halftone selection signal 24.
is "small", the halftone signal C153 is output as the halftone signal 15.

In this case, the display control circuit 16 outputs "high" for each frame for If A u, and outputs the state of the halftone signal 15 for II B II. 1. Since the frame count value outputted by 12]3 is Pa○'°, N], -. When the halftone signal C]53 is "high" and the halftone signal 15 is also "high", II API and tL B Tl are both "high" and are given to the liquid crystal display panel 18, but in the third frame, the halftone signal C153 is "high". The halftone signal 15 is also low and the character RB II is not provided to the liquid crystal display panel 18.

Therefore, the character 'B' is applied to the liquid crystal display panel 18 three times in four frames.

FIG. 8 shows the relationship between the effective voltage on the liquid crystal display panel 18 and the display brightness at this time. VB5 represents the effective voltage of 11B II, L, 5 represents the display brightness of itB'', and parts corresponding to those in Fig. 6 shown above are given the same symbols. ■A2.1 (B II effective voltage ■l) 4, non-display effective voltage ■.The relationship between 2 is as follows.The relationship between display brightness LA2, LB4, L, and 2 is as follows. In other words, the value of the effective voltage V B4 is larger than the relationship expressed by equation (3), but the display brightness maintains a relationship close to that expressed by equation (4).

As described above, according to this embodiment, even when the contrast (liquid crystal drive voltage) is changed, the effective voltage for halftone display can be controlled, so that a linear halftone display can always be realized.

In addition, in the embodiment described above, 1 and 4 frames are
Although explained as a cycle, it is not limited to this, and the frame counter 12 is set to N (N is an integer of 2 or more) base,
Each halftone signal generation circuit, 141, B142, C1
By changing 43, a circuit with an N frame period can be easily realized.

Furthermore, the configuration of the halftone signal generation circuit is, for example,
In the case of the 4-frame cycle shown in this embodiment, the frame count value can be decoded using a decoder consisting of an AND circuit 26, a logic inversion circuit 27, and an OR circuit shown in FIG. .

Furthermore, if the period is other than the 4-frame period, a frame counter 12 corresponding to the period may be provided and a decoder for decoding the frame counter 12 may be used.

Further, the halftone signal generation circuit has a frame count value of 13.
It can also be realized by a pattern storage device or the like that uses .

That is, when the period is 4 frames, the halftone signal generating circuit A141 has a frame count value 13 of 1 (OI
When the frame count value 13 is tr Otp and tr 2 tr, the halftone signal generation circuit B 142 is "high", and the halftone signal generation circuit C 143 is "high" when the frame count value 13 is tr Otp and tr 2 tr. and 11271, it becomes "high", and each of the 8 outputs becomes a halftone signal A152, B
152 and C Yu 53, a pattern storage device such as a memory in which such patterns are stored is provided.

In addition, when realizing a wider variety of combinations, it can be easily realized by changing the storage pattern of the pattern storage device, switching a plurality of decoders, etc.

In addition, the pattern storage device is configured with a memory that can be read and written freely, and by changing the storage pattern according to the effective voltage versus display brightness characteristics of the liquid crystal display panel 18, it can be used for multiple types of liquid crystal display panels with different characteristics. It may be possible to do so.

In addition, in this example, the contrast (liquid crystal drive voltage) is
Although it is divided into three stages of "large", "medium", and "small", it is not limited to this, and the halftone signal generation circuit is m (m
is an integer of 2 or more), the level detection circuit 23 discriminates m types of contrast values 20, and the halftone signal selection circuit 2
By configuring 5 with a selector that selects one from m types of halftone signals, it is possible to easily deal with m stages of contrast (liquid crystal running voltage).

Further, the frame counter 12 with a different base number is M
(M is an integer between 1 and m), and by connecting at least one halftone signal generation circuit to one frame counter, a more detailed halftone display circuit can be realized. You can also do it.

In addition, in the embodiments described so far, a case has been described in which three gradation levels are displayed including all frame display ON and all frame display OFF, but n types of halftone signal generation circuits,
And, n types of halftone signal selection circuits 25 are prepared (n is an integer of 1 or more), and the display control circuit 16 selects "high", 60
-'' and n types of halftone signals 15, one is selected and output as the liquid crystal display data 17, thereby making it possible to display n,22 gradations.

Note that this embodiment is not limited to monochrome display. That is, the invention can also be applied to liquid crystal display devices that perform color display.

Here, an information processing device such as a word processor or a personal computer using the liquid crystal display device described above will be explained.

FIG. 10 shows the configuration of this information processing device.

In the figure, 101 is a CPU, 107 is a bus, 102 is a main memory, and 104 is a small compute
erSystem Interface) 103 is an external storage device connected to the bus 107, and 106 is a keyboard connected to the bus 107 via a keyboard interface 105.

The other part is the liquid crystal display device according to this embodiment shown in FIG. 1 previously.

The CPU 101 connects to the display memory 51 via the bus 107.
．． Display information such as images to be displayed is written in 53.

As described above, the liquid crystal display device according to this embodiment can be used in an information processing device and the like.

Note that the halftone display circuit described in this embodiment may be provided in a liquid crystal display panel.

Further, these halftone display circuits may be built into a liquid crystal driver used in a liquid crystal display panel.

Furthermore, in one or more embodiments, a liquid crystal display device using a liquid crystal display panel has been described as an example, but other display devices such as a liquid crystal projector or a liquid crystal display may also have a non-linear effective voltage versus display brightness characteristic. Alternatively, if there is a saturation region, this embodiment can be similarly implemented and has the same effect.

However, since 0N10FF is controlled for each frame, it is necessary to make the frame frequency high enough to avoid problems such as flicker.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a display device that can display an appropriate medium tone even when the contrast changes.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a display device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a display device according to the prior art, and FIG. 3 shows display information when displaying halftones. FIG. 4, FIG. 5, and FIG. 6 are explanatory diagrams showing the relationship between display on a liquid crystal display panel, and FIGS. 7 and 8 are explanatory diagrams showing the relationship between effective voltage and display brightness on a liquid crystal display panel in a display device according to an embodiment of the present invention, and FIG. FIG. 10 is a block diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention. 1... Oscillator, 2... Character clock, 3...
・Display address generation circuit, 4...Display address, 51
．． 52...Display memory, 61.62...Display data,
7...Timing signal generation circuit, 8...Frame signal, 9...Line signal, 10...Data shift signal, 1
1... Halftone control circuit, 12... Frame counter,
13... Frame count value, 141-143... Halftone signal generation circuit, 151-153... Halftone signal,
15. Halftone signal, 16. Display control circuit, 17. Liquid crystal display data, 18. Liquid crystal display panel, 19. Contrast volume, 20. Contrast value, 21.
... Voltage control circuit, 22.. Liquid crystal drive voltage, 23. Level detection circuit, 24.. Halftone selection signal, 25.. Halftone signal selection circuit, 26.. AND circuit, 27. Logic inversion circuit. Applicant: Hitachi, Ltd. (and 1 other person) Agent: Patent attorney Tomi 1) Interest 111 Figure 2 Figure o1 s1 A1 Effective voltage [V] o2 s2 A2 Effective voltage [V] Figure flavor ■0 B A Effective voltage port V o1 B3 VAI effective voltage rV] o2 s4 A2 Effective voltage mV] Figure 9 Frame count value 13 Figure 10

Claims (1)

[Claims] 1. A display characterized by expressing intermediate tones of display dots through intermittent display in which the ratio of the display period to the non-display period is changed in accordance with changes in the drive voltage of the display section. Device display control method. 2. A display device that expresses halftones by intermittent display of display dots, characterized in that the ratio of the display period and non-display period of the halftone display dots changes according to changes in display contrast. Display device. 3. A display control device having a halftone display means for intermittently displaying display dots to be displayed in a halftone on a liquid crystal display panel whose drive voltage is variable, the display control device comprising: a detection means for detecting the drive voltage value; The halftone display means includes a means for displaying a half tone according to the drive voltage value detected by the detection means.
A display control device that intermittently displays display dots to be displayed in halftone on a display panel at a ratio between a display period and a non-display period. 4. The display control device according to claim 3, wherein the halftone display means uses a plurality of timing patterns prepared in advance to define a display period and a non-display period according to the drive voltage value detected by the detection means. By switching the ratio between the display period and the non-display period, the display dots that should be displayed in halftone are displayed at the ratio of the display period and the non-display period according to the drive voltage value detected by the detection means. A display control device characterized by intermittent display on a panel. 5. The display control device according to claim 2, 3 or 4, wherein switching between the display period and the non-display period is performed in units of frame periods. 6. A display control device that controls the display of a liquid crystal display panel with a variable drive voltage, comprising: a level detection circuit that classifies drive voltage values into m types (m is an integer of 2 or more); and a level detection circuit that counts the number of display frames. a frame counter; a halftone signal generator that generates m types of halftone signals that instruct display only when the count values of the frame counters are respectively predetermined values; , a halftone signal selection circuit that selects one halftone signal from the m kinds of halftone signals, and a halftone signal selection circuit that selects one halftone signal from the m types of halftone signals; A display control device comprising: a control circuit that outputs output to a display panel. 7. The display control device according to claim 6, wherein the halftone signal generating section generates a halftone signal that instructs display only when the count values of frame counters provided individually are respective predetermined values. 1. A display control device comprising m halftone signal generation circuits that generate m halftone signal generation circuits. 8. A liquid crystal display panel with variable driving voltage; Claims 3 and 4;
8. A display device comprising the display control device according to 5, 6 or 7. 9. A liquid crystal display panel incorporating the display control device according to claim 3, 4, 5, 6 or 7. 10. A display driver for use in a liquid crystal display panel with variable drive voltage, characterized in that it incorporates the display control device according to claim 3, 4, 5, 6, or 7. 11. Liquid crystal display panel with variable driving voltage and claims 3 and 4.
An information processing device comprising: the display control device according to claim 5, 6, or 7; or the liquid crystal display panel according to claim 9; and a central processing device that generates display data including halftones to be displayed on the display panel.