JPH0464251A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the integration of a semiconductor device by forming cells without space on the whole face of a semiconductor substrate without partitioning a cell region and a wiring region, and applying wiring at the upper layer of this cell. CONSTITUTION:Wiring lead terminals 5... are the ones for performing the in-cell wiring of the cells being made without space on the whole face of a semiconductor substrate 9. These wiring lead terminals 5 are wired by the in-cell wiring layers 7 ... formed respectively at the upper layers of the cells 1... These in-cell wiring layers 7 are constituted of high melting point materials. And the wiring mutual junctions 6, which are made at the optional positions of the in-cell wiring layers 7 are connected by the cell mutual wiring layers 8 made at the upper layer 8 of the wiring layers 7. The wiring layer 8 consist of low electric resistance materials, and are made at the layer upper than the in-cell wiring 7. Thereupon, the cells can be made on the whole face of a semiconductor substrate, and the integration can exceptionally be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and in particular, to a semiconductor device in which an intra-cell wiring layer and a cell interconnection layer are formed in the upper layer of cells that are formed without gaps over the entire surface of a semiconductor substrate. This is intended to improve the degree of integration of the semiconductor device.

[Prior Art] Conventionally, the following two methods have been used in the arrangement and wiring of cells in semiconductor devices.

The first method is a standard cell method as shown in FIG. In this method, each cell for an integrated circuit is formed on a semiconductor substrate, t=cell area 2, and this cell area 2.
The wiring area 4 is divided into a wiring area 4 for wiring 3 of each cell l- in the wiring area.

In addition, the second method is shown in Fig. 5, as shown in f2, a custom r
This is the Sea of Gate method (hereinafter abbreviated as SOG method) used for applications such as C. This method uses a buried gate array G formed on the entire surface of the semiconductor substrate.
is used. And each cell la necessary for the circuit
. . . The wiring 3 between them is connected to another cell 1b that is unnecessary for circuit formation.
・This is done at the top.

[Problem to be solved by the invention] In recent years, large-scale DSP technology has been developed in the field of electronic musical instruments, etc.
(D digital signal process
or) etc. have come to be used. Since the number of gates in this DSP reaches nearly 10,000, there is a great desire for its integration.

However, when such an SP or the like is constructed using the standard cell method described above, the semiconductor substrate is divided into the cell area 2 and the wiring area 4, which limits the area of the semiconductor substrate that can be used as the cell area 2. There was a limit to the degree of accumulation.

Also, since the SOG method uses a gate array G,
Although it is easy to increase the number of cells, an excessive load is placed on the cells 1b below the wiring 3.

Therefore, it becomes difficult to use the cells 1b under these wiring lines 3 as a circuit, and since this portion becomes a wiring area, there is an inconvenience that the number of usable cells is limited.

This invention was made to solve the above problems, and by forming cells without any gaps on the entire surface of a semiconductor substrate without separating the cell area and the wiring area, and by providing wiring on the upper layer of the cell, The purpose is to improve the degree of integration of semiconductor devices.

[Means for Solving the Problems] Does the semiconductor device of the present invention cover the entire surface of a semiconductor substrate? Wire take-out terminals are provided in a plurality of cells formed without gaps, and wiring is formed between these wire take-out terminals using a high melting point material in the upper layer of the cell to form an intra-cell wiring layer. The solution was to form a cell interconnection layer by providing connection points and wiring between the interconnection points using a low electrical resistance material in a layer above the intra-cell interconnection layer.

[Function] A cell is formed on the entire surface of the semiconductor substrate without any gaps, a wiring lead-out terminal is provided at an arbitrary location on each cell, and the wire lead-out terminal is wired with a high melting point material in the entire area of the upper layer of the cell to form internal cell wiring. Since the layers are formed, the semiconductor substrate is no longer divided into a cell region and a wiring region.

Furthermore, for wiring between cells, wiring interconnection points are provided in the intra-cell wiring layer, and these wiring interconnection points are routed using a low electrical resistance material in a layer above the intra-cell wiring layer. Since the cells are formed in this manner, cells can be formed even in areas that were conventionally used as wiring areas, and the degree of integration can be improved.

In addition, by providing wiring take-out terminals and wiring interconnection points, limiting the materials for each wiring, and wiring in different layers, no load is placed on the cells underlying the wiring, so all It becomes possible to use cells, and the degree of layer integration can be improved.

[Example] The present invention will be explained in detail below.

FIG. 1 shows an example of a semiconductor device of the present invention.

In the semiconductor device of the present invention, a plurality of buried cells 1 are formed on the entire surface of a semiconductor substrate without any gaps, and wiring lead-out terminals 5 are provided at arbitrary locations of these cells 1.
. . . and inter-wiring connection points 6 . was formed.

FIGS. 2 and 3 show the main parts of FIG. 1 in an enlarged manner.

FIG. 2 shows an outline of the intra-cell wiring layer 7, and FIG. 3 shows an outline of the cell interconnection layer 8.

The cells 1 are formed by diffusing various ions into the semiconductor substrate 9, and a plurality of cells are successively formed over the entire surface of the semiconductor substrate.

Wire extraction terminals 5, . . . are provided at arbitrary locations in these cells 1-. This wiring take-out terminal 5.
The cells 1 and 1 are formed on the entire surface of the semiconductor substrate 9 without any gaps.
・This is for wiring inside the cell. Wiring is provided between these wiring lead-out terminals 5 using intra-cell wiring layers 7 formed in the upper layer of the cell 1, respectively. This intra-cell wiring layer 7 is made of MoS i2. W Si
Silicide compounds, which are compounds of high melting point metals such as 2 and silicon, polysilicon, Ta, M
It is composed of so-called high melting point materials such as O, W, Ti, and P L.

Then, as shown in FIG. 3, the wiring between cells is formed on the upper layer of the intra-cell wiring layer 7 between wiring interconnection points 6 formed at arbitrary positions on the intra-cell wiring layer 7. This is done by connecting through the cell interconnection layer 8 that has been formed. This cell interconnect layer 8 is made of a low electrical resistance material such as aluminum, and is formed above the intra-cell interconnect 7 .

The wiring lead-out terminals 5 . . . , the wiring interconnection points 6 , the intra-cell wiring layers 7 , and the cell interconnection layers 8 . . . are all formed by ordinary thin film forming means used in semiconductor manufacturing processes.

In the semiconductor device of the present invention, (1) a cell is formed on the entire surface of the semiconductor substrate 9 without any gaps; (2) the wiring take-out terminals 5 provided in the cell are wired in the intra-cell wiring layer 7 above the cell. (1) Wiring interconnection points 6 provided in the intra-cell wiring layer 7 are connected to the intra-cell wiring layer 7.
By wiring in the upper layer and wiring between cells, a semiconductor device with a high degree of integration can be obtained without adding a large amount to each cell in the lower layer.

When the semiconductor device is configured in this way, the intra-cell wiring layer 7... and the cell interconnection layer 8... are formed on the upper layer of each cell, so a special wiring area is set on the semiconductor substrate. It becomes possible to provide a plurality of cells continuously over the entire surface of the semiconductor substrate, and the degree of integration of the circuit can be improved.

Furthermore, all of the cells formed on the semiconductor substrate can be used as a circuit, and each element can be connected freely, which improves the degree of freedom in circuit design. Furthermore, each element can be connected efficiently.

Note that if it is impossible to conduct wiring only on the cells formed over the entire surface of the semiconductor substrate, a small amount of wiring area 4 may be set between each cell as in the conventional semiconductor device.

[Effects of the Invention] As explained above, in the semiconductor device of the present invention, wiring lead-out terminals are provided in a plurality of cells formed without gaps over the entire surface of a semiconductor substrate, and a high-melting point material is formed between the wiring lead-out terminals in the cell upper layer. At the same time, interconnection points are provided in this intracell wiring layer, and wiring is performed between these interconnection interconnection points using a low electrical resistance material in a layer above the intracell wiring layer. Since the cell interconnection layer is formed in the semiconductor substrate, the semiconductor substrate is no longer divided into a cell area and a wiring area, and cells can be formed on the entire surface of the semiconductor substrate, which reduces the degree of integration. It can be improved significantly.

Furthermore, since the intra-cell wiring and the inter-cell wiring are wired in different layers, an excessive load is not applied to the cells below the wiring, and all of the formed cells can be used. This also makes it possible to improve the degree of integration of the semiconductor device.

Furthermore, since cells are not divided into a cell area and a wiring area, and cells under the wiring can also be used, each cell can be freely connected.

Therefore, the degree of freedom in designing integrated circuits can be greatly increased.

Furthermore, each cell can be wired efficiently, which reduces the load on each cell.

[Brief explanation of drawings]

1 is a schematic configuration diagram showing an embodiment of the semiconductor device of the present invention; FIG. 2 is an enlarged view of essential parts showing a cell and an internal wiring layer of the semiconductor device of FIG. 1; The figure is an enlarged view of the main parts showing the cell interconnection layer of the semiconductor device of FIG. 1, FIG. 4 is a schematic configuration diagram showing an example of a conventional semiconductor device, and FIG. 5 is a diagram of the conventional semiconductor device. FIG. 3 is a schematic configuration diagram showing another example. ■Cell, 5... Wiring take-out terminal, 6... Wiring interconnection point, 7... Cell internal wiring layer, 8... Cell interconnection layer.

Claims (1)

[Claims] Wire extraction terminals are provided in a plurality of cells formed without any gaps on the entire surface of the semiconductor substrate, and wiring is formed between these wiring extraction terminals using a high melting point material in the upper layer of the cell to form an intra-cell wiring layer. A semiconductor device characterized in that a cell interconnection layer is formed by providing wiring interconnection points in a layer, and wiring between the interconnection interconnection points using a low electrical resistance material in a layer above the intra-cell interconnection layer.