JPH046409A - Photoelectric switch - Google Patents

Abstract

PURPOSE:To ensure the reliability of the display of the allowance of the amount of light by inhibiting the reset of a display state until the next period for judging the presence or absence of a body by an allowance-display setting circuit when the display state is set at the allowance state of the amount of the light during one period for judging the presence or absence of the body. CONSTITUTION:A body-presence judging circuit 6 judges the presence or absence of a body when reflected light R from an object X is higher than the lowest amount of light. An allowance judging circuit 7a judges the fact that there is allowance or there is no allowance, when the judged results as to whether the reflected light R exceeds the amount of the allowance light larger than the lowest amount of the light or not are equal by the specified number of times. An allowance-display setting circuit 7b sets the allowance display based on the result of the judgment of the circuit 6 and the result of the judgment of the circuit 7a. In the circuit 7b, the reset of the display state is inhibited until the next period for judging the presence or absence of the body, when the display state with a display means 9 is set in the allowance state of the amount of the light during one period for judging the presence or absence of the body. Therefore, the sufficient reliability and the stabilized display state are obtained in the judgment of the allowance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reflective photoelectric switch that detects the presence of an object to be detected by emitting and receiving a light beam.

[Prior Art] FIG. 4 shows a block diagram of a reflective photoelectric switch using a conventional triangulation method. In the figure, 1 is a light projecting means, which projects a light beam P onto an object X to be detected. The light projecting means 1 includes a light emitting element 1b made of a semiconductor laser or the like, and this light emitting element 1b is driven by a drive circuit 1a.

The drive circuit 1a supplies a drive current to the light emitting element 1b at a light emitting timing according to a clock pulse generated by a timing generation circuit 11.The light emitted from the light emitting element 1b is transmitted by a light emitting optical system 21 consisting of a convex lens. The light beam P is projected onto the detection area.

When the light beam P hits the detected object X within the detection area,
Generates reflected light R. This reflected light R is condensed by a light receiving optical system 22 made of a convex lens, and is received by a position detection element 3 arranged on the condensing surface. Light receiving optical system 2
2 and the position detection element 3 are arranged laterally at a predetermined distance from the light projecting means 1. The position detection element 3 is composed of, for example, a one-dimensional position detection element (PSD) or a split photodiode, and outputs position signals 1a and lb corresponding to the position of the focused spot. These position signals 1a and lb are contradictory signals.

An apparatus signal Ia composed of this position detection element 3.

1b is input to the arithmetic processing circuit 4. Based on the position signal faJb, the arithmetic processing circuit 4 determines whether the detected object X exists in a predetermined detection area, and also determines whether the amount of reflected light R is at a sufficient level. For this purpose, the arithmetic processing circuit 4 includes first and second light receiving circuits that amplify the position signals 12a and 1b, respectively, and first and second logarithmic circuits that logarithmically amplify the outputs V a and V b of each light receiving circuit, respectively. Output ff1n of the conversion circuit and each logarithmic conversion circuit
Vaj! A subtraction circuit that performs division isometrically by calculating the difference of nVb, and an output Nn(Va,・'
A first comparator circuit that compares Vb) with a first reference value Vr and an output 1nVa (or NnV
b) as the second and third reference values V r 2 , 'V'
It is provided with second and third comparison circuits that respectively compare r3. Here, the first reference value Vrl is the output ff1n of the subtraction circuit when the detected object exists at a predetermined position.
It corresponds to (Va/Vb). Therefore, the output of the first comparison circuit is an object presence/absence determination output for determining whether or not the detected object X exists in a predetermined detection area. Also,
The second reference value Vr2 corresponds to the minimum amount of reflected light R that makes it possible to determine the presence or absence of a detected object, and the third reference value
r3 corresponds to a margin light amount that is slightly larger than the minimum light amount. Therefore, the output D2 of the second comparison circuit is the reflected light R
The output D3 of the third comparison circuit is a margin light amount determination output for determining whether the reflected light R is larger than the margin light amount.

The output of this arithmetic processing circuit 4, D2. D3 is input to the logic operation circuit 10. The logic operation circuit 10 has first to third latches 5a to 5c that latch the outputs DD2 and Ds of the first to third comparison circuits in synchronization with the clock pulse output from the timing generation circuit 11, respectively. It is equipped with The first latch 5a latches the object presence/absence determination output D1, and the second latch 5b latches the minimum light amount determination output D2.

Therefore, by calculating the logical product of the outputs of the first and second latches 5a and 5b in the object detection and discrimination circuit 6, it is possible to obtain an object presence/absence discrimination result at a light reception level that ensures the SZN ratio. The result of this object presence/absence determination is outputted by the output circuit 8. Further, the third latch 5c latches the margin light amount determination output D3.

Therefore, based on the output of the object detection and discrimination circuit 6 and the output of the third latch 5C, it can be determined whether or not the object presence/absence discrimination result outputted from the output circuit 8 is a discrimination result based on the margin light amount. The margin display holding circuit 7 performs this margin determination. The margin determination result by the margin display holding circuit 7 is displayed by the margin display means 9. The margin display means 9 includes a display LED drive circuit 9a and a display LED 9b, and is controlled by the margin display holding circuit 7.

FIG. 5 shows a specific circuit example of the conventional logical operation circuit 10. The circuit configuration will be explained below.

First, the object presence/absence determination output from the arithmetic processing circuit 4 is input to the data input of the D flip-flop F1. The clock pulse T2 of the timing generation circuit 11 is input to the clock input C of the D flip-flop F1. The signal A obtained at the output Q of the D flip-flop F1 is input to one side of the AND circuit A1. This D flip-flop F1 constitutes the above-mentioned first latch 5a.

Next, the minimum light amount determination output D2 from the arithmetic processing circuit 4 is input to the data input of the D flip-flop F2. D flip-flop F2 glue lock human power C has
The clock pulse T3 of the timing generation circuit 11 is also input. The signal B obtained at the output Q of the D flip-flop F2 is used as the other input of the AND circuit A], and is also used as one input of the AND circuit A. This D flip-flop F2 constitutes the above-mentioned second latch 5b.

Next, the margin light amount determination output D3 of the arithmetic processing circuit 4 is input to the inverter 1, and its logic is inverted. Signal C output from inverter 1 is input to the other AND circuit A. Signal I output from AND circuit A4
is input to the data output of the D flip-flop F. The signal J output from the AND circuit A is input to the clock C of the D flip processor 1F.

The clock pulse T4 of the timing generation circuit 11 is input to one input of the AND circuit A.

The other input of the AND circuit A5 is an AND circuit #r A
A signal G output from s is input. These circuits constitute the margin display holding circuit 7 described above. In addition, the above-mentioned third
The latch 5c is configured as follows.

Next, the object detection discrimination circuit 6 includes ant circuit AA 2 ,
It includes A3 and D flip-flops F, , F5 and RS flip-flop F6. The signal outputted from the AND circuit A is input to one side of the AND circuit A6, and is also input to the data output of the D-free sop-flop 1F4. The signal E obtained from the output Q of the D flip-flop 1F4 is input to the other input of the AND circuit A6, and is also input to the data output of the D flip-flop F at the next stage. It is considered as one input. The other input of AND circuit A2 has D
A signal F obtained from the output Q of the flip-flop F5 is input. Each D flip-flop F,.

The clock pulse T of the timing generation circuit 11 is input to the clock input C of F5, and each inversion output port is input to the AND circuit A.

The outputs of the AND circuits A 2 and A:l are respectively input to the set input S and reset input R of the RSS flip processor 1F. And RS flip-flop F
Whether the signal H obtained from the output Q of 6 or the object presence/absence determination circuit 6
The output is

FIG. 6 is a time chart showing the operation of the logical operation circuit 10. Now, the latches 5a and 5b constituted by the D flip-flop FF2 receive the clock pulse T2. T,
The object presence/absence determination output D2 and the minimum light amount determination output D2 are respectively latched and stored.

Then, the object presence/absence judgment circuit 6 calculates the logical product of the object presence/absence judgment output D1 and the minimum light intensity judgment output D2 by the AND circuit A, and outputs the result to the clock pulse T,
The signal is input to a two-stage shift register consisting of flip-flops F, , F, and is shifted and stored based on the clock pulse T. The timing at which this data shift is performed is indicated by an arrow in the figure.

Next, in the AND circuit A2, each D flip flower 1F, .
The logical product of the output Q of F5 is taken and the RS flip-flop F
6 set manually, and the AND circuit A3 connects each D flip-flop F4. Take the logical product of the inverted output ports of F and get R
By manually resetting the SS flip floor 1F, R will be reset when the same detection state is obtained twice in a row.
The output of the S flip-flop F6 is inverted. Once, the signal H output from the RS flip-flop F6 was caused by the reflected light R exceeding the minimum light intensity to become S2.
This signal H is outputted via the output circuit 8.

On the other hand, the margin light amount determination output D3 is from the inverter 1. This inverted margin light amount determination output signal C,
Logical result I-(Bn
C) is calculated by AND circuit A. The logical product output (2) of the AND circuit A4 is input to the data output of the D flip-flop F3 for latching the margin light amount determination output.

In addition, the clock C of the D flip-flop F3 is
The AND circuit A6 calculates the logical product G=(DnE) of the signal output from the AND circuit A1 and the signal E obtained from the output Q of the D flip-flop F4 constituting the shift register, and outputs the logical product G. A pulse signal obtained by calculating the logical product J=(T, nG) of and clock pulse T in an AND circuit A5 is input. For this reason, both the data of DF1, F<, and Fs are
When it is determined that there is an object, the output of the antenna circuit A4 or the D flip-flop F3 is latched as a judgment result of the margin light amount at the timing of the clock pulse T4, and the margin display is displayed. It is used for holding. Therefore, when the determination result of "object presence" is obtained, the data for holding the margin display is updated.As a result, when the light amount is less than the margin light amount, the margin display is displayed regardless of whether or not an object is detected. The means 9 always displays a warning about the insufficient amount of light.

In the operation example shown in FIG. 6, in the first object presence detection state, the reflected light R is less than the margin light amount (but more than the minimum light amount), and the margin scene determination signal C is at the °'High" level. Therefore, when a detection output indicating that the object is present is obtained, the light emitting diode 9b of the margin display means 9 lights up to indicate that the reflected light R is below the margin light amount and that the light amount is insufficient.

Next, in the detection state of the second object "presence", the reflected light R is greater than the margin light amount, and since the light amount is sufficient, the margin light amount judgment result is "Low" level. In this case, when the object detection output is obtained, the light emission indicator 9b of the margin display means 9 is turned off to display that the reflected light R is greater than the margin light amount. In the case of the detection state of ", the margin display means 9 retains the previous display state, and the display state is updated to indicate that the object is present.
This is done only when a detection output of 1 is obtained, so the indication that the amount of light is insufficient is always displayed regardless of the time when the presence of an object is detected.

[Problems to be Solved by the Invention] In the above-mentioned conventional example, when the margin light amount determination results of the last two cycles in the period when the object presence/absence determination result is less than or equal to the margin light amount, the margin display means 9 Next, the insufficient amount of light is continuously displayed until the object presence/absence determination result indicates that an object is present. For this reason, for example, as shown in FIG. 7(a),
If the edges of the object X detected by the photoelectric switch KS are slanted in the direction of movement, or if the object X is uneven in the direction of movement, as shown in FIG. or, as shown in FIG. 7(c), if the edges of the object No matter how short the distance is, the insufficient light display may not disappear. This has led to doubts about the characteristics of the photoelectric switch, resulting in the problem that the original function of the photoelectric switch cannot be fully demonstrated. Further, even if the user understands that the margin display of the photoelectric switch has the above-mentioned characteristics, the problem of poor usability for the user cannot be solved.

The present invention has been made in view of the above points, and its purpose is to improve the reliability of the light amount margin display and ensure the stability of the display in a reflective photoelectric switch.

[Means for Solving the Problems] In order to solve the above problems, the photoelectric switch according to the present invention detects the presence of a detected object by emitting and receiving a light beam, as shown in FIG. In the reflective photoelectric switch to be detected, there is an object presence/absence determination circuit 6 that determines the presence or absence of an object when the reflected light is greater than or equal to the minimum light intensity, and a state in which the reflected light is greater than the minimum light intensity and continues for a predetermined period of time or more. A margin determination circuit 7a determines that the amount of light is in a surplus state when the reflected light is less than the margin light amount, and determines that the amount of light is insufficient when the reflected light is less than the margin light amount for a predetermined period of time; The display state of the display means 9 is set according to the determination result of the margin determination circuit 7a during the object presence determination period in which the presence of an object is determined by the object presence determination circuit 6. A margin display setting circuit 7b is provided, and when the display state of the display means 9 is set to the light amount margin state during one object presence determination period, the margin display setting circuit 7b resets the display state until the next object presence determination period. It is characterized by having a means for prohibiting.

[Function] As described above, in the present invention, the light amount surplus state is determined when the reflected light is greater than or equal to the minimum light amount, or continues for a predetermined period of time, and the reflected light is determined to be in the light amount surplus state when the reflected light is less than the margin light amount. Since the margin determination circuit 7a is provided, which determines that the light amount is insufficient when a certain state continues for a predetermined period of time or longer, sufficient reliability can be obtained in determining whether the light amount margin state or the light amount insufficient state is present. Therefore, when it is determined that the light quantity margin state is reached during one object presence determination period, the determination result may be trusted and the display state may be maintained until the next object presence determination period. Based on this idea, the margin display setting circuit 7b:
When the display state of the display means 9 is set to the light amount margin state during one object presence determination period, resetting of the display state is prohibited until the next object presence determination period.
A stable display state can be obtained regardless of the shape of the detected object.

[Example〕 FIG. 1 is a block diagram of one embodiment of the present invention.

In this embodiment, the margin display holding circuit 7 in the conventional example shown in FIG. 4 is replaced with a margin determination circuit 7a and a margin display setting circuit 7b, and other configurations are shown in FIG. This is the same as the conventional example shown. Here, the margin determination circuit 7a determines whether the margin is present or not when the determination result of whether or not the reflected light R5 exceeds the margin light amount which is larger than the minimum light amount is the same a certain number of times. This is a circuit that makes decisions.

Further, the margin display setting circuit 7b is a circuit that sets a margin display based on the determination result of the object presence/absence determination circuit 6 and the determination result of the margin determination circuit 7a.

FIG. 2 is a circuit diagram showing an example of the internal configuration of the logic operation circuit 10 in this embodiment. D flip flora 1F ,,F
2+F,,F, and RSS flip-flop F and AND circuit A,,A2. A and their connection relationships are the same as in the conventional example shown in FIG.

The circuit configurations of the margin determination circuit 7a and margin display setting circuit 7b will be described below.

The margin determination circuit 7a includes D flip-flops F, .
F, and RS flip-flop F, and AND circuit A,
7, consisting of As. The margin light amount determination output from the arithmetic processing circuit 4 is input to the data input of the D flip-flop F7. The signal M obtained from the output Q of the D flip-flop F is input to the data output of the next-stage L flip-flop F8, and is further input to one side of the AND circuit A7. The other input of the azide circuit A7 has a D flip-flop
A signal N obtained from the output Q of , is input. Each D
There is a timing generation port 1i'i! in the tarokk input C of the flip-flops F,,Fs. 11 clock pulse T,
is input, and each inverting output port is input to an AND circuit A8. The outputs of the AND circuits A 7 and As are input to the set power S and the reset power R of the RS flip-flop F, respectively.

Next, the margin display setting circuit 7b includes RS flip-flops F1, o, F2, D flip-flop F12, AND circuits A9, A1o, NAND circuits N, N2, and inverter 2. The signal H output from the object presence/absence determination circuit 6 is the input signal G of the margin display setting circuit 7b.
As such, it is input to the data output of the D flip-flop F12. The clock pulse T of the timing generation circuit 11 is input to the clock input C of the D flip-flop F12. This D flip flor rough F, 2
The signal Y obtained from the output Q of is input to the inverter 2, and is also input to one of the nil 1 to circuit N1 and the ant circuit A1o. The other input of the NAND circuit N receives the signal X obtained from the output Q of the RS flip 70 in the margin determination circuit 7a. Also, AND circuit A. The other input of is inputted to the inverting output port of the RSS flip-flop F in the margin determination circuit 7a. The output signal Z of AND circuits A and 0 is RS
It is input to the flip-flop F and the glue setting manual R. The output signal U of the NAND circuit N is input to one side of the NAND circuit N2. A reset signal R8T is input to the other input of the NAND circuit N2. The output signal Q of the NAND circuit N2 is input to the reset input R of the RS flip-flop Flo. Next, inverter r
The output of 2 is used as one input of AND circuit A.

The clock pulse T4 of the timing generation circuit 11 is input to the other input of the AND circuit A. The output signal P of the AND circuit A is input to the set signal S of the RS flip-flop Flo. The signal W obtained at the inverted output q of the RS flip-flop Flo is input to the set input S of the RS flip-flop F. The signal obtained at the output Q of the RSS flip-flop F1 is output to the margin display means 9 as the output of the margin display setting circuit 7b.

The operation of this embodiment will be explained below. The object presence/absence determination output D1 and minimum light amount determination output D2 obtained from the arithmetic processing circuit 4 are latched by D flip-flops Fl and F2, respectively, in synchronization with clock pulses T2 and T3. In the object presence/absence determination circuit 6, the AND circuit A1 calculates the logical product of the object presence/absence determination output and the minimum light amount determination output, and the result is synchronized with the clock pulse T1 to be output to a two-stage circuit consisting of D flip-flops F4 and F5. input into the shift register and store it. Then, the AND circuit A2 takes the logical product of each output Q to obtain the set power S of the RSS flip-flop F, and the AND circuit A3 takes the logical product of each inverted output Ω to obtain the reset power R of the RSS flip-flop F. By doing so, when the same discrimination state is obtained twice in succession, the object presence/absence discrimination result can be obtained as the output of the RSS flip-flop F.

Next, the operation of the margin determination circuit 7a will be explained. First, the surplus light amount determination output D3 is input to and stored in a two-stage shift register consisting of D flip-flops F t and F s in synchronization with the clock pulse T1. Then, the AND circuit A7 takes the AND of each output Q to set the RS flip-flop F, and sets the RS flip-flop F, and the AND circuit As takes the AND of each inverted output q to set the RS flip-flop F. By setting R, the same discrimination state is 2
RS flip-flop F when obtained times in succession.

The light amount margin determination result is obtained as the output. When there is a margin "°°, the output Q of the RS flip-flop F is "
It becomes "High" level.

Next, the operation of the margin display setting circuit 7b will be explained.

This circuit sets the margin display state using the object presence/absence determination result and the margin determination result. The object presence/absence determination result is “object”
When there is a power output, the output Q of the D flip-flop F6 is "')
This signal is input to the D flip-flop F12, and its output Q is the clock pulse T.
It becomes "'High" level in synchronization with 5. On the other hand, when the object presence/absence determination result indicates that the object is present and the margin determination result indicates that the margin is present, the output signal U of the NAND circuit N1 is
The NAND circuit N2 calculates the logical product of this signal U and the reset signal R3T, which becomes the High level after a certain period of time after power-on. Since Q becomes 'High' level, RS flip-flop F,. When the RS flip-flop F and 1 are set, the set force S of the RS flip-flop F and 1 becomes 'High' level, and the RSS flip-flop F and 1 are set to the 'High' level.
．． The output Q becomes 'High' level.

Next, when the object presence/absence determination result becomes "No object", the output Q of the D flip-flop F12 becomes "LOLll" level in synchronization with the clock pulse T5, and the output of 1 to the NAND circuit becomes High regardless of the margin determination result. '' level, the output of NAND circuit N2 is 'Loud' level, the output of Ant circuit Alo is 'Low' L=Hell, the output of inverter ■2 is '°') Iigh' level, and clock pulse T is enabled. The RS flip-flop F is set by the clock pulse T4, that is, the clock pulse T,
is valid only when the object presence/absence determination result is that there is no object. At this time, the inverting output port of the R, S flip-flop F1o is "Low", and the reset human power S is in accordance with the clock pulse T4, the reset human power R is at the "Low" level, and the output Q of the RS flip-flop F1 is held. Therefore, the output of the RS flip-flop F,1 is valid until the next time the object presence/absence determination result becomes "object present" and the output of the D flip-flop F9 is made valid via the NAND circuit N or the AND circuit A1. holds the object presence/absence determination result or the state when the object is present.

Then, when the next object presence/absence determination result shows that the object is present, if the margin determination result is "no margin", the output of the ant circuit A1o is at the 'Higb' level, and the output of the NAND circuit N2 is remains at the "'Lou" level, so
As the final output, the output Q of RSS flip Flora 1F is “
'LOII+' level.Furthermore, when the object presence/absence determination result indicates that the object is present, the output of the NAND circuit N is at the 'Low' level.
Since the output of the NAND circuit N2 becomes "High" level, the output Q of the RS flip-flop FII is used as the final output.
becomes "HIGH" level.

Next, during the period in which the object presence/absence determination result, which is a feature of the present invention, indicates that the object is present, first, the state starts with no margin, then remains in the state with margin for a certain period of time, and then again. Returning to the “no margin” state, the object presence/absence determination result is “no object”
The operation when this happens will be explained.

Ant circuit A when there is no margin. The output of F becomes “High” level, and the RS flip-flop F
The output Q of is at the "LolI+" level. After that, when the state becomes "with margin", the output of the NAND circuit N becomes "Lo".
The output of the revenand circuit N2, which is u+level, is “'H1g.
Since the RS flip-flop F10 has a high level, the inverting output port of the RS flip-flop F10 becomes a high level, and the final output Q of the RS flip-flop F I+ becomes a high level. After this, the state returns to the state with no margin, and the AND circuit A
Even if the output of 10 becomes "'High" level, the set input S of RS flip-flop F Io remains at "Low" level, and the reset input R goes "'High".
Since the level only changes from the level to 'Low', the inverted output q of the RS flip-flop F10 does not change and remains at 'High' level.
S flip-flop Fll set human power S is “'High
h"" level remains, and the reset input R is "Low".
Since it only changes from "level" to "High" level, the final output Q of RS flip-flop F I+
does not change and maintains the "'High" level output.

Therefore, the object presence/absence determination result shifts to the "no object" state while the margin state is "presence".

FIG. 3 is a time chart showing the operation of the logic operation circuit 10 of this embodiment. Note that the operation for determining the presence or absence of an object is the same as in the conventional example, so a description thereof will be omitted. Masu,
The initial object presence determination period ■ has a margin of ``
Since it is in a valid state, there is no problem with its operation. Next object °“
During the "existence" determination period, there are two consecutive "existence" states and one time "no margin" state, and the display of "no margin" is performed as a margin display in the object "existence" determination period. There is no.The next object “presence” judgment period is four times for the margin “no” condition and two times for the margin “presence” condition. The ``display'' is carried out for one period, and then the ``margin'' state continues twice, so the margin display changes to the ``margin'' present display and is maintained until the next object'' determination period. During the next object determination period, there are two consecutive states of "no margin" and one time of "existence of margin", and in this case,
The margin display becomes "no margin" and is maintained until the next object presence determination period. In this way, it will not become effective unless the state of "with margin" continues twice.The next period for determining whether the object is present is either in the state of "no margin" or twice, followed by the state of "with margin" twice. times, so in this case, the margin display will be "existence", and the next object "existence" will be displayed.
will be retained until

[Effects of the Invention] As described above, in the present invention, in a reflective photoelectric switch that transmits and receives a light beam to detect the presence of an object to be detected, it is possible to emit a margin of light larger than the minimum light amount of the reflected light. When the judgment result of whether or not to exceed the limit remains the same for a certain period of time,
Since the light amount surplus state or the light amount insufficient state is determined, sufficient reliability can be obtained for determining the margin of reflected light amount, and moreover, it is determined that the reflected light is larger than the minimum light amount and an object is present. The display state of the display means is set according to the margin determination result of the amount of reflected light during the object existence period, and when the display state of the light amount surplus state is set during one object existence period, the display state of the display means is set during the next object existence period. Since resetting the display state was prohibited until now, the margin display of reflected light amount is stable regardless of the shape of the detected object, and the display is easy to see and highly reliable for the user. effective.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a specific circuit diagram of the main parts of the above, Fig. 3 is a time chart showing the operation of the above, Fig. 4 is a block diagram of a conventional example, and Fig. 5 is a block diagram of an embodiment of the present invention. The figure is a specific circuit diagram of the main part of the same as above, FIG. 6 is a time chart showing the operation of the same as above, and FIGS. 7(a) and (b). (c) is an explanatory diagram for explaining the problems of the conventional example. 7a is a margin determination circuit, and 7b is a margin display setting circuit.

Claims (1)

[Claims] (1) In a reflective photoelectric switch that detects the presence of a detected object by emitting and receiving a light beam, it includes an object presence/absence determination circuit that determines the presence or absence of an object when the reflected light is at least the minimum amount of light; A margin determination circuit that determines a light amount surplus state when a state where the light amount is greater than the margin light amount continues for a predetermined time or more, and determines a light amount insufficient state when a state where the reflected light is less than the margin light amount continues for a predetermined time or longer. and a display means for displaying whether the light amount is in a sufficient light amount state or in a light amount insufficient state; and a margin display setting circuit that sets a display state of the display means to a light amount margin state, and the margin display setting circuit sets a display state of the display means to a light amount margin state during one object existence determination period.
A photoelectric switch characterized by comprising means for prohibiting resetting of a display state until the next object presence determination period.