JPH0463653U - - Google Patents
Info
- Publication number
- JPH0463653U JPH0463653U JP1990107333U JP10733390U JPH0463653U JP H0463653 U JPH0463653 U JP H0463653U JP 1990107333 U JP1990107333 U JP 1990107333U JP 10733390 U JP10733390 U JP 10733390U JP H0463653 U JPH0463653 U JP H0463653U
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- semiconductor device
- spiral
- showing
- sectional
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990107333U JPH0463653U (enExample) | 1990-10-12 | 1990-10-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990107333U JPH0463653U (enExample) | 1990-10-12 | 1990-10-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0463653U true JPH0463653U (enExample) | 1992-05-29 |
Family
ID=31853797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990107333U Pending JPH0463653U (enExample) | 1990-10-12 | 1990-10-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0463653U (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7414506B2 (en) | 2003-12-22 | 2008-08-19 | Nec Electronics Corporation | Semiconductor integrated circuit and fabrication method thereof |
-
1990
- 1990-10-12 JP JP1990107333U patent/JPH0463653U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7414506B2 (en) | 2003-12-22 | 2008-08-19 | Nec Electronics Corporation | Semiconductor integrated circuit and fabrication method thereof |