JPH0463005A - Automatic gain controller - Google Patents

Automatic gain controller

Info

Publication number
JPH0463005A
JPH0463005A JP17259590A JP17259590A JPH0463005A JP H0463005 A JPH0463005 A JP H0463005A JP 17259590 A JP17259590 A JP 17259590A JP 17259590 A JP17259590 A JP 17259590A JP H0463005 A JPH0463005 A JP H0463005A
Authority
JP
Japan
Prior art keywords
amplifier
signal
memory
histogram
automatic gain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17259590A
Other languages
Japanese (ja)
Inventor
Shigeyuki Uzawa
繁行 鵜澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP17259590A priority Critical patent/JPH0463005A/en
Publication of JPH0463005A publication Critical patent/JPH0463005A/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To reduce the influence of a pulsative single noise and to improve an S/N by controlling the amplification factor and offset of an amplifier based on the mean value and dispersion of an input signal. CONSTITUTION:The output signal OUT of the amplifier 2 is converted to a digital signal at an A/D converter 4, and is sent to a read only memory 5 as an address signal. An adder 7 adds one on data at the correspondent address of histogram memory 6 at every access to the histogram memory 6 by the read only memory 5. Such operation is repeated for a constant period decided in advance. A mean and dispersion detector 8 finds mean and dispersion from the histogram of the histogram memory 6, and multiplies them by a coefficient set in advance and sends them to the amplifier 2 as an offset control signal S and an amplification factor control signal G, respectively. Thereby, the S/N resistant for the pulsative noise can be obtained.

Description

【発明の詳細な説明】 [産業上の利用分野コ 本発明は、計測器等電気回路一般における自動ゲイン制
御装置に関し、特にビデオ信号の自動ゲイン制御装置に
関係する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an automatic gain control device for electrical circuits such as measuring instruments in general, and particularly to an automatic gain control device for video signals.

[従来の技術] 従来の自動ゲイン制御は、人力信号の最大値(Vmax
)と、最小値(Vmin )を調べて、増巾器へ下式の
ようなフィードバック信号gを送ることによって行われ
ていた。
[Prior art] Conventional automatic gain control is based on the maximum value of the human input signal (Vmax
) and the minimum value (Vmin), and send a feedback signal g as shown in the following formula to the amplifier.

[発明が解決しようとしている課題] しかしながら、このような従来技術によれば、第2図(
a)に示すようなパルス性のノイズによって入力信号の
最大値V maxもしくは最小値V minの計測値が
変動し、これが自動ゲイン制御の誤動作の原因となって
いた。
[Problems to be Solved by the Invention] However, according to such prior art, the problem as shown in FIG.
The measured value of the maximum value V max or minimum value V min of the input signal fluctuates due to pulse noise as shown in a), which causes malfunction of automatic gain control.

本発明の目的は、この従来技術の問題点に鑑み、自動ゲ
イン制御装置において、対ノイズ性を向上させ、パルス
性のノイズによって誤動作しないようにすることにある
In view of the problems of the prior art, an object of the present invention is to improve noise resistance in an automatic gain control device and prevent malfunctions caused by pulse noise.

[課題を解決するための手段] 上記目的を達成するため本発明では、増幅器の出力信号
に基づき増幅器のゲイン制御を行なう自動ゲイン制御装
置において、増幅器の出力信号に基づきその平均と分散
を表わす信号を出力する回路を備え、その平均と分散を
表わす信号を用いて増幅器のゲイン制御を行なうように
している。
[Means for Solving the Problems] In order to achieve the above object, the present invention provides an automatic gain control device that performs gain control of an amplifier based on an output signal of the amplifier. The amplifier is equipped with a circuit that outputs a signal representing the average and variance of the signal, and is used to control the gain of the amplifier.

[作用コ この構成においては、増幅器の出力信号の平均値と分散
の二つの統計量を基にして、増幅器の増幅率とオフセッ
トを制御するようにしたため、パルス性の単発ノイズの
影響を受けることが少なく、したがって、このようなノ
イズによる誤動作なしにゲイン制御が行なわれる。
[Effects] In this configuration, the amplification factor and offset of the amplifier are controlled based on the two statistics of the average value and variance of the output signal of the amplifier, so it is not affected by single-shot pulse noise. Therefore, gain control is performed without malfunctions caused by such noise.

[実施例コ 以下、図面を用いて本発明の詳細な説明する。[Example code] Hereinafter, the present invention will be explained in detail using the drawings.

第1図は本発明の一実施例に係る自動ケイン制御装置を
含むブロック図である。図中、1は自動ケイン制御装置
、2は増幅器、3は信号処理装置であり、自動ケイン制
御装置1は増幅器2の出力信号OUTに基づきフィード
バック信号S、Gを増幅器2に出力して増幅器2のゲイ
ン制御を行ない、制御された増幅器2の出力か信号処理
装置3に出力されるようになっている。
FIG. 1 is a block diagram including an automatic cane control device according to an embodiment of the present invention. In the figure, 1 is an automatic cane control device, 2 is an amplifier, and 3 is a signal processing device.The automatic cane control device 1 outputs feedback signals S and G to the amplifier 2 based on the output signal OUT of the amplifier 2. Gain control is performed, and the controlled output of the amplifier 2 is output to the signal processing device 3.

4は増幅器2の出力アナログ信号をデジタル化するA/
D変換器、5はA/D変換器4からのデジタル信号をア
ドレスとする読出し専用メモリ、6は読出し専用メモリ
5の出力に基づくヒストグラムを格納するヒストグラム
メモリ、7はヒストグラムメモリ6のヒストグラムの計
算をするための加算器、8はヒストグラムメモリ6のヒ
ストグラムから平均・分散を計算し、増幅器2に指令信
号を送る平均・分散検出器である。
4 is an A/ that digitizes the output analog signal of amplifier 2;
A D converter, 5 is a read-only memory whose address is the digital signal from the A/D converter 4, 6 is a histogram memory that stores a histogram based on the output of the read-only memory 5, and 7 is a histogram calculation in the histogram memory 6. The adder 8 is an average/variance detector that calculates the average/variance from the histogram in the histogram memory 6 and sends a command signal to the amplifier 2.

この構成において、第2図に示すような入力信号INは
増幅器2で適切なレベルまで増幅され、信号処理装置3
に送られる。その際、自動ゲイン制御装置1は、増幅器
2の増幅レベルを最適化する。
In this configuration, an input signal IN as shown in FIG. 2 is amplified to an appropriate level by an amplifier 2, and a signal processing device 3
sent to. At this time, the automatic gain control device 1 optimizes the amplification level of the amplifier 2.

自動ゲイン制御装置1においては、増幅器2の出力信号
OUTは、A/D変換器4においてデジタル信号に変換
され、アドレス信号として読出し専用メモリ5に送られ
る。これによって読み出される読出し専用メモリ5のデ
ータはヒストグラムの階級値であり、ヒストグラムメモ
リ6へのアドレスとなる。このようにして読出し専用メ
モリ5がヒストグラムメモリ6をアクセスする毎に、加
算器7は、ヒストグラムメモリ6の対応するアドレスの
データに+1だけ加算する。そして、上記動作をあらか
じめ定められた一足期間内繰り退すことによって、第2
図(b)に示すようなヒストグラムがヒストグラムメモ
リ6内に作成される。
In the automatic gain control device 1, the output signal OUT of the amplifier 2 is converted into a digital signal by the A/D converter 4 and sent to the read-only memory 5 as an address signal. The data read from the read-only memory 5 by this is the class value of the histogram, and becomes the address to the histogram memory 6. Each time the read-only memory 5 accesses the histogram memory 6 in this way, the adder 7 adds +1 to the data at the corresponding address in the histogram memory 6. Then, by reversing the above operation within a predetermined period of time, the second
A histogram as shown in FIG. 6(b) is created in the histogram memory 6.

そして、平均・分散検出器8は、ヒストグラムメモリ6
のヒストグラムから、平均および分散を求め、それらに
あらかじめ設定された係数を乗じてそれぞれオフセット
制御信号Sおよび増幅率制御信号Gとして増幅器2へ送
る。
Then, the mean/variance detector 8 includes a histogram memory 6
The average and variance are obtained from the histogram, multiplied by a preset coefficient, and sent to the amplifier 2 as an offset control signal S and an amplification factor control signal G, respectively.

本実施例によれば、■信号の分散値を増幅器へのフィー
ドバックとしているため、パルス性のノイズに強い。ま
たヒストグラム上で頻度か小さいもの、あるいは分布か
ら大きく外れたものを異常値として簡単に除去可能であ
る。■信号処理装置3か、デジタル信号処理装置である
場合には、A/D変換器等の多くの部分を自動ケイン制
御装置と共用することか可能である。さらに、■自動ケ
イン制御装置1は増幅率の制御のみならず、オフセット
電圧の制御も同時に可能である。
According to this embodiment, (1) the dispersion value of the signal is used as feedback to the amplifier, so it is resistant to pulse noise. Furthermore, it is possible to easily remove values with low frequency on the histogram or values that deviate greatly from the distribution as abnormal values. (2) If the signal processing device 3 is a digital signal processing device, it is possible to share many parts such as an A/D converter with the automatic cane control device. Furthermore, (1) the automatic cane control device 1 is capable of controlling not only the amplification factor but also the offset voltage at the same time.

[他の実施例] 上述実施例においてはA/D変換を伴なっているが、A
/D変換をせずにすへてアナログ回路で処理する手法も
考えられる。第3図はアナログ回路による実施例を示す
。ここで必要とする信号波形の分散と平均は下記式(1
)および(2)で表わすことができる。
[Other Embodiments] Although the above embodiments involve A/D conversion,
It is also possible to consider a method in which processing is performed entirely by an analog circuit without performing /D conversion. FIG. 3 shows an embodiment using an analog circuit. The variance and average of the signal waveform required here are expressed by the following formula (1
) and (2).

(平均) (分散) ・ ・ (2) 第3図は、これらの式を演算増幅器を用いて実現した回
路を示すものである。
(Average) (Variance) (2) FIG. 3 shows a circuit that implements these equations using an operational amplifier.

式(1)はゲート回路32、積分器33、掛算器34お
よび係数回路35を直列に接続した回路によって実現さ
れ、この回路を経て増幅器2の出力信号OUTは増幅器
■へのオフセット制御信号Sとなる。
Equation (1) is realized by a circuit in which a gate circuit 32, an integrator 33, a multiplier 34, and a coefficient circuit 35 are connected in series, and the output signal OUT of the amplifier 2 is passed through this circuit to the offset control signal S to the amplifier ■. Become.

式(2)は、ケート回路32、掛算器36、積分器37
、加算器38(ここでは減算器として用いている)、お
よび係数回路39を直列に接続し、かつ掛算器34の出
力を加算器38の(−)端子へ入力させることによって
実現され、増幅器2の出力信号01JTはこの回路を経
て増幅器2へのゲイン制御信号Gとなる。
Equation (2) consists of a gate circuit 32, a multiplier 36, and an integrator 37.
, an adder 38 (here used as a subtracter), and a coefficient circuit 39 are connected in series, and the output of the multiplier 34 is input to the (-) terminal of the adder 38. The output signal 01JT becomes the gain control signal G to the amplifier 2 through this circuit.

[発明の効果コ 以上説明したように本発明によれば、人力信号の平均値
と分散を基にして増幅器の増幅率とオフセットを制御す
るようにしたため、パルス性の単発ノイズの影響を受け
ることが少なく、対ノイズ性が向上する。
[Effects of the Invention] As explained above, according to the present invention, since the amplification factor and offset of the amplifier are controlled based on the average value and variance of the human input signal, it is possible to avoid the influence of pulsed single-shot noise. This reduces noise and improves noise resistance.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明を実施した自動ゲイン制御装置を含む
回路のブロック図、 第2図(a)および(b)は、第1図の装置における人
力信号例を時間変化およびヒストグラムとで示したグラ
フ、そして 第3図は、本発明の他の実施例に係る自動ゲイン制御装
置を含む回路のブロック図である。 1:自動ゲイン制御回路、2:増幅器、3:信号処理装
置、4 : A/D変換器、5:a出し専用メモリ、6
:ヒストグラムメモリ、7:加算器、8:平均・分散検
出器、32:ゲート回路、33:積分器、34:掛算器
、35:係数回路、36:掛算器、37;積分器、38
:加算器、39:係数回路。 特許田願人
FIG. 1 is a block diagram of a circuit including an automatic gain control device embodying the present invention, and FIGS. 2(a) and (b) show examples of human input signals in the device of FIG. 1 as time changes and histograms. FIG. 3 is a block diagram of a circuit including an automatic gain control device according to another embodiment of the present invention. 1: automatic gain control circuit, 2: amplifier, 3: signal processing device, 4: A/D converter, 5: memory dedicated to a output, 6
: Histogram memory, 7: Adder, 8: Average/variance detector, 32: Gate circuit, 33: Integrator, 34: Multiplier, 35: Coefficient circuit, 36: Multiplier, 37; Integrator, 38
: Adder, 39: Coefficient circuit. patent applicant

Claims (1)

【特許請求の範囲】[Claims] (1)増幅器の出力信号に基づき増幅器のゲイン制御を
行なう自動ゲイン制御装置であって、増幅器の出力信号
に基づきその平均と分散を表わす信号を出力する回路を
備え、その平均と分散を表わす信号を用いて増幅器のゲ
イン制御を行なうようにしたことを特徴とする自動ゲイ
ン制御装置。
(1) An automatic gain control device that controls the gain of an amplifier based on the output signal of the amplifier, and includes a circuit that outputs a signal representing the average and variance of the output signal of the amplifier, and a circuit that outputs a signal representing the average and variance of the output signal of the amplifier. An automatic gain control device characterized in that the gain control of an amplifier is performed using the following.
JP17259590A 1990-07-02 1990-07-02 Automatic gain controller Pending JPH0463005A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17259590A JPH0463005A (en) 1990-07-02 1990-07-02 Automatic gain controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17259590A JPH0463005A (en) 1990-07-02 1990-07-02 Automatic gain controller

Publications (1)

Publication Number Publication Date
JPH0463005A true JPH0463005A (en) 1992-02-28

Family

ID=15944764

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17259590A Pending JPH0463005A (en) 1990-07-02 1990-07-02 Automatic gain controller

Country Status (1)

Country Link
JP (1) JPH0463005A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006524939A (en) * 2003-04-28 2006-11-02 コアオプティックス・インコーポレイテッド Amplification adjustment method and circuit
WO2006115254A1 (en) * 2005-04-25 2006-11-02 Matsushita Electric Industrial Co., Ltd. Automatic gain control circuit and signal reproducing device
JP2013172288A (en) * 2012-02-21 2013-09-02 Renesas Electronics Corp Control device, digitally controlled power supply and control method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5679511A (en) * 1979-12-04 1981-06-30 Ricoh Co Ltd Automatic gain control circuit
JPS63302679A (en) * 1987-06-03 1988-12-09 Nippon Hoso Kyokai <Nhk> Video signal level control system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5679511A (en) * 1979-12-04 1981-06-30 Ricoh Co Ltd Automatic gain control circuit
JPS63302679A (en) * 1987-06-03 1988-12-09 Nippon Hoso Kyokai <Nhk> Video signal level control system

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006524939A (en) * 2003-04-28 2006-11-02 コアオプティックス・インコーポレイテッド Amplification adjustment method and circuit
WO2006115254A1 (en) * 2005-04-25 2006-11-02 Matsushita Electric Industrial Co., Ltd. Automatic gain control circuit and signal reproducing device
JPWO2006115254A1 (en) * 2005-04-25 2008-12-18 松下電器産業株式会社 Automatic gain control circuit and signal reproducing apparatus
JP4623677B2 (en) * 2005-04-25 2011-02-02 パナソニック株式会社 Automatic gain control circuit and signal reproducing apparatus
US7894312B2 (en) 2005-04-25 2011-02-22 Panasonic Corporation Automatic gain control circuit and signal reproducing device
JP2013172288A (en) * 2012-02-21 2013-09-02 Renesas Electronics Corp Control device, digitally controlled power supply and control method

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