JPH0461318A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce the characteristic fluctuation of a semiconductor device by crystallizing an amorphous semiconductor by utilizing solid phase growth by repeating short-time heat treatment on an amorphous semiconductor film for several times, with each heat treatment being shorter in time than the latent period of the solid phase growth. CONSTITUTION:After a desired element area is formed in a p-type silicon substrate 20, an oxide and polycrystalline silicon films 21 and 22' are successively formed on the substrate by CVD methods. At the time of forming the films 21 and 22', small holes are formed through the silicon film 21 so that the polycrystalline silicon film 22' can come into contact with the substrate 20 and the contact areas are used as seed crystals. The silicon ions are implanted twice under such conditions that the accelerating voltages are respectively set at 50keV and 120keV and the dozing quantities are respectively set at 2.5X10<15>cm<-2> and 5.4X10<15>cm<-2>. Thereafter, the amorphous silicon film 22 thus formed is repeatedly heated to 610 deg.C for 10 hours each and a recrystallized polycrystalline silicon film 23 is obtained.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly relates to a semiconductor device and a method for manufacturing the same.
The present invention relates to a semiconductor device having a tor) structure.

(Prior Art) As semiconductor devices become more highly integrated, the miniaturization of elements continues to progress, and the limits of integration are now being reached. Therefore, there is a need for a method of increasing the degree of integration by vertically overlapping some elements.

Therefore, a so-called Sol structure in which elements are formed within a semiconductor thin film formed on the surface of a substrate with an insulating film interposed therebetween has become widely used. This structure has the advantage that it is easy to separate elements from the substrate, and is an effective technique.

Conventionally, semiconductor devices with such a Sol structure have been manufactured using a method in which an amorphous silicon film formed on an insulating film is grown in a solid phase as a single crystal or a polycrystalline film with large crystal grains through heat treatment, and a semiconductor element is formed within this film. It is completely formed by

(Problems to be Solved by the Invention) However, in this conventional method, crystal growth from a seed crystal often does not grow long and becomes polycrystalline.

For this reason, even when used as a polycrystal, the size of crystal grains varies, resulting in variations in device characteristics, which has been a major hindrance when these devices are combined to operate as a system.

Furthermore, in solid-phase growth using amorphous silicon deposited by the conventional CVD method, many crystal nuclei are generated at the amorphous silicon/insulating film interface, making it difficult to form a polycrystalline film with a sufficiently large grain size. there were.

An object of the present invention is to reduce variations in characteristics and form a highly reliable semiconductor device.

[Structure of the invention]

(Means for Solving the Problems) Therefore, in the first aspect of the present invention, an amorphous semiconductor film is solidified by repeating a plurality of short-time heat treatments, each time shorter than the latent time of solid phase growth. The amorphous semiconductor is crystallized by phase growth.

In the second aspect of the present invention, an amorphous semiconductor film is deposited on an insulating film, and ions of the same material as the semiconductor are implanted so as to reach the vicinity of the interface between the amorphous semiconductor film and the insulating film, and then The amorphous semiconductor is crystallized by solid-phase growth by performing heat treatment for a shorter time than the average time.

In the third aspect of the present invention, the maximum grain size of the crystal grains of the semiconductor thin film formed by the in-phase growth method is set to be one-half or less and one-tenth or more of the channel length of the semiconductor element formed in this thin film. I am trying to adjust it accordingly.

(Function) According to the first aspect of the present invention, by performing heating multiple times,
Since growth is performed little by little, any desired crystal size can be obtained without being hindered by random nucleation.

When crystallization occurs through solid phase growth, there is a preparation time called latent time before crystal nuclei are generated.

If the heat treatment is stopped within this time, new crystal nuclei will not be generated. Therefore, by repeating heat treatment shorter than this latent time, only the growth of existing crystal grains is promoted while preventing the generation of crystal nuclei, preventing the generation of unnecessary crystal nuclei, and promoting only the necessary crystal growth.

In addition, if a seed crystal exists, the heating time each time should be less than or equal to the latent time, and if there is no seed crystal, the heating time should initially be longer than the latent time to form a seed crystal. do.

Furthermore, if the material is rapidly cooled after heating, the crystal nuclei that have begun to form will become quenched (quickly frozen), and there is a possibility that they will become crystal nuclei during the next heating. However, by gradually cooling the amorphous semiconductor film at a cooling rate that returns the state of the non-crystalline region to the state before the heat treatment, it is possible to eliminate the source of the crystal nuclei that have begun to form. Good crystal growth can be achieved.

Furthermore, by adding impurities such as phosphorus, the same effect can be obtained even if the slow cooling rate is increased.

According to the second method of the present invention, an amorphous semiconductor is formed on an insulating film, and ions of the same material as the semiconductor are implanted near the amorphous semiconductor/insulating film interface. The generation of crystal grains near the interface could be suppressed, and a polycrystalline film with large grain size could be formed. Note that by reducing the dose amount, it is possible to suppress the incorporation of impurities.

According to the third semiconductor device of the present invention, since the semiconductor element is formed such that the crystal grain size of the semiconductor thin film is one-half or less of the channel length, the number of grain boundaries in the channel length direction varies. In addition, since it is set to one-tenth or more, it is possible to prevent the mobility from being significantly reduced due to too many grain boundaries.

Furthermore, if the thickness of this semiconductor thin film is 0.1 μl or less, it is possible to suppress a decrease in mobility and improve device characteristics.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Example 1 Figure 1 is an explanatory diagram showing the solid phase growth method of the embodiment of the present invention, and Figures 2(a) to 2(d) are recrystallized polycrystals using in-phase growth of the embodiment of the present invention. FIG. 3 is a process diagram showing a method of forming a silicon thin film.

First, as shown in FIG. 2(a), a p-type silicon substrate 2
After forming a desired element region within 0.0 nm, a silicon oxide film 21 is deposited by the CVD method, and a polycrystalline silicon film 22' having a thickness of 2000 nm is deposited on top of this by the CVD method.

At this time, a small hole is formed in the silicon oxide film 2 by RIE, the p-type silicon substrate 20 is brought into contact with the polycrystalline silicon film 22', and this region is used as a seed crystal.

As shown in FIG. 2(b), the acceleration voltage is 50 keV.
, dose amount 2, 5 x i O15C12, acceleration voltage 120 keV, dose amount 5, 4 x 1. O"
An amorphous silicon film 22 is formed by implanting silicon ions twice at cm-2.

Next, as shown in FIG. 2(C), this amorphous silicon film 22 was repeatedly heated at 610° C. for 10 hours as shown in the heating profile shown in FIG.
), a recrystallized polycrystalline silicon 23 is obtained.

This heat treatment was repeated several to several thousand times until the amorphous portion disappeared.

The recrystallized polycrystalline silicon thus formed had extremely good crystal properties.

This means that one heating time (10 hours) is the latent time (12 hours).
(time) or less, crystal growth progresses from the seed part where crystals already exist, and only crystal nuclei are formed in the amorphous part where there are no seeds.

When the temperature is slowly lowered, the crystals that have already grown remain intact, while the nuclei that have begun to grow disappear.

When the temperature is raised again, crystal growth occurs from the crystallized parts, and crystal nuclei begin to form in the amorphous parts.

Then, if the temperature is lowered again within the latent time, only the growth remains and the original nucleus disappears.

By repeating this process, crystal growth from the seed part can be extended for a long time.

Next, in order to measure the relationship between the length of one heating time and the length of the crystal part extending from the seed part (lateral self-growth 10 growth distance), we changed the heating time of one time and The lateral in-phase growth distance when the heat treatment was repeated until the portion disappeared was determined as M1. The material used is exactly the same as in the previous embodiment. After forming a desired element region in a p-type silicon substrate as shown in FIG. 2(a), a silicon oxide film is deposited by the CVD method, and the upper layer A polycrystalline silicon film with a thickness of 2000 μm was deposited using the CVD method, and an accelerating voltage of 50 μm was applied.
keV, dose amount 2. 5 x 1015 am-2, acceleration voltage 120 k, eV, dose 5. 4 x
] An amorphous silicon film 22 was formed by implanting silicon ions twice at 015 cm -2 , and the other conditions were exactly the same as in the previous example.

The results are shown in FIG.

As is clear from Fig. 3, the incubation time at this temperature (610°C) is about 12 hours, or if the heating time for one time becomes less than this incubation time, the lateral solid phase growth distance suddenly increases. It can be seen that it stretches and reaches lOμ-. Conventionally, when heated once (700° C. for 5 hours), it was about 2 μ-.

Example 2 Next, as a second example of the present invention, solid phase growth without using a seed crystal will be described.

In exactly the same manner as in the previous embodiment, after forming a desired element region in a p-type silicon substrate as shown in FIG. 2(a),
A silicon oxide film is deposited by the CVD method, and C is deposited on this upper layer.
A polycrystalline silicon film with a thickness of 2,000 ml was deposited by the VD method at an accelerating voltage of 50 keV and a dose of 2. 5 x 10
An amorphous silicon film 22 was formed by implanting silicon ions twice at ``crA-2'', an acceleration voltage of 12 Q ke V, and a dose of 5.4 x 10150 m-''.

As shown in Figure 4(a), only the first heating is performed at 650°C for 20 hours, which is longer than the latent time, to generate crystal nuclei, and the second and subsequent heat treatments are performed at 600°C for 20 hours. Heat treatment was repeated within the latent time until the amorphous portion disappeared.

As a result, large crystals could be obtained as shown in transmission micrographs in FIG. 4(a) and FIG. 5(a).

In addition, as shown in FIG. 4(b), only the first heating was performed at a high temperature of 750°C for 20 hours for a longer time than the latent time.
The second and subsequent heat treatments are conducted at 600℃2 to generate crystal nuclei.
The heat treatment was carried out within the latent time of 0 hours, and the heat treatment was repeated until the amorphous portion disappeared.

As a result, large crystals could be obtained as shown in FIG. 4(b).

From the comparison between FIG. 4(a) and FIG. 4(b), according to the present invention, the size of the crystal can be controlled by the first heating temperature.

Also, for comparison, Fig. 4 (C) shows the conventional 650
Heating was carried out continuously at °C. In this case, as shown in the transmission micrograph in Figure 5(b), new nuclei are generated while the crystals are growing from the nuclei and becoming larger, so small crystals mix with the large crystal grains and form in the film. It's coming.

In contrast, in the method of the present invention shown in FIGS. 4(a) and 5(a), large crystals with uniform grain sizes are formed.

Such a difference in crystal grain size brings about a large difference in characteristics when an element is actually formed.

Example 3 Next, as a third example of the present invention, in order to measure the difference in device characteristics due to the difference in crystal grain size, a MOSFET was actually used.
Form ET.

As shown in FIG. 6, this MOSFET is made of n-type nested crystalline silicon ions formed by solid-phase growth by heat-treating a polycrystalline silicon film formed on the upper layer of a silicon oxide film 11 formed on the surface of a silicon substrate 10. It was formed in

This n-type wheel crystal silicon film 1 is made by forming a desired element region in a p-type silicon substrate, depositing a silicon oxide film by CVD method, and depositing a silicon oxide film on top of this film to a thickness of 20 mm by CVD method.
Deposit an n-type polycrystalline silicon film of
keV, dose 2.5 x 1015Cta-2
, acceleration voltage 12CIkeV, F-zuise amount 5.4 x 10
``cm-2'' silicon ions were implanted twice to form an amorphous silicon film, and the first heating was performed at 750°C for 30 minutes, which was longer than the latent time, to remove the crystal nuclei. The second and subsequent heat treatments were performed at 620° C. for 2 hours within the latent time, and the heat treatments were repeated until the amorphous portion disappeared.

A gate electrode 3 made of polycrystalline silicon is formed on the surface of the n-type silicon layer 1 formed in this manner with a gate insulating film 2 interposed therebetween. 10 p layers 5a and 5b are formed. 6a.

6b is a source and drain electrode. Here, the dimensions are gate width W/gate length L-1/1.5 μm.

The results of measuring the variations in threshold voltage of the MOSFET thus formed are shown in FIG. 7(a).

For comparison, only the step of heat-treating the amorphous silicon layer was performed once at 700°C for 5 hours as in the conventional method, and the other conditions were exactly the same as in the previous example. The results of determining n1 are shown in FIG. 7(b).

Although the maximum crystal grain size of these crystals of the n-type silicon layer 1 is approximately 0.5 μm, FIG.
As is clear from the comparison in FIG. 7(b), the MOSFET formed by the method of the present invention has much smaller variations in threshold voltage.

This means that if the relationship between the crystal grain size and the channel region of the device becomes unstable, such as grain boundaries entering or not entering the channel region, or the number of grain boundaries differing, the characteristics of the semiconductor device will change. This is because there is a large variation due to this influence.

According to the method of the present invention, the size of the crystal can be made appropriately smaller than the channel region and uniform in size, so that all devices stably contain the same number of grain boundaries and do not cause variations in device characteristics. You can do it like this.

Next, the latent time at each temperature was measured.

The results are shown in FIG.

Here, too, after forming the desired device region in the silicon substrate, a silicon oxide film is deposited by the CVD method, and a polycrystalline silicon film with a thickness of 2000 nm is deposited on top of this by the CVD method, with an acceleration voltage of 50 k eV, Dose amount 2. 5 X
The amorphous silicon film was formed by implanting silicon ions twice at 1015 cm-', an acceleration voltage of 12 QkeV, and a dose of 5-4 x 10'' cm-2, and then heat-treated.

The relationship between the crystallization rate and each temperature of this film was measured.

The results are shown in FIG. The time at which crystallization begins, that is, the latent time, at each temperature is shown below. Although the length of this latent time varies depending on the formation conditions and method of forming the amorphous silicon film, the general behavior of the film is formed as described above.

Next, the formation of crystal nuclei was measured when the heat treatment method was changed.

Here, we observed the generation of nuclei when the heating temperature and time were the same and the cooling rate after heating was varied. 9th
Figure 9(a) shows the case where the cooling rate is fast, and Figure 9(b) shows the case where the cooling rate is slow. As is clear from these comparisons, even if heating is stopped within the latent time, if the cooling rate is fast, a so-called quench (quick freezing) state will occur, and crystal nuclei will be generated the next time heating is performed. On the other hand, if the temperature is lowered slowly, the amorphous silicon will return to its original state during the process of lowering the temperature, and no nuclei will be generated even after repeated heating. Does the optimum cooling rate differ depending on the film quality of amorphous silicon?1. 'C/min is suitable, and 40
The cooling rate was irrelevant below 0°C.

Furthermore, when impurities such as phosphorus were added, the same effect could be obtained even if the slow cooling rate was increased.

Furthermore, as shown in Figure 10(b), instead of slow cooling, the same effect could be obtained by repeating the process of rapidly cooling, maintaining it at a low temperature of about 50 cm for a predetermined period of time, and then heating it again. . Figure 10(a) shows the
This shows the generation of nuclei when the process of maintaining at ℃ for a predetermined period of time and heating again is repeated. From these comparisons, it can be seen that even with rapid cooling, the
It can be seen that the same effect as slow cooling can be obtained by maintaining the temperature at about 0 cm and raising the temperature again. Moreover, by doing so, the total heating time can be shortened.

Embodiment 4 FIG. 11 is a diagram showing a process for forming a polycrystalline silicon film according to a fourth embodiment of the present invention.

First, as shown in FIG. 11(a), after forming a desired element region in a p-type silicon substrate 20, a silicon oxide film 21 is deposited using the CVD method. A 2μ-thick amorphous silicon film 32 is deposited. The deposition conditions at this time were a deposition temperature of 450 to 600°C.
The raw material gas was silane gas at 0.1 to 5 Torr or disilane gas at 0.1 to 5 Torr.

As shown in FIG. 11(b), the acceleration voltage is 160K.
eV, dose 2 x 1.0"c-2, acceleration voltage 120 keV, dose 5-4 x 1.O15o
Silicon ions are implanted twice (n-') to damage the interface between the silicon oxide film 21 and the amorphous silicon film 32.

Next, as shown in FIG. 11(C), this amorphous silicon film 32 is heated at 600° C. for 10 hours as shown in the heating profile to form large grains as shown in FIG. 11(d). Recrystallized polycrystalline silicon 33 is obtained.

Recrystallized polycrystalline silicon 33 thus formed
A planar TEM photograph after solid-phase growth is shown in FIG. 12(a). From this figure, it can be seen that a polycrystalline silicon film with a maximum crystal grain size of 2 μm is formed. For comparison, FIG. 12(b) shows a planar TEM photograph of conventional amorphous silicon after solid-phase growth in which recrystallization was performed without ion implantation.

This is believed to be because ion implantation into amorphous silicon suppresses its generation from the interface.

FIG. 12(e) shows a cross-sectional TEM photograph of a conventional example in which amorphous silicon is directly recrystallized without ion implantation. This photo also shows that crystal grains are quickly formed at a high density at the amorphous silicon/insulating film interface in the early stages of heat treatment.

A conceptual diagram for explaining this result is shown in FIG. −
13(a) to 13(C) are examples of the present invention, conventional recrystallization of amorphous silicon without ion implantation, and recrystallization of polycrystalline silicon by ion implantation. This shows the case where the conversion is performed.

As described above, according to the method of the present invention, since nucleation from the interface is suppressed by ion implantation, recrystallized polycrystalline silicon having a large crystal grain size can be obtained.

A MOSFET was prepared using this film in the same manner as shown in FIG. 6 in Example 3, and its current-voltage characteristics were measured. The results are shown in FIG. 14(a). Figure 14 (b
) is the current of a MOSFET formed using a recrystallized polycrystalline silicon film formed by a conventional method.
The results of measuring voltage characteristics are shown. Curve a in Figure 14 is L
Curve C is for polycrystalline silicon formed by PCVD method and recrystallized by heat treatment, curve C is for amorphous silicon formed by LPCVD method and recrystallized by heat treatment. This is a characteristic curve of a MOSFET formed using a MOSFET that is recrystallized by heat treatment after ion implantation.

These comparisons also show that M formed by the method of the example of the present invention
It can be seen that the OSFET exhibits extremely good characteristics.

The result of calculating the maximum field effect mobility from this measurement result17
It was 5 cm'/Vs. Incidentally, Table 1 shows the maximum field effect mobilities and maximum grain sizes of the materials formed by the methods of the present invention and the conventional methods.

This table also shows that the MOSFE formed by the method of the embodiment of the present invention
It can be seen that T exhibits extremely good characteristics.

In addition, in the above embodiment, the amorphous silicon was made by CVD.
Although it is formed by a method, it may be formed by a vapor deposition method or a sputtering method. In addition, the acceleration voltage and dose amount are, for example, when the film thickness of amorphous silicon is 0.1 μm.
When M, the acceleration voltage is 90~1], Ok e V, dose, t7xlO"-BxlQ15c-2, and the film thickness is 0.
．． Acceleration voltage 150 to 170 k e V when 2μ
, the dose amount is preferably 1 to 6×10 15 cff12.

Moreover, similar results could be obtained by performing solid phase growth at a temperature in the range of 500 to 900°C.

Furthermore, the ion implantation species used to suppress nucleation from this interface is not limited to silicon, but similar effects can be obtained with arsenic, boron, argon, neon, oxygen, nitrogen, etc. . When using these elements, by setting the accelerating voltage and dose according to each mass number, it is possible to always use the minimum dose and accelerating voltage necessary to form damage at the interface. do.

Also, in terms of leakage current and threshold voltage, the MOSFET of the present invention is superior to MOSFETs formed by conventional methods.
can obtain extremely excellent properties.

This result can be considered as follows.

In other words, when forming an amorphous silicon film by implanting silicon ions into a polycrystalline silicon film, a high dose of 1 x 10 l6Cs-2 is required to completely eliminate crystal grains from the polycrystalline silicon. It is also necessary to set the accelerating voltage so that the entire layer is damaged at the same time. This is considered to be because if the dose is not sufficient, many crystal grains remain in the film and become nuclei and begin crystallization, making it impossible to obtain a large crystal grain size.

On the other hand, if amorphous silicon is deposited from the beginning, it is sufficient to damage only the amorphous silicon/insulating film interface.

That is, the accelerating voltage may be set so that the depth at which the maximum damage formation efficiency occurs and the thickness of the amorphous silicon film approximately match, and a relatively low dose amount is sufficient.

As a result, the amount of impurities such as nitrogen that is ion-implanted simultaneously with silicon ion implantation can be suppressed. Since impurities such as nitrogen cause neutral scattering in polycrystalline silicon, it is thought that devices with a low impurity concentration in the film can achieve high mobility.

Curve a in FIG. 15 shows the results of measuring the concentration distribution of nitrogen in the depth direction when ions are implanted into amorphous silicon using the method of the present invention.

For comparison, the curves show the results of measuring the concentration distribution of nitrogen in the depth direction when ions were implanted into polycrystalline silicon. As is clear from these comparisons, it can be seen that according to the method of the present invention, the impurity concentration in the film is kept low.

Example 5 Next, a fifth embodiment of the present invention will be described.

MOSFs similar to those formed in Example 3 and Example 4
This is to form an ET, and here the crystal grain size and channel length are optimized.

As shown in FIG. 16, this MOSFET is characterized by being formed so that the channel length is twice the crystal grain size. Here, 41 is a silicon substrate, 42
4 is a silicon oxide film, 43 and 45 are source/drain regions, and 44 is a channel region. The channel region and source/drain region were formed by implanting ions into amorphous silicon and recrystallizing it by repeated heating at 700° C. for 30 minutes as in Example 4. It is made of polycrystalline silicon with a thickness of 0.5 .mu.m, and two grain boundaries 46 are formed in the length direction within the channel region 45.

FIG. 17(a) shows the results of measuring the mobility dispersion of this MOS FET. It can be seen that the variation in mobility has become smaller. For comparison, FIG. 17(C) shows the results of measuring the mobility dispersion of a MOSFET made of polycrystalline silicon with a grain size of 2 μm. From these comparisons, it can be seen that variations in mobility can be suppressed by using the MOSFET of the present invention in which the channel length is formed to be twice the crystal grain size.

Further, FIG. 17(b) shows the results of measuring the variation in mobility when the film thickness was 0.08 μl.

As a result, the mobility can be increased compared to the case where a polycrystalline silicon film having a thickness of 0.1 μm and a grain size of 0.5 μm is used as shown in FIG. 17(a).

Figure 17(d) shows a film with a thickness of 0.1μ obtained by recrystallization by repeated heating at 600°C for 10 hours.
(2) Shows the results of measuring variations in mobility when formed using polycrystalline silicon with a grain size of 2 μm. It can be seen from this figure that the mobility varies widely.

Further, the results of measuring the variation in the r14M voltage of this MOSFET are shown as a in FIG. 18. b is a MOSFET formed using polycrystalline silicon with a grain size of 2 μ-. From these comparisons, it can be seen that particle size RO 15μ dust channel length and 2μ
(R/L-1/4) MOSFET of the present invention or R/
It can be seen that the variation in threshold voltage is much smaller than that of the conventional MOSFET of L -1,/1.

The reason why this variation in threshold voltage occurs will be considered.

As shown in FIG. 19(a) and FIG. 19(b), two cases are possible: a case where there is a grain boundary 46 in the channel region and a case where there is no grain boundary 46.

If a grain boundary enters or does not enter the channel region, variations in threshold voltage occur.

Therefore, if the number of grain boundaries is increased, the variation will be reduced.

However, as the number of grain boundaries increases, the mobility decreases.

Therefore, we measured the variation in mobility by varying the particle size with respect to the channel length. As a result, by reducing the grain size so that the ratio of grain size R/channel length is less than 1/2, a large number of grain boundaries exist in the channel length direction, and the difference in the number of grain boundaries increases the mobility. It is possible to prevent variations. If the unilateral diameter R/channel length is less than 1/10, the particle size will be too large and the mobility will be significantly reduced. Therefore, it was found that by setting R/L to 1/2 to 1/10, it was possible to obtain a MOSFET with little variation and high mobility. The particle diameter here refers to the maximum diameter of the particles.

Furthermore, in order to increase the mobility by reducing the grain size, the characteristics can be improved by reducing the film thickness of the channel region to 0.1 μm or less. In the above embodiments, 81 was used as the semiconductor material, but other semiconductors such as Ge or compound semiconductors such as 5IGe may also be used.

〔Effect of the invention〕

As explained above, according to the first aspect of the present invention, amorphous silicon is crystallized by solid-phase growth by repeating heat treatment on the amorphous silicon film multiple times, each heating time being within the latent time. Since this is carried out, a recrystallized silicon film with a large crystal grain size can be obtained.

In the second aspect of the present invention, an amorphous silicon film is deposited on an insulating film, silicon ions are implanted so as to reach the vicinity of the interface between this amorphous silicon film and the insulating film, and then heat treatment is performed to form an amorphous silicon film by solid phase growth. Since silicon is crystallized, the generation of crystal grains near the interface can be suppressed.

In the third aspect of the present invention, since the semiconductor element is formed such that the crystal grain size of the silicon thin film is 1/2 or less and 1/10 or more of the channel length, variations in threshold voltage are suppressed and characteristics are improved. It becomes possible to obtain a good semiconductor device.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing an in-phase growth method according to an embodiment of the present invention, and FIGS. 2(1) to 2(d) show formation of a recrystallized polycrystalline silicon thin film using in-phase growth according to an embodiment of the present invention. A process diagram showing the method, and FIG. 3 is a diagram showing the results of measuring the relationship between the length of one heating time and the length of the crystal part extending from the seed part (lateral in-phase growth distance) in the same example. , Figure 4 (a
) and FIG. 4(b) are explanatory diagrams showing the solid phase growth method of the second embodiment of the present invention, FIG. 4(C) is an explanatory diagram showing the in-phase growth method of the conventional example, and FIG. 8) and Figure 5 (
b) is a TEM photograph showing polycrystalline silicon formed by the method of the embodiment of the present invention shown in FIG.
FIG. 6 is a TEM photograph showing polycrystalline silicon formed by the conventional method shown in FIG.
Figure (b) shows the MOS of the third embodiment of the present invention and the conventional example.
A diagram showing the results of measuring the variation in threshold voltage of FET,
FIG. 8 is a diagram showing the relationship between heating time and crystallization rate, and FIG. 9(a), FIG. 9(b), FIG. 10(a), and FIG. 11(a) to 11(d) are diagrams illustrating a heat treatment method according to an embodiment. FIGS. 11(a) to 11(d) are steps showing a method for forming a recrystallized polycrystalline silicon thin film using in-phase growth according to a fourth embodiment of the present invention. 12(a) is a plan view TEM photograph of recrystallized polycrystalline silicon formed by the method of the fourth embodiment of the present invention, and FIG. Figure 12 (C) is a plan view TEM photograph of recrystallized polycrystalline silicon that has been recrystallized without any implantation. Figures 13(a) to 13(c) are diagrams showing cross-sectional TEM photographs at the initial stage when recrystallization was carried out in an embodiment of the present invention and conventional amorphous silicon without ion implantation. In this case, conceptual diagram when ion implantation is performed into a polycrystalline silicon film and recrystallization is performed, 14th
Figures (a) are diagrams showing current-voltage characteristics of a MOSFET formed by the method of the present invention, Figure 14 (b) are diagrams showing current-voltage characteristics of a MOSFET formed by a conventional method, and Figure 15 is a diagram showing current-voltage characteristics of a MOSFET formed by the method of the present invention. Figure 16 shows the results of measuring the concentration distribution of nitrogen in the depth direction when ions are implanted into amorphous silicon using the conventional method.
FIG. 17(a) is a perspective view showing the MOSFET of the embodiment.
Figures 17(d) to 17(d) are diagrams showing the results of measuring the mobility variations of the MOSFET of the same example and the conventional MOSFET, and Figure 18 is a diagram showing the results of measuring the variations of the threshold voltage. FIG. 19 is a diagram explaining the principle of the same embodiment. 1. N-type silicon layer, 2. Gate insulating film, 3. Gate electrode, 5a, 5b-p ten layers, 6a, 6b-. Source/drain electrode, 20. Silicon substrate, 2]. Silicon oxide film, 22'... Polycrystalline silicon film, 22.
... Amorphous silicon film, 23 ... Recrystallized polycrystalline silicon film, 32 ... Amorphous silicon film, 41
・・Silicon substrate, 42・Silicon oxide film, 43.45
... Source train region, 44 ... Channel region, 46
・Grain boundaries. Kai Saki Figure 1 Figure 2 Time (Q) Watch r: I (b) Figure (busy 1) Figure (fΦ2) 200nm (Q,) ((+) ne dimming? 1 1 direct e pressure (V) (b) ftf Figure 7 Figure 6 Time for surface? (C) (d) No. 77rl!J(f'92) -Ch ly4ability (Q) Mobility Cb) -21nOtJac'rl
sK 600”C), 0.5pm (gM
18M 700'C)) Figure 18 Procedural Amendment (Method) % Formula % Name of the invention Semiconductor device and its manufacturing method (0") (307) Toshiba Corporation September 10, 1990 (Shipping mortar 1990) (September 25) (b) Contents of amendment to Figure 19 7 (1) "Polycrystalline silicon" on page 30, line 14 and line 16 of the same page of the specification of the present application has been changed to "crystal of polycrystalline silicon.""Structure". (2) The ``diagram showing a planar TEM photograph of polycrystalline silicon'' in the 8th line above and the 11th line of the same page on page 31 of the same specification was changed to ``crystal structure of polycrystalline silicon''. It has been corrected to ``Plane TEM photo showing the (3) In the 14th line of page 31 of the same specification, "Diagram showing a cross-sectional TEM photograph at the initial stage of the case" is corrected to "A cross-sectional TEM photograph showing the crystal structure at the initial stage of the case." (4) "Ion implantation" on page 31, line 16 of the same specification is corrected to "ion implantation." (5) Figure 11 of the accompanying drawings of the same specification is corrected as shown in the attached sheet. Figure 11

Claims (5)

[Claims] (1) A deposition step of depositing an amorphous semiconductor film on the substrate surface, a seed crystal formation step of forming a seed crystal in the amorphous semiconductor film, and a heat treatment each time shorter than the latent time of solid phase growth. A method for manufacturing a semiconductor device, comprising a heat treatment step of repeatedly performing solid phase growth from the seed crystal. (2) Claim (1) characterized in that the seed crystal forming step is a heat treatment step that is longer than the latent time of solid phase growth.
A method of manufacturing the semiconductor device described above. (3) The heat treatment step includes a heating step shorter than the latent time of solid phase growth and a gradual cooling rate such that the state of the non-crystalline region in the amorphous semiconductor film returns to the state before the heat treatment. A claim characterized in that it includes a slow cooling step of cooling (
1) The method for manufacturing the semiconductor device described above. (4) An amorphous semiconductor film deposition step of depositing an amorphous semiconductor film on the insulating film, and ion implantation of the same material as the semiconductor so as to reach near the interface between the amorphous semiconductor film and the insulating film. The ion implantation process and the heat treatment, which is shorter than the latency time of solid phase growth, are repeated.
1. A method of manufacturing a semiconductor device, comprising: a heat treatment step of crystallizing an amorphous semiconductor by solid phase growth. (5) In a semiconductor device including a semiconductor element within a semiconductor thin film formed by a solid phase growth method, the maximum grain size of crystal grains of the amorphous semiconductor thin film is one-half or less of the channel length of the semiconductor element. , 1/10 or more.