JPH0461156A - Writing method of semiconductor storage device - Google Patents
Writing method of semiconductor storage deviceInfo
- Publication number
- JPH0461156A JPH0461156A JP2164798A JP16479890A JPH0461156A JP H0461156 A JPH0461156 A JP H0461156A JP 2164798 A JP2164798 A JP 2164798A JP 16479890 A JP16479890 A JP 16479890A JP H0461156 A JPH0461156 A JP H0461156A
- Authority
- JP
- Japan
- Prior art keywords
- fuse
- upper electrode
- voltage
- insulating film
- mos transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000015556 catabolic process Effects 0.000 claims description 8
- 239000004020 conductor Substances 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
Landscapes
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
この発明は半導体記憶装置の古き込み方法に関し、より
詳しくは、ＭＯＳトランジスタとごのＭＯＳトランジス
タに直列に接続されたアンタイフコズとからなるメモリ
セルを有する半導体記憶装置の書き込み方法に関する。The present invention relates to a method of aging a semiconductor memory device, and more particularly to a method of writing a semiconductor memory device having a memory cell consisting of a MOS transistor and an anti-fuco transistor connected in series to each MOS transistor.
最近、第２図に示Ｖように、ＦＲＯＭのメモリセルＭを
Ｐ型半導体基板Ｉの表面に形成されたｎチャネル型ＭＯ
Ｓ）＝ランジスタ８と、このＭＯＳトランジスタ８に直
列に接続したアンタイフユーズ７とで構成することが多
い（例えば“ダイエレクトリック・ヘースト・アンタイ
フユーズ・フォー・ロジック・アンド・メモリＩＣ”Ｉ
ＥＩ）ＭＢ２、ｐｐ７８６−７８９）。上記アンタイフ
ユーズ７は、第３図に示ｔように、上記ＭＯ６トランジ
スタ８のドレイン３上に薄い絶縁膜ｌＯと上部電極５と
を設けて構成される。なお、２はメモリセルＭを分離す
る局所酸化膜、４はゲート電極を示している。このメモ
リセルＭに情報の書き込みを行う場合、まずゲート電極
４に正の電圧を印加して、ＭＯＳトランジスタ８をオン
させる。この状態で、アンタイフユーズ７の上部電極５
とＭＯＳトランジスタ８のソース６との間に、上部電極
５が正。
ソース６が負となる向きに数ボルトの電圧Ｖｐを印加す
る。すなわち、ＭＯＳトランジスタ８を介してアンタイ
フユーズ７に電圧を印加する。そして、上記アンタイフ
ユーズ７の絶縁膜１０を絶縁破壊して、アンタイフユー
ズ７を導通させる。従来はこの段階で書き込みを完了し
ている。Recently, as shown in FIG.
S) = often composed of a transistor 8 and an untie fuse 7 connected in series to this MOS transistor 8 (for example, a "dielectric heist untie fuse for logic and memory IC" I)
EI) MB2, pp786-789). The anti-fuse 7 is constructed by providing a thin insulating film lO and an upper electrode 5 on the drain 3 of the MO6 transistor 8, as shown in FIG. Note that 2 indicates a local oxide film separating the memory cells M, and 4 indicates a gate electrode. When writing information into this memory cell M, first, a positive voltage is applied to the gate electrode 4 to turn on the MOS transistor 8. In this state, the upper electrode 5 of the untied fuse 7
The upper electrode 5 is connected between the source 6 of the MOS transistor 8 and the source 6 of the MOS transistor 8. A voltage Vp of several volts is applied in the direction in which the source 6 becomes negative. That is, a voltage is applied to the anti-fuse 7 via the MOS transistor 8. Then, the insulating film 10 of the anti-fuse 7 is dielectrically broken down to make the anti-fuse 7 conductive. Conventionally, writing is completed at this stage.
ところで、上記アンタイフユーズ７は数μＡの電流で絶
縁破壊する。そして、絶縁破壊後の電気抵抗は絶縁破壊
時の電流の大きさに依存し、電流が大きければ電気抵抗
は低下する一方、電流が小さければ電気抵抗は大きいま
まとなっている。従来のようにＭＯＳトランジスタ８を
介してアンタイフユーズ７に電圧を印加する場合、数ボ
ルトの電圧Ｖｐを印加するだけでは、電流は制限されて
アンタイフユーズ７の電気抵抗が十分には下がらないこ
とがある。この結果、第１図（ａ）に示すように、メモ
リセルＭを動作させたとき、５ｍＡ以下の低電流域（図
中に矢印で示す箇所）で電圧−電流（Ｖ−Ｉ）特性が湾
曲し、特性異常を示すという問題が生じている。この問
題は、ＭＯＳトランジスタ８が微細化されるにつれて深
刻になってきている。なお、電源の電圧に制約があるた
め、印加する電圧Ｖｐをあまり大きくすることはできな
い。
そこで、この発明の目的は、数ボルトの電圧でもって上
記アンタイフユーズの電気抵抗を十分に低下させること
ができる半導体記憶装置の書き込み方法を提供すること
にある。By the way, the anti-fuse 7 undergoes dielectric breakdown with a current of several μA. The electrical resistance after dielectric breakdown depends on the magnitude of the current at the time of dielectric breakdown; if the current is large, the electrical resistance decreases, while if the current is small, the electrical resistance remains large. When applying a voltage to the anti-fuse 7 via the MOS transistor 8 as in the past, applying only a voltage Vp of several volts limits the current and does not reduce the electrical resistance of the anti-fuse 7 sufficiently. Sometimes. As a result, as shown in Figure 1(a), when the memory cell M is operated, the voltage-current (V-I) characteristic curves in the low current range of 5 mA or less (points indicated by arrows in the figure). However, a problem has arisen in that it exhibits characteristic abnormalities. This problem is becoming more serious as the MOS transistor 8 is miniaturized. Note that since there are restrictions on the voltage of the power supply, the applied voltage Vp cannot be increased too much. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a writing method for a semiconductor memory device that can sufficiently reduce the electrical resistance of the anti-fuse with a voltage of several volts.
上記目的を達成するために、この発明の半導体記憶装置
の書き込み方法は、半導体基板の表面に形成されたＭＯ
Ｓトランジスタと、このＭＯＳトランジスタのドレイン
上に絶縁膜と上部電極とを設けて構成され、上記ドレイ
ンと上部電極との間の電圧により上記絶縁膜が絶縁破壊
されたとき導通して情報を記憶するアンタイフユーズと
からなる半導体記憶装置の書き込み方法であって、上記
ＭＯＳトランジスタをオンさせた状態で、上記アンタイ
フユーズの上部電極と上記ＭＯＳトランジスタのソース
との間に所定の電圧を印加して、上記アンタイフユーズ
の絶縁膜を絶縁破壊した後、上記アンタイフユーズの上
部電極と上記半導体基板との間に所定の電圧を印加して
、上記絶縁膜を絶縁破壊したときの電流よりも大きい電
流を上記アンタイフユーズに流すようにしたことを特徴
としている。In order to achieve the above object, a writing method for a semiconductor memory device according to the present invention includes an MO
It is composed of an S transistor and an insulating film and an upper electrode provided on the drain of this MOS transistor, and becomes electrically conductive and stores information when the insulating film is dielectrically broken down by a voltage between the drain and the upper electrode. A writing method for a semiconductor memory device comprising an unty fuse, wherein a predetermined voltage is applied between the upper electrode of the unty fuse and the source of the MOS transistor while the MOS transistor is turned on. , after dielectric breakdown of the insulating film of the untied fuse, a predetermined voltage is applied between the upper electrode of the untied fuse and the semiconductor substrate, and the current is greater than the current when dielectric breakdown of the insulating film is caused. It is characterized in that the current is made to flow through the untied fuse.
以下、この発明の半導体記憶装置の書き込み方法を実施
例により詳細に説明する。なお、第２図および第３図に
示したＦＲＯＭの書き込み方法について説明するものと
する。
まず、ゲート電極４に所定の電圧を印加してＭＯＳトラ
ンジスタ８をオンさせた状態で、アンタイフユーズ７の
上部電極５とＭＯＳトランジスタ８のソース６との間に
、上部電極５が正ソース６が負となる向きに数ボルトの
電圧Ｖｐを印加する。すなわち、従来と同様に、ＭＯＳ
トランジスタ８を介してアンタイフユーズ７に電圧を印
加する。そして、上部電極５．絶縁膜１０．トレイン３
゜チャネル９およびソース６を経路として電流を流して
、アンタイフユーズ７の絶縁膜ＩＯを絶縁破壊してアン
タイフユーズ７を導通させる。
次に、上記アンタイフユーズ７の上部電極５と基板１と
の間に、上部電極５が負、基板（Ｐ型用が正となる向き
に、数ボルトの電圧Ｖａを印加する。そして、基板１．
ドレイン３．絶縁破壊された絶縁膜ｌＯおよび電極５を
経路として電流を流す。
このようにした場合、ＭＯＳトランジスタ８のチャネル
９を経路としていないので、数ボルトの電圧でもって数
ｍＡの電流を流すことができる。したがって、第１図（
ｂ）に示すように、メモリセルＭを動作させたとき、低
電流域のＶ−Ｉ特性をリニアにすることができ、正常動
作させることができる。
なお、この実施例では、ＭＯＳトランジスタ８はＰ型１
４４導体基板ｌｔに形成されノ、・、ｎチャ碕ル型のも
のと１２だが、これに限られるものではなく、逆の極性
であ−・でも良い。この場合、印加４゛る電圧の向きを
逆にして書き込みを行えば良い。。Hereinafter, the method of writing in a semiconductor memory device of the present invention will be explained in detail with reference to examples. Note that the writing method of the FROM shown in FIGS. 2 and 3 will be explained. First, with a predetermined voltage applied to the gate electrode 4 to turn on the MOS transistor 8, the upper electrode 5 is connected between the upper electrode 5 of the anti-fuse 7 and the source 6 of the MOS transistor 8. A voltage Vp of several volts is applied in the direction in which the voltage Vp becomes negative. That is, as in the past, MOS
A voltage is applied to the anti-fuse 7 via the transistor 8 . And upper electrode 5. Insulating film 10. train 3
A current is passed through the channel 9 and the source 6 to dielectrically break down the insulating film IO of the anti-fuse 7 and make the anti-fuse 7 conductive. Next, a voltage Va of several volts is applied between the upper electrode 5 of the anti-fuse 7 and the substrate 1 in such a direction that the upper electrode 5 is negative and the substrate (for P type is positive). 1.
Drain 3. A current is passed through the dielectrically broken insulating film IO and the electrode 5 as a path. In this case, since the channel 9 of the MOS transistor 8 is not used as a path, a current of several mA can flow with a voltage of several volts. Therefore, Fig. 1 (
As shown in b), when the memory cell M is operated, the V-I characteristic in the low current region can be made linear, and the memory cell M can be operated normally. In this embodiment, the MOS transistor 8 is of P type 1.
44 is formed on the conductor substrate lt, and 12 is of the N-channel type, but is not limited to this, and may have the opposite polarity. In this case, writing may be performed by reversing the direction of the applied voltage. .
以」−より明らかなように、この発明の崖導体記憶装置
の書き込み方法は、アンタイフユーズの絶縁膜を従来通
りに絶縁破壊した後、アンタイフユーズの北部電極と半
導体基板との間に電圧を印加して、上記アンタイフユー
ズに対して上記絶Ｗ膜を絶縁破壊したときの電流よりも
大きい電流を流すようにしているので、上記アンタイフ
ユーズの電気抵抗を数ボルトの電圧でもって十分に低ト
させることができる。As is clear from this, the writing method of the cliff conductor memory device of the present invention involves dielectrically breaking down the insulating film of the untying fuse in the conventional manner, and then applying a voltage between the northern electrode of the untying fuse and the semiconductor substrate. A voltage of several volts is sufficient to reduce the electrical resistance of the untying fuse by applying a current larger than the current generated when dielectrically breaking down the untying W film to the untying fuse. It can be lowered to
第１図（ａ）はアンタイフユーズを従来通りに絶縁破壊
した後におけるメモリセルの■−■特性を示す図、同図
（ｂ）はこの発明の−・実施例の゛ｆ導体記憶装置の書
き込み方法によって書き込みした後におけるメモリセル
のｖ−■特性を示す図、第２図、第：（図はそれぞ右書
き込みを？ｊう△＜ Ａｓ Ｐ ｒｔ 。
Ｍのメモリセルの等価回路、断面溝］告を）・４図で”
ある。
１ ・Ｉ）型半導体￥、板、２ 局所酸化膜、３ ・ｌ
・レイン、４ ・ゲー ）・電極、６ ’−ス、７
アンタイフユーズ、
８− Ｍ ＯＳ トランジスタ、９ ヂャネル、ｌＯ絶
縁膜、Ｍ メモリセル、７FIG. 1(a) is a diagram showing the ■-■ characteristics of the memory cell after dielectric breakdown of the untied fuse in the conventional manner, and FIG. Figure 2 shows the v-■ characteristics of the memory cell after writing using the writing method. 4 pictures)
be. 1 ・I) type semiconductor ¥, plate, 2 local oxide film, 3 ・l
・Rain, 4 ・Ge)・Electrode, 6'-su, 7
Untied fuse, 8- M OS transistor, 9 channel, IO insulating film, M memory cell, 7
Claims (1)
タと、このＭＯＳトランジスタのドレイン上に絶縁膜と
上部電極とを設けて構成され、上記ドレインと上部電極
との間の電圧により上記絶縁膜が絶縁破壊されたとき導
通して情報を記憶するアンタイフューズとからなる半導
体記憶装置の書き込み方法であって、 上記ＭＯＳトランジスタをオンさせた状態で、上記アン
タイフューズの上部電極と上記ＭＯＳトランジスタのソ
ースとの間に所定の電圧を印加して、上記アンタイフュ
ーズの絶縁膜を絶縁破壊した後、上記アンタイフューズ
の上部電極と上記半導体基板との間に所定の電圧を印加
して、上記絶縁膜を絶縁破壊したときの電流よりも大き
い電流を上記アンタイフューズに流すようにしたことを
特徴とする半導体記憶装置の書き込み方法。(1) Consisting of a MOS transistor formed on the surface of a semiconductor substrate, and an insulating film and an upper electrode provided on the drain of the MOS transistor, the insulating film is insulated by a voltage between the drain and the upper electrode. A writing method for a semiconductor memory device comprising an antifuse that becomes conductive and stores information when destroyed, the method comprising: connecting the upper electrode of the antifuse and the source of the MOS transistor with the MOS transistor turned on; A predetermined voltage is applied between them to cause dielectric breakdown of the insulating film of the antifuse, and a predetermined voltage is applied between the upper electrode of the antifuse and the semiconductor substrate to cause dielectric breakdown of the insulating film. A method for writing in a semiconductor memory device, characterized in that a current larger than the current flowing through the antifuse is caused to flow through the antifuse.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16479890A JPH0834292B2 (en) | 1990-06-22 | 1990-06-22 | Writing method of semiconductor memory device |
| US07/716,785 US5299151A (en) | 1990-06-22 | 1991-06-18 | Method for writing into semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16479890A JPH0834292B2 (en) | 1990-06-22 | 1990-06-22 | Writing method of semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0461156A true JPH0461156A (en) | 1992-02-27 |
| JPH0834292B2 JPH0834292B2 (en) | 1996-03-29 |
Family
ID=15800137
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16479890A Expired - Fee Related JPH0834292B2 (en) | 1990-06-22 | 1990-06-22 | Writing method of semiconductor memory device |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5299151A (en) |
| JP (1) | JPH0834292B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007134373A (en) * | 2005-11-08 | 2007-05-31 | Nec Electronics Corp | Semiconductor device and fuse treatment method thereof |
| JP2012033221A (en) * | 2010-07-29 | 2012-02-16 | Renesas Electronics Corp | Semiconductor memory device and program method for anti-fuse |
| CN113872177A (en) * | 2021-10-14 | 2021-12-31 | 上海军陶科技股份有限公司 | Anti-reverse-filling circuit based on field effect transistor |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5426614A (en) * | 1994-01-13 | 1995-06-20 | Texas Instruments Incorporated | Memory cell with programmable antifuse technology |
| US5444650A (en) * | 1994-01-25 | 1995-08-22 | Nippondenso Co., Ltd. | Semiconductor programmable read only memory device |
| US5468680A (en) * | 1994-03-18 | 1995-11-21 | Massachusetts Institute Of Technology | Method of making a three-terminal fuse |
| US5552743A (en) * | 1994-09-27 | 1996-09-03 | Micron Technology, Inc. | Thin film transistor redundancy structure |
| DE4440539C2 (en) * | 1994-11-12 | 1996-09-19 | Itt Ind Gmbh Deutsche | Programmable semiconductor memory |
| US5553022A (en) * | 1994-12-27 | 1996-09-03 | Motorola Inc. | Integrated circuit identification apparatus and method |
| US5741720A (en) * | 1995-10-04 | 1998-04-21 | Actel Corporation | Method of programming an improved metal-to-metal via-type antifuse |
| US5896041A (en) * | 1996-05-28 | 1999-04-20 | Micron Technology, Inc. | Method and apparatus for programming anti-fuses using internally generated programming voltage |
| US5841723A (en) * | 1996-05-28 | 1998-11-24 | Micron Technology, Inc. | Method and apparatus for programming anti-fuses using an isolated well programming circuit |
| US5859562A (en) * | 1996-12-24 | 1999-01-12 | Actel Corporation | Programming circuit for antifuses using bipolar and SCR devices |
| US5909049A (en) | 1997-02-11 | 1999-06-01 | Actel Corporation | Antifuse programmed PROM cell |
| JP4599059B2 (en) * | 2001-09-18 | 2010-12-15 | キロパス テクノロジー インコーポレイテッド | Semiconductor memory cell and memory array utilizing breakdown phenomenon of ultra-thin dielectric |
| US6700151B2 (en) * | 2001-10-17 | 2004-03-02 | Kilopass Technologies, Inc. | Reprogrammable non-volatile memory using a breakdown phenomena in an ultra-thin dielectric |
| US7057258B2 (en) * | 2003-10-29 | 2006-06-06 | Hewlett-Packard Development Company, L.P. | Resistive memory device and method for making the same |
| FR3085530B1 (en) | 2018-08-31 | 2020-10-02 | St Microelectronics Rousset | INTEGRATED CIRCUIT CONTAINING AT LEAST ONE MEMORY CELL WITH AN ANTI-FUSE DEVICE. |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4899205A (en) * | 1986-05-09 | 1990-02-06 | Actel Corporation | Electrically-programmable low-impedance anti-fuse element |
| JPH0817039B2 (en) * | 1988-08-19 | 1996-02-21 | 株式会社東芝 | Semiconductor memory cell |
| JPH0831564B2 (en) * | 1990-06-22 | 1996-03-27 | シャープ株式会社 | Semiconductor device |
-
1990
- 1990-06-22 JP JP16479890A patent/JPH0834292B2/en not_active Expired - Fee Related
-
1991
- 1991-06-18 US US07/716,785 patent/US5299151A/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007134373A (en) * | 2005-11-08 | 2007-05-31 | Nec Electronics Corp | Semiconductor device and fuse treatment method thereof |
| JP2012033221A (en) * | 2010-07-29 | 2012-02-16 | Renesas Electronics Corp | Semiconductor memory device and program method for anti-fuse |
| CN113872177A (en) * | 2021-10-14 | 2021-12-31 | 上海军陶科技股份有限公司 | Anti-reverse-filling circuit based on field effect transistor |
| CN113872177B (en) * | 2021-10-14 | 2022-08-16 | 上海军陶科技股份有限公司 | Anti-reverse-filling circuit based on field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0834292B2 (en) | 1996-03-29 |
| US5299151A (en) | 1994-03-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0461156A (en) | Writing method of semiconductor storage device | |
| US6069064A (en) | Method for forming a junctionless antifuse | |
| US5086331A (en) | Integrated circuit comprising a programmable cell | |
| US5301159A (en) | Anti-fuse circuit and method wherein the read operation and programming operation are reversed | |
| JPH0461155A (en) | Semiconductor device | |
| EP1459321A2 (en) | Reprogrammable non-volatile memory using a breakdown phenomena in an ultra-thin dielectric | |
| US5834813A (en) | Field-effect transistor for one-time programmable nonvolatile memory element | |
| US4573144A (en) | Common floating gate programmable link | |
| US4084108A (en) | Integrated circuit device | |
| JPS63140550A (en) | Elecric fuse for redundant circuit | |
| US20210143161A1 (en) | A novel antifuse OTP structure with hybrid junctions | |
| JP2859481B2 (en) | Non-volatile memory device | |
| JP2809162B2 (en) | Semiconductor device | |
| US5027186A (en) | Semiconductor device | |
| JP3221014B2 (en) | Semiconductor device | |
| JPH10222984A (en) | Structure of sram storing cell having n-channel thin film transistor load device and manufacture thereof | |
| US20040052148A1 (en) | Memory device that can be irreversibly programmed electrically | |
| JPH049388B2 (en) | ||
| JPH04162473A (en) | Semiconductor storage device | |
| JPS62128557A (en) | Semiconductor memory device and writing method thereof | |
| JPS622662A (en) | Semiconductor device and manufacture thereof | |
| JPS62143292A (en) | Semiconductor integrated circuit device | |
| JP2000049240A (en) | Semiconductor storage device | |
| JPH0855964A (en) | Apparatus for selecting design option in integrated circuit | |
| JPS63224355A (en) | Semiconductor storage device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080329 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090329 Year of fee payment: 13 |
|
| LAPS | Cancellation because of no payment of annual fees |