JPH0460596A - Processor for electronic musical instrument - Google Patents

Abstract

PURPOSE:To improve the ability as a sound source without depending upon sound source circuit hardware in exclusive structure by enabling plural CPUs to operate according to individual programs and to be put in partial charge of the generation processing of a musical sound signal. CONSTITUTION:This system has two central processing units, e.g. MCPU 10 and SCPU 20, which are stored with the programs respectively and operate according to the program. The MCPU 10 controls the whole system and controls the processing of input information besides part of sound source processing. The SCPU 20, on the other hand, it used exclusively for the remainder of sound source processing and DAC 100 which converts a digital musical sound signal into an analog musical sound signal. Thus, the CPUs include means having the CPUs which are so constituted to operate according to their programs and put in partial charge of respective parts of the generation processing of the musical sound signal according to the programs. Consequently, the processing unit for the electronic musical instrument which has the high musical sound generating ability corresponding to the number of CPUs is obtained without requiring the sound source circuit hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a processing device for an electronic musical instrument, and more particularly to the structural architecture of a processing device for an electronic musical instrument.

[Background of the invention] In recent years, electronic musical instruments have been computerized.

However, the part related to the generation of musical tones that requires large amounts of high-speed data processing is performed by dedicated hardware called a sound source circuit, and the microcomputer controls the musical instrument by inputting it from the control cap 1 or console panel. It merely processes MIDI and other external control inputs, inputs from internal or external performance memories, etc.) and transfers appropriate commands to the tone generator circuit.

There are several problems with the system architecture of electronic musical instruments, in which the musical tone generation capability is performed by sound source circuit hardware, and the processing of musical instrument control inputs is performed by a microcomputer. The first sound source circuit hardware requires a storage device for temporarily storing data and an arithmetic circuit for performing calculations at various stages of processing musical tone parameters, so the circuit size inevitably becomes large. Second, when changing the design of sound source circuit hardware, large-scale circuit changes are often necessary, requiring a great deal of development time and effort. Furthermore, the interface between the microcomputer and the sound source circuit hardware also needs to be reconsidered and redeveloped for each sound source circuit hardware.

For the above reasons, the present applicant proposed a processing device for an electronic musical instrument that can generate musical tones only by program control of a microcomputer without using sound source circuit hardware (Japanese Patent Application No. 334158/1982).

The embodiment of this application shows a configuration in which a single CPU executes a program to generate musical tones. In this case, it is necessary to increase the processing speed of the CPH in order to increase the musical tone generation ability. Unfortunately, since the processing speed of the CPU is limited by the operating speed limit of the semiconductor device used, there is a limit to the musical tone generation ability that can be achieved.

[Object of the Invention] Therefore, an object of the present invention is to provide a processing device for an electronic musical instrument that has a relatively high musical tone generation ability without using sound source circuit hardware.

[Structure and operation of the invention] According to the present invention, there is provided a plurality of CPUs configured such that each CPU operates with each program, and the plurality of CPUs are
There is provided a processing device for an electronic musical instrument, characterized in that the PU includes means for dividing and executing each section of musical tone signal generation processing according to the program.

According to this configuration, it is possible to obtain a processing device for an electronic musical instrument that has a high musical tone generation ability according to the number of CPUs without requiring conventional tone generator circuit hardware. Also,
The hardware of each CPU itself can be the same with no particular difference in structure, and basically only the programs executed by each CPU should be used that match the processing purpose of each CPU. This makes it easier to construct a system as a processing device for electronic musical instruments.

The means for executing musical tone signal generation processing in parallel can take various forms. In one embodiment, a plurality of CPUs are pipeline-coupled to perform parallel processing of musical tone signal generation. For example, the first CPU handles the first partial process of the entire process of musical tone signal generation, and the The CPU of
Each CPU handles the second partial process of the musical tone generation process in response to the processing results of the PU, and executes the process at predetermined intervals in order to maintain the sampling rate of musical tone output data. While a certain CPU is executing partial process j for the i-th musical tone data sample, the CPU next to this CPU
executes the partial process N+1) for the (i-1) lljth musical tone data sample. For pipeline coupled systems, processing time from pipeline inlet to outlet is often a problem, typically as a response delay. However, conveniently, when applied to electronic musical instruments,
A delay in response of several milliseconds is not a problem. Therefore, for example, if the sampling frequency of musical tone output data (corresponding to the execution interval of each CPU's partial processing) is set to 20K.
HzL, and assuming that the response delay in the pipeline is 1 millisecond, a maximum of 20 CPUs can be coupled in the pipeline.

Therefore, a configuration in which musical tones are generated by connecting a plurality of CPUs in a pipeline is effective when employing a musical tone synthesis method that has a complex musical tone synthesis algorithm and requires many processing steps. Furthermore, in this specific embodiment, when the musical tone signal generation processing consists of control processing and sound source processing for the entire system, the first CPU shares the control processing and the first part of the sound source processing, and the second CPU Now, it might be possible to share the rest of the sound source processing. Here, the sound source processing is divided and processed by two CPUs, but the second CPU
It is desirable that the processing performed by the PU be divided into parts that take a relatively long processing time, such as multiplication processing, and the first CPU, which also performs overall control processing, should be made to perform the remaining processing, which is relatively light in burden.More specifically, When sound source processing consists of envelope processing and waveform processing that adds this envelope, the first
The second CPU performs only envelope processing without multiplication processing, and the second CPU performs waveform processing that involves multiplication of envelope data obtained from the processing results of this envelope processing. In this way, each CP
Since the processing load placed on U is significantly reduced, the processing speed is increased and the musical tone generation ability is also increased.

Alternatively, the first CPU may perform only overall control processing, and the second CPU may be used exclusively for sound source processing. In this way, even when changing the sound source circuit, there is no need to change the hardware, and it is possible to easily support various electronic musical instruments.

As a preferable configuration example of the first and second CPUs, the plurality of CPUs include one main CPU and one main CPU.
The main CPU is configured to generate musical tones based on a processing result of the input to the musical instrument by an input device program and an input processing program for processing input to the musical instrument. MCPU program storage means for storing a musical tone generation program; MCPU address control circuit means for controlling an address of the MCPU program storage means; and MCPU address control circuit means for storing data necessary for input processing to the musical instrument and generation processing of the musical tones. MCPU data storage means and M that performs arithmetic processing
a CPU arithmetic processing circuit means, and an MCPU that decodes each instruction of a program in the MCPU program storage means to control operations of the MCPU address control circuit means, the MCPU data storage means, and the MCPU arithmetic processing circuit means;
operation control circuit means, and the sub-CP
Each of U includes an SCPU program storage means for storing a musical tone generation program for generating a musical tone based on a processing result of the input to the musical instrument by the input processing program of the MCPU program storage means, and the SCPU program storage means. SCPU address control circuit means for controlling the address of the CPU, SCPU data storage means for storing data necessary for the musical tone generation process, SCPU@arithmetic processing circuit means for performing arithmetic processing, and SCPU program storage means for performing arithmetic processing. The SCPU decodes each instruction of the program.
address control circuit means, said SCPU data storage means;
and SCPU operation control circuit means for controlling the operation of the SCPU arithmetic circuit means.

[Example 1 Hereinafter, the present invention will be described in detail with reference to the drawings.

Summary> This embodiment applies this invention to an electronic musical instrument6.
This embodiment (FIGS. 1-13) includes various features. The first feature is that multiple microcomputer processing units (
CPU), and there is no need for a conventional hardware sound source with a dedicated structure. One CPU works as the main CPU or master CPU (10), and handles not only part of the sound source processing but also the input devices (W1 board, function keys, etc.) according to the application (in this case, a musical instrument) (Figures 4 to 6). ), other CPUs are master CPUs
Sub CPU or slave CPU for U (20)
Acts as the remaining sound source processing, output wave a! 1 (DAC, etc.) (FIGS. 8 and 9), therefore, the burden of sound source processing is shared between each CPU.

The second feature is related to the mechanism by which the sub CPU starts and ends its operation, and according to this embodiment, the sub CPU
The operation starts when data for sound source processing is received from the master CPU using a timer interrupt that requests sound source processing from the master CPU, and as a result, sound source processing is performed in the master CPU and sub CPU. It is carried out in a divided manner. When the operation (sound source processing) of the sub CPU is completed, the sub CPU shifts to the reset state (stop state) according to the end signal, and the end signal is transmitted to the master CPU (Fig. 13).With this feature,
The master CPU can effectively manage and understand the operation periods and timings of the sub CPUs. Furthermore, this feature allows efficient execution of sound source processing tasks (generating digital samples of musical tone signals) that require high-speed processing.

The third feature of this embodiment is that the CPU external memory as a data source is shared by multiple CPUs.
According to this embodiment, by providing a memory device conflict avoidance circuit (50) to be described later, conflicts in access to the shared memory are resolved, and after a certain waiting time, the shared memory is Allows data to be retrieved from memory.

The fourth feature of this embodiment relates to speeding up data conversion processing (shifting, inversion, partial extraction, etc.).

Conventionally, in order to obtain data converted from data in a data memory such as the above-mentioned CPU external memory onto the CPU internal memory (computation memory), a transfer (read access) command is used to transfer the data in the data memory. is transferred to the arithmetic memory, and then the data in the arithmetic memory is converted via the ALU by a conversion instruction. It is also often necessary to execute multiple conversion instructions to effect the desired data conversion. As described above, there has been a problem in the past that data conversion processing takes time, which is a particularly serious problem in applications that require high-speed processing, such as sound source processing. To solve this problem, according to this embodiment, data ψ address conversion hardware (60
, 70) and executes a special transfer instruction (transfer with conversion instruction), the data that has been subjected to the desired data conversion via the data/address conversion hardware that responds to the instruction is transferred to the calculation memory ( 106, 206). Therefore, in order to obtain desired conversion data, it is sufficient to execute a single instruction instead of a plurality of instructions, and the processing speed can be increased.

Overall Configuration (Figure 1) Figure 1 is a block diagram showing the overall configuration of this embodiment configured as a processing device for an electronic musical instrument.
(denoted as U20).

Each CPU120 has a built-in program, and the 1MCPU10 that operates according to each program controls the entire system in addition to part of the sound source processing (Figs. 5 and 6). The SCPU 20 controls the processing of input information from connected input devices (for example, II board, function keys, etc.) (Fig. 4).In contrast, the SCPU 20 processes the remaining sound sources and converts digital musical tone signals into analog musical tone signals. (Figures 8 and 9).

A memory 90 serves as a data source for sound source control data, waveform data, and the like. The data memory 90 is an LSI
It consists of a ROM externally attached to a chip (which carries the remaining devices in Figure 1). If the degree of integration is high, data memory 90 can be formed as an internal memory on a single LSI chip. External memory 90 is MCPUI
It is shared by the CPU 20 and the SCPU 20. Address information from MCPUIO is transferred to address bus MA which couples to MCPUIO.
, the MCPU external memory address latch 30M of the external memory address latch 30, the address switching circuit 40, and the address conversion circuit 60 are applied to the address input of the external data memory 90. On the other hand, the address information from the SCPU 20 is sent to the address SA connected to the SCPU 20.
, the SCPU external memory address latch 305, the address switching circuit 40, and the address conversion circuit 60 to the address input of the external data memory 90. The data transmission path from the external data memory 90 to the MCPUIO is the data output of the external data memory 90 and the data conversion circuit 7.
0, external memory data latch 80, MCPU external memory data latch 80M, and data bus MD coupled to MCPUlo. On the other hand, the data transmission path from the external data memory 90 to the SCPU 20 includes the data output of the external data memory 90, the data conversion circuit 70. S
It is composed of a CPU external memory data raft 80S and a data bus SD coupled to the SCPU 20.

The memory device contention avoidance circuit 50 includes MCPUIO and SCPU.
This system controls access to the external memory 90 by both CPUs 20 and avoids conflicts. The memory device M contention avoidance circuit 5o controls the address switching circuit 40 to switch addresses in response to the signal roma requesting external memory access from the MCPUIO and the signal roma requesting external memory access from the SCPU. The circuit 40 is caused to select either the address from the MCPUIO or the address from the SCPU 20 as the address to the external memory 90. For this purpose, the address switching circuit 40 performs a selection operation in response to the selection signal MSEL from the memory device conflict avoidance circuit 50. When the address to the external memory 90 is determined, the memory device conflict avoidance circuit 50 sends a chip selection signal to the external memory 90. ~CE and output enable signal ~OE are activated. This causes data to be output from external memory 90 and appear on the input path of external memory latch 80 through data conversion circuit 70 . Here, the memory device contention avoidance circuit 50 sends data to the CPU that requested data access.
Either the external memory data latch 80M or the SCPU external memory data latch 80S is activated to latch data. For this purpose, MCPU external memory data latch 8
0M is the latch signal M from the memory device contention avoidance circuit 50
The SCPU external memory data latch 803 performs a latch operation based on the latch signal SDL from the memory device conflict avoidance circuit 50.

The address conversion circuit 60 and the data conversion circuit 70 convert the data of the external data memory 90 to the CPU101.
This is a conversion device for importing into 20. The address conversion circuit 60 is the address switching circuit 40.
The address passed through the CPU (MCPUIO or S
Address (logical address) output from CPU 20)
The data conversion circuit 70 selectively changes the data output from the external data memory 90 to form an address that is actually input to the external data memory 90. or SCPU2
0) forms the data that is actually input.

Control signals are used to specify the manner of conversion in each conversion circuit 60,70. In each CPU10120, data access to the external data memory 90 is performed by executing a transfer command. The control signals generated by the CPU based on the transfer command are transmitted to MHl, MR2, and MR.
3 (for MCPUIO), SR1, SR2, SR3 (
(in case of SCPU 20). These signals are sent to the external memory address switch 30 and the address switching circuit 4.
After passing through 0, the signals are called R1, R2, R3 (MR
i-LMRi→Ri or 5R5-+LSRi→Ri)
, control signals R1 and R2 are input to the address conversion circuit 60 in order to specify the manner of conversion. Furthermore, in order to specify the conversion mode in the data conversion circuit 70, a control signal R
1, R2, R3, address bit 12 signal A12 from address conversion circuit 60, and address bit 15 signal A
15 is added to the data conversion circuit 70. Details of the address conversion circuit 60 and data conversion circuit 70 will be described later.

To define the interface between MCPU lO and SCPU 20, a plurality of signals are transmitted between the two CPUs. Signal A is S sent from MCPUIO to SCPU20.
A signal indicating the start of processing rMI of the CPU 20, signal B is SC
A signal indicating the end of processing of the SCPU 20 sent from the PU 20 to the MCPUIO, Ma is a signal sent from the MCPUIO to the SCPU
The internal memory of the SCPU 20 (2 in FIG.
06) address information, signal C is from MCPUIO to SC
The read/write control signal for the internal memory of the SCPU20 sent to the PU20, Dour is sent from the MCPUIO to the SCPU2
0 to the internal memory of the SCPU 20.

As described above, the digital musical tone signal is generated by the sound source processing in the SCPU 20. The generated result is sent from the SCPU 20 to a digital-to-analog converter (DAc) ioo consisting of a right DAC 100K and a left DAC 100L, where it is converted into an analog musical tone signal and output to the outside.

<Configuration of MCPU and SCPU (Figures 2 and 3)> Figure 2 shows the internal structure of MCPUIO, and Figure 3 shows the configuration of SCPU2.
The internal structure of 0 is shown.

In FIG. 2, the control ROM 102 stores a main program for processing various control inputs of the musical instrument and an interwoven processing program for generating musical tones. Program words (commands) in
In the specific embodiment, the program word length is 28 bits, and part of the program word is located at the lower address of the address storing the program word to be read next. ROM address control unit 11 as part (intra-page address)
The next address method is entered in 4, but
A program counter method may be used instead, RA
When the operand of the instruction from the control ROM 102 specifies a register, the M address control unit 105 controls the RA
specifying the address of the corresponding register in M106;
The RAM 106 is a group of registers constituting a calculation memory, and is used for general-purpose calculations, flag calculations, musical tone calculations, and the like. The ALU section (addition/subtractor and logic operation section) 108 and multiplier 110 are used when the instruction from the control ROMIO 2 is an operation instruction.

In particular, the multiplier 110 is used to calculate musical waveforms, and as an optimization for this purpose, it multiplies the first and second data inputs (for example, 16-bit data) to obtain data of the same length (16 bits) as the input. It is designed to be output. Above RA
M106, adder/subtractor 108, and multiplier 110 constitute an arithmetic circuit. The operation control circuit 112 decodes the operation code of the instruction from the control ROM 102 and sends control signals (indicated by CNTR) to each part of the circuit in order to execute the instructed operation. In addition, when executing a conditional branch instruction, the operation 1 control circuit 112
detects the establishment of a branch condition based on the status signal S (for example, an overflow signal, a zero flag signal, etc.) from the ALU unit 108 and jumps the address to the branch destination address via the ROM address control unit 114.

In order to execute the musical tone generation program in the control ROM 102 at predetermined intervals, this embodiment employs timer interaction. That is, the interwoven generation section 116 having a timer (hardware counter) sends the control signal IN to the ROM address control section 114 at regular intervals.
T (interrupt request signal) is sent, and in response to this signal, the ROM address control unit 114 saves (holds) the address of the next main program instruction, and returns the address to the beginning of the interwoven processing program (subroutine) in which musical tones are generated. Set the address instead. This starts the interwoven processing program. Since there is a return instruction at the end of the interwoven processing program, when this return instruction is decoded by the operation control circuit 112, the ROM address control section 114 sets the saved address again and returns to the main program. . Furthermore, the control signal INT from the interwoven generator 116 is D.
It is supplied to the DAC 100 in order to determine the digital/analog conversion sampling rate of the musical tone signal in the AC 100. Note that the interacted generation unit 116 is M in the diagram.
Internal CPUIO? Although this is a basic drawing, the MCPU
It requests special processing by stopping the work currently being performed on the IO, and is logically an external element (peripheral device I) of the MCPU lO.

The clock generation circuit 136 is a master clock generation circuit (
2-phase master clocks CKI and CK from (not shown)
2, various timing signals (T1, T2) are applied to each part of the circuit including the operation control circuit 112.
, T3, TlCK1, T2CK2, T3CK3, etc.).

The remaining elements in FIG. 2 relate to the MCPU 20's interface with external devices. 122 represents a gate as a path interface for connecting the MCPU internal bus to the external memory access address MA (FIG. 1), and 124 represents a gate for connecting the MCPU internal bus to the external memory data bus MD. Express, also enter capo
) 118 and the output port are interfaces for coupling the MCPU internal path to external human powered devices. 128 is a game for connecting the MCPU internal path to the SCPU internal RAM addressing path) 130 is the SCPU internal R
Represents a gate for connecting the MCPU internal path to the AM write data bus.

The SCPU reset control unit 134 is a device for managing the operating period of the SCPU 20. According to this embodiment, the SCPU reset control control unit 4 is
In response to the interwoven signal INT from 16, the SCP
A signal A indicating the start of processing of U20 is generated. This signal A
is sent to the ROM address control section 214 (FIG. 3) of the SCPU 20, thereby starting the address updating operation of the ROM address control section 214, and the operation of the SCPU 20 (including sound source processing) starts. When the operation of the SCPU 20 is completed, a signal B indicating the completion of processing is generated from the operation control circuit 212 of the SCPU 20, and this signal B is sent to the SCPU 20.
It is sent to the reset control section 134. On the other hand, SCP
The U reset control unit 134 inverts the signal A to stop the operation of the SCPU 20, thereby causing the R of the SCPU 20 to stop.
An SCPU that stops the operation of the OM address control unit 214 and indicates that the SCPU 20 is stopped.
A status flag signal is sent to operation control circuit 112. Operation control circuit! 12 is a control ROM 102
When executing an instruction to check the SCPU state from
By reading the U status flag signal, the status of the SCPU 20 can be detected.

In the block diagram of the SCPU 20 in FIG.
2.202a, 204.205.206.208.21
2.214.222.224.236 are the second
Element 102.1 in the block diagram of MCPUIO in FIG.
02a, 104.105.106.108.110.1
This is an element corresponding to 12.114.122.124.136. However, the control ROM 202 of the SCPU 20 basically stores only programs for sound source processing, making the SCPU 20 function as a processing device dedicated to sound source processing.

126 represents a gate for connecting the SCPU internal path to the DAC data transfer path.

240 is RAM 2 as a calculation memory for the SCPU 20
The data input to 06 is the data from MCPUlo (M
From CPUIO to gate 130, data bus D our
This is a RAM data-in switching unit that selects between data (data passed through the RAM) and data generated (computed) by the SCPU 20 (data on the data bus DB from the ALU unit 208 or the multiplier 210). RAM data-in switching section 240
Its selection mode is controlled by signal A, and when signal A indicates "SCPU 20 in operation", SCP
The data calculated by U20 is selected, and the signal A is “SCPU
20 "Stopping", data from MCPUIO is selected.

The mode of the RAM address control unit 204 is also controlled by the signal A, and when the signal A indicates "SCPU 20 in operation", the RAM address control unit 204 inputs the information on the path SA from the instruction output latch 202a of the control ROM.
Selected as the address of AM206, signal A is “SCP
When "U20 is stopped" is displayed, information from the MCPUIO on the path Ma is transferred from the MCPUIO to the RAM 20 via the pass gate 128 (opened by signal A).
Select it as address 6. Similarly, the mode of the write signal switching unit 242 is controlled by the signal A,
When the signal A indicates "SCPU 20 is operating", the RAM read/write signal from the operation control circuit 212 of the SCPU 20 is selected and coupled to the read/write manual R/W of the RAM 206, and the signal A indicates "SCPU 20 is operating".
When "stopped" is displayed, S is sent from the operation control circuit l12 of the MCPUIO instead of the SCPU20.
Select CPURAM read/write signal and write to RAM206
Connects to read/write manual R/W.

Below, various features of this embodiment will be explained in more detail.

<Explanation of CPU operation> Figure 4 is a flowchart showing the operation of MCPUIO by the main program (pack ground program) of MCPUIO, and Figures 5 and 6 are the interwoven processing routine of MCPUIO activated by the timer interwoven signal INT. FIGS. 8 and 9 are flowcharts showing the operation of the SCPU 20 according to the program of the SCPU 20 activated by the operation start signal A from the MCPUIO.

As described with reference to FIGS. 1 to 3, the electronic musical instrument processing system of this embodiment includes a plurality of CPUs consisting of the MCPU 10 and the SCPU 20, and both CPUs cooperate to perform processing for the electronic musical instrument. Execute. Especially MCPUIO,
In this embodiment, FIG.

A part of the sound source processing is performed by an interwoven processing routine as shown in FIG. 6, and the SCPU 20 performs the remaining sound source processing by a program shown in FIGS. 8 and 9.
Furthermore, the MCPUIO executes various tasks for controlling the entire system using the main program shown in FIG.

In the flow of the main program shown in Figure 4, 4-1 is a process to initialize the system when the power is turned on, and MC:
PUIO clears RAM 106 and RAM 206, sets initial values such as rhythm tempo, etc., and MCP at 4-2.
The UIO outputs a signal for key scanning from the output port 120 and captures the states of input devices such as the keyboard and function switches from the input port 118, thereby storing the states of the function keys and keyboard keys in the key buffer area of the RAM 106. do. In 4-3, the function key whose state has changed is identified from the new state of the function key obtained in 4-2 and the previous state,
Execute the instructed functions (for example, set musical tone numbers, set envelope numbers, set rhythm numbers, etc.).In 4-4, based on the latest and previous states of the keyboard obtained in 4-2, 0 to identify changed II (key press, key release)
In the next 4-5, from the processing result of 4-4, sound generation control processing 4-
In 4-6, when a demo performance key is pressed using a function key, demo performance data (sequencer data) is sequentially read out from the external memory 90 and processed, thereby performing sound production control processing. In 4-7, when the rhythm start key is pressed, rhythm data is sequentially read from the external memory 9o, and key assignment processing for 4-9 is performed. , flow-period timer processing 4-8, in order to know the timing of events required in the main flow,
Flow-Identical Time (This is obtained by counting the number of timer interrelated operations executed during one cycle of the flow. This counting process is performed in Interrelated Timer Processing 5-5, which will be described later.
It is done in 2. ) to obtain reference values for the envelope timer (envelope calculation cycle) and rhythm. In the 0 sound control process 4-9, the actual value is calculated from the data set in 4-5.46.4-7. Various calculations are performed to generate musical tones, and the results are set from the sound source processing register in RAM 106 (FIG. 7) to the sound source processing register in RAM 206 (FIG. 11). Specifically, address addition I1. is stored in the sound source processing register in the RAM 106 of the MCPUIO shown in FIG. SC whose loop address, end address and start address are shown in Figure 11.
It performs the operation of setting the sound source processing register in 206 of the PU 20. This MCPUIO can generate musical tone data for 8 channels, and these data are 4-
1 MCPU based on the data assigned in steps 5 to 4-7
l0. It is assigned to a corresponding channel in each register of SCPU 20. The address addition value, loop address, end address, and start address are address information for the basic waveform stored in the external memory 90, and the start address is the basic waveform memory (external memory 90
The start address and loop address (in Figure 1O) are the return address when repeatedly reading out the basic waveform (same as the start address in Figure 1O), the end address is the end address of the basic waveform, and the current address is the current address of the basic waveform. It is an address that represents the phase, and its integer part is
It represents the storage location that actually exists in the basic waveform memory, its fractional part represents the deviation from this storage location, and the address addition value is the value that is added to the current address at each time interval of the timer-interrupted processing routine. and is directly proportional to the pitch of the musical tone being generated.

4-10 is a preparation process for the next main flow pass, and NEW indicating the change to the key press state obtained in this pass.
Processes such as changing the ON state to ON or changing the NEW OFF state indicating a change to the key released state to OFF are performed.

The interwoven signal INT from the interwoven generation section 116
When this occurs, the MCPUIO interrupts the main program being executed and executes the interwoven processing routine shown in FIG. Here, the MCPUIO generates musical tone signal data in the flows shown in FIGS. 5 and 6, and the SCPU 20 generates musical tone signals based on the data from the MCPUIO in the flows shown in FIGS. 8 and 9. There is.

Detailed explanation of the flow shown in Fig. 5. Held, MCPUIO
is configured to be able to output 8 channels of musical sound data,
5-1, first, the current envelope value data of each channel in the sound source processing register (FIG. 7) of the RAM 106 of the MCPUIO is transferred to the register of the RAM 206 of the SCPU 20 (FIG. 11). A pulsed write signal C is outputted from the MCPUIO to the SCPU 20 in accordance with the timing of this data transfer. When this data transfer is completed, the MCPUIO outputs an operation start signal A that starts the operation of the SCPU 20 (5-2).

Thereafter, in steps 5-3 to 5-10, sound source processing for each channel from the first channel to the eighth channel, that is, processing to create envelope data and store it in the sound source processing register in the RAM 106 is executed.

After this, return to the main routine again.

FIG. 6 shows a detailed flow of channel storage processing in steps 5-1 to 5-8 in FIG. (For example, FM synthesis is also possible, and the present invention is not limited to a specific musical tone synthesis method.) In this process, envelope data is created and stored in the sound source processing register of the RAM 106. There is. To execute this process, as shown in FIG. 7, a group of registers in the RAM 106 of the MCPUIO stores an envelope data timer, a target envelope, an envelope ΔX, an envelope with an addition/subtraction flag, and a current envelope.
This desired register is operated and updated. The envelope should be added to the basic waveform for amplitude modulation, and consists of several segments (steps) as a whole. Envelope ΔX timer, target envelope, envelope ΔX, and envelope Δy with addition/subtraction flux are envelope parameters that define the currently ongoing envelope segment, and this envelope parameter is M
In the sound generation control processing 4-9 of the CPUIO main program (Fig. 4), this information is updated each time the envelope value reaches the target value of the segment, and in the interconnected processing routine (Fig. 5), these envelops are updated. The bellows parameters are only referenced except for the envelope ΔX timer. The envelope ΔX represents the calculation cycle of the envelope, the target envelope represents the target value of the envelope in the current segment, the envelope Δy with addition/subtraction flag represents the change in the envelope for each calculation cycle, and the current envelope represents the current envelope value. To describe in detail the flow shown in FIG.
When it matches with perform subtraction or addition, 6
-6 checks whether the current envelope has reached the target envelope value, and if so, sets the current envelope to the target level in step 6-7.

As a result, the data of the next envelope step is saved at the output J[4-9 of the main program. Further, when the current envelope of zero is read in output processing 4-9, it is processed as the end of the sound generation. 6 more after this
The current envelope value generated at -8 is stored in the corresponding channel area in the sound source processing register of the RAM 106.

FIG. 8 shows the flow of the interwoven processing routine of the SCPU 20. This routine starts in synchronization with the generation of the signal A output in the flow of FIG.

7-1 is the RAM area for waveform addition (inside RAM106, RAM
M206) is cleared, and sound source processing for each channel from the first channel to the eighth channel is sequentially executed in steps 7-2 to 7-9. At the end of each channel sound source processing, the tone waveform value of the channel is added to the data in the waveform addition RAM area. After this, in 8-10, the RAM for waveform addition
The operation control circuit 212 outputs the end signal B at 8-11.

This signal B is the SCPU reset cap 13 of the MCPUIO.
4 and stop the output of signal A. As a result, S
The operation of the CPU 20 is stopped.

FIG. 9 shows a detailed flow of the sound source processing for each channel in FIG. It adds an envelope function based on envelope data. The waveform processing here uses the integer part of the current address to read the waveform data of two adjacent addresses from the basic waveform memory, and calculates the expected waveform value for the current address indicated by (integer part to decimal part). The reason why 8-interpolation is necessary is that the waveform sampling period by timer interpolation is constant, and the address addition value (pitch data) spans a certain range for application to musical instruments (scale tones). (If you prepare waveform data for each scale note on an instrument that only outputs the sound, there will be no need for interpolation, but it will increase the storage capacity into an unacceptable amount.) Since the deterioration and distortion of the timbre due to interpolation are more pronounced in the high range, it is necessary to record the original sound. It is preferable to reproduce the original sound at a cycle faster than the sampling cycle. In this embodiment, the cycle for playing the original sound (4-4) is doubled (10th
), Therefore, when the address addition X value is 0.5, A
4 sounds can be obtained. In this case, A#4
Then, the address addition value is 0.529, and when it is A3,
It becomes l.

These address addition values are stored as pitch data in the control data/waveform external memory 90, and when a key is pressed, they are selected as beef thousand data corresponding to the key in the output process 4-9 as described above. The waveform start address, waveform end address, and waveform loop address of the selected tone are transferred to RAM 106, and from RAM 106 to RAM2.
06(7) Set in the corresponding registers, ie, address addition value register, start address/current address register, end address register, and loop address register.

For reference, in FIG. 10, which shows interpolated waveform data with respect to time, white circles indicate waveform data values stored at storage locations in the basic waveform memory, and X marks indicate output samples containing interpolated values.

There are various interpolation methods, but here we use linear interpolation. In detail, first, in 9I, an address addition value is added to the current address to obtain a new current address. Compare the current address and end address in 9-2, and if the current address > end address, use 9-3.9-4. If the current address is less than the end address, use 9-5 to determine whether the The next logical (operational) address is calculated, and the basic waveform memory is accessed using the integer part at 9-7 to obtain the next waveform data. The loop address is operationally the next address after the end address.

That is, in the 1011th case, the illustrated waveform is repeatedly read out. Therefore, when the current address = end address, read the waveform data of the loop address as the next address (9-6), access the basic waveform with the integer part of the current address by 9-8.9-9, and read the waveform data of the loop address as the next address (9-6). Read the waveform data 0 Next, in steps 9-10, subtract the current waveform value from the next waveform value, in steps 9-11, multiply the difference by the decimal part of the current address, and use the result as the current waveform value in steps 9-12. The linear complement of the waveform is obtained by adding F! Find the Jff value. This linearly interpolated data is multiplied by the current envelope value to obtain the musical tone data value of the channel (9-13), and it is added to the contents of the waveform addition register to accumulate the musical tone data (9-14). The digital musical tone data accumulated in the register is sent to 8-1O-cDAcloo of the SCPU interwoven processing routine (FIG. 8). Related to this! ! In Figure 1, DACloo consists of a right DAC 100R and a left DAC 100L to obtain a stereo output. In this case, it is preferable to decide which of the left and right DACs to assign each of the sound source channels processed by the SCPU 20. Specifically, the sound source data for each channel is stored on the internal RAM 206 as the selected DAC.
In addition, two waveform addition areas are provided, namely, a left DAC waveform addition area and a left DAC waveform addition area. In addition, in the step corresponding to 8-1, each waveform addition area for the left and right DACs is cleared, and after the processing in 9-13, the DAC assigned to the processing channel is determined from the selected DAC instruction data, and the corresponding Add the musical waveform data of the processing channel to the waveform addition area. Then, in a step corresponding to step 8-10 of the interwoven processing routine of the SCPU 20 (FIG. 8), the musical waveform data for the left DAC and the right DAC, which are the addition results, are added to the 5-
In step 5, the signals are sent to the left DAC 100L and right DAC 100R, respectively.

FIG. 12 shows an example of the configuration of the DAC shown in FIG.

In this embodiment, DAcloo converts the digital musical tone signal generated by the SCPU 20 into an analog musical tone signal. As shown in 8 to 10 of FIG.
is executed by the SCPU in the timer-interrupted processing routine.
The sample of the digital musical tone signal generated by DAC 1
Set to 00. The execution interval of this process 8-10 is on average equal to the generation interval of the interwoven signal INT generated by the timer interwoven generation section 116, but the actual execution interval varies due to the program operation. Therefore, if D/A conversion is performed with the execution interval of process 8-10 as the conversion period of D/A conversion, a large distortion will occur in the analog tone signal.

This problem can be solved by adopting a configuration as shown in FIG. That is, the operation control circuit 112
An interlaced signal, which is a precise timing signal from the interlaced generator 116, is connected between the soft control latch 1004 controlled by a program control signal from the interlaced generator 116 and the D/A converter 1002 that converts the digital musical tone signal to an analog musical tone signal. An interlaced control latch 1006 controlled by INT is provided. The generation period of the interwoven signal follows the stability of the clock oscillator, so it is extremely stable. The output of latch 1006 is switched in synchronization with the timing of the interlaced signal. That is, the generation period of the interwoven signal becomes the conversion (sampling) period of the D/A converter 1002. Therefore, the timing at which the error and chi 1004 outputs switch varies according to the timing deviation of the interwoven processing, but since there is a latch 1006 that operates with the interwoven signal, the timing at which the λ data of the D/A converter 1002 switches is the same as the interwoven signal. Synchronize. Accordingly, the above-mentioned FIG. 13 is a time chart showing the flow of the operation of this embodiment along the flow of time. As can be seen from this figure, when the interwoven signal INT is generated, the MCPUIO interrupts execution of the main flow and executes the interwoven processing routine. Here, data is first transferred to the SCPU 20, and when this data transfer is completed, an operation start signal A is output to the SCPU 20.

After that, the SCPU 20 performs envelope processing.
receives the signal A and performs processing of waveform data pitch interpolation and envelope multiplication, and when the processing is completed, it enters a standby state.

In this way, the electronic musical instrument processing device of this embodiment is an MCPU.
It has a plurality of IO and SCPU20 (5) CPUs,
Sound source processing for one sound can be divided and executed by each CPU according to a built-in program. Although one SCPU is used in the embodiment, a plurality of SCPUs that perform sound source processing may be provided.

[Modifications] This concludes the description of the embodiments, but various modifications and changes are possible within the scope of the present invention.

For example, in the above embodiment, the sound source processing for one sound is performed by the MCPUIO, the envelope processing is performed by the SCPUIO, and the SCPU
20 is responsible for waveform processing, but it is also possible to change the responsibility of each CPU to MCPUIO, which handles only overall control of the system, and SCPU 20, which handles all sound source processing.

FIG. 14 to FIG. 17 show a flowchart and a time chart showing the operation of this modification.

What is characteristic here is that only the SCPU 20 performs sound source processing, and the MCPUIO performs overall control processing such as key scanning, accompaniment pattern generation, and channel assignment. The MCPUIO performs these overall control processes in the main flow, and in the interwoven processing routine performed when an interwoven signal is generated, data is transferred from the MCPUIO to the sound source processing register (Fig. 18) in the RAM 206 of the SCPU 20. . Furthermore, this data transfer is performed only when necessary, such as when the value of the data has changed compared to previously transferred data.

FIG. 14 is a diagram illustrating the main flow of MCPUIO, in which the same steps as in FIG. 4 are given the same numbers as in FIG. 4 and their explanations are omitted.

In the sound generation control process of step 4-9, after the necessary data is stored in the area of the RAM 106 corresponding to each channel, in step 14-1, among these data, for example, data that has changed compared to the previously transferred data is stored. It is determined whether there is data to be transferred to the SCPU 20.

Here, if it is determined that there is, a transfer flag is set in 14-2, and if it is determined that there is no transfer, the transfer flag is reset in 14-3, and the process moves to 4-1O. The operation of this flow continues until the interwoven signal INT is generated, and when the signal INT is generated, the process moves to the MCPU interwoven processing routine.

FIG. 15 shows the flow of the MCPU interwoven processing routine.

First, in step 15-1, it is determined whether the operation of the SCPU 20 has been completed. Specifically, it is determined whether the operation start signal A is output from the MCPUIO. If the signal A is generated, it waits at this step, and if the signal A is not generated, the next step is performed. Step 1
The process proceeds to 5-2. In 15-2, it is determined whether the above-mentioned transfer flag is set. If set, data necessary for sound source processing (for example, modulation data from a modulation wheel, etc.) is transferred to the SCPU 20 in step 15-3, and then the transfer flag is reset (step 15-4).

If it is determined in 15-2 that the transfer flag has been reset, steps 15-3 and 15-4 are not performed, and in the next step 15-5, the SCPU 20
The signal A for starting the operation is output to , and the process returns to the main routine.

The SCPU 20 starts operating upon receiving an operation start signal from the MCPUIO. FIG. 16 is a flowchart showing the operation of this SCPU 20. First, at 16-1, musical tone signal data is generated based on the data transferred from the MCPUIO and output to the DACI OO. This is performed, for example, by combining the flowcharts of FIGS. 6 and 9. And after this, at 16-2,
Sends operation end signal B to MCPUIO. MCPUI
O receives this signal B, stops signal A, and sends SCPU2
Stop the operation of 0.

FIG. 17 is a time chart showing the flow of operation of this modification. As can be seen from this figure, the MCPUIO executes the interwoven flow by generating the interwoven signal INT, and during the operation, transfers data to the SCPU 20 and instructs the SCPU 20 to start the operation. SCPU2
0 starts its operation in response to this operation start instruction, generates musical tone data, and sends the data to the DAC 100. DAC
loo is configured to D/A convert and output the musical tone generation data from the SCPU 20 when an interwoven signal is generated thereafter. In addition, in this modification, MCP
Although all data is transferred from the MCPU to the SCPU in the UIO interwoven processing routine, the data may be transferred during the main flow operation period of the MCPU while the SCPU is not operating, as in the above embodiment.

In this manner, in this modification, the MCPUlo performs the overall control processing, and the SCPU 20 performs the sound source processing, and so on. For this reason, the sound source that used to be made up of hardware is now made up of a single CPU, making it extremely easy to change the characteristics of the sound source.
Moreover, even when using it as a sound source for other musical instruments, it can be easily done without changing the hardware configuration. Further, although only one SCPU is used here, it goes without saying that it is possible to provide a plurality of SCPUs for processing a plurality of sound sources.

[Effects of the Invention] Finally, the effects and advantages of the invention described in the claims will be described.

According to the structure of claim 1, since the plurality of CPUs operate according to respective programs and share each part of the musical tone signal generation processing, it is possible to use the CPU as a sound source without relying on the conventional dedicated sound source circuit hardware. It is possible to provide a processing device for an electronic musical instrument with high performance. Additionally, additions and changes to the functions of the device can be basically accomplished by changing the programs executed by each CPU, and do not require major changes to the hardware circuitry.

According to the configuration of claim 2, in addition to the above-mentioned effects, there is also an advantage that the amount of access between multiple CPUs (which leads to a decrease in system operating efficiency) can be minimized, and the use of a single main CPU allows the system to The advantage is that control becomes easier, the hardware of each CPU can be configured with similar circuits, and the programs built into each CPU can be used as common as possible.As a result, the system construction of processing equipment for electronic musical instruments is easy There are advantages such as ease of use.

Further, according to the configuration of claim 3, the main CPU performs the first process, which is the first part of the musical tone generation process, and the sub CPU performs the remaining process, the second process. Therefore, even if the tone synthesis algorithm is complex and requires many processing steps, the burden on each CPU is lightened, making it possible to generate a wider variety of tone signals.

Further, according to the configuration of claim 4, the main CPU performs the overall control processing and part of the sound source processing, and the sub CPU performs the remaining sound source processing, so that the sound source processing does not require an extremely large number of processing steps. In this case, an excessive burden is not placed only on the sub-CPU, the processing time is shortened, and the musical tone generation ability is improved.

According to the structure of claim 5, when the sound source processing consists of envelope processing and waveform processing with envelope addition (multiplication processing), the main CPU performs the envelope processing, and the sub CPU performs the waveform processing with multiplication processing. As a result, waveform processing that involves multiplication processing, which takes time, is processed by a dedicated sub-CPU, so neither CPU is overly burdened, and as a result, the time required for musical tone generation processing is shortened. Become.

Furthermore, according to the configuration of claim 6, since the sub-CPU is used exclusively for sound source processing, even when trying to change the characteristics of the sound source, the manner in which musical sounds are generated can be easily varied without changing the hardware configuration. It can be used with a variety of electronic musical instruments.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of an electronic musical instrument processing device to which the present invention is applied. FIG. 2 is a block diagram of the MCPU shown in FIG.
Figure 4 is a flowchart of the main program executed by the MCPU; Figure 5 is a flowchart of the interwoven processing routine executed by the MCPU; Figure 6 is a detailed flowchart of the channel processing in Figure 5; Figure 7 is a diagram showing the RAM table for sound source processing by the MCPU, Figure 8 is a flowchart of the processing routine executed by the SCPU, Figure 9 is a detailed flowchart of each channel processing in Figure 8, and Figure 10 is a diagram showing the waveform data. Figure shown. FIG. 11 is a diagram showing the RAM table for sound source processing of the SCPU, and FIG. 12 is a configuration diagram of the DAC. FIG. 13 is a time chart showing the operation of the embodiment over time; FIG. 14 is a flowchart of the main routine of the MCPU in a modification of the present invention; FIG. 15 is a flowchart of the MCPU's interactive processing routine in the modification Flowchart, FIG. 16 is a flowchart of the processing routine of the SCPU in the modified example, FIG. 17 is a time chart showing the operation of the modified example over time, and FIG. 18 is the RAM for sound source processing of the SCPU in the modified example.
It is a figure showing a table. lO...MCPU (main CPU) 20...
...SCPU (sub CPU) 102... Control ROM (MCPU program storage means) 106... RAM (MCPU data storage means)
108... ALU unit (MCPU arithmetic processing circuit means) 110... Multiplier (MCPU arithmetic processing circuit means) 112... Operation control circuit (MCPU
operation control circuit means) 114...ROM address control unit (MCPU address control circuit means) 202...control ROM (SCPU program storage means) 206...RAM (SCPU data Storage means) 208... ALU unit (S CPU arithmetic processing circuit means) 210... Multiplier (SCPU arithmetic processing circuit means) 212... Operation control circuit (SCPU
operation control circuit means) 214...ROM address control section (SCPU address control circuit means)

Claims (6)

[Claims] (1) It has a plurality of CPUs, each of which is configured to operate according to a respective program, and each of the plurality of CPUs includes means for dividing and executing each part of the musical tone signal generation process according to the program. Characteristic processing device for electronic musical instruments. (2) In the processing device for an electronic musical instrument according to claim 1, the plurality of CPUs include one main CPU and one main CPU.
It consists of at least one sub-CPU controlled by the main CPU, and the main CPU generates musical tones based on the processing results of the input to the musical instrument by an input device program for processing input to the musical instrument and an input processing program. MCPU program storage means for storing a musical tone generation program for the musical tones; MCPU address control circuit means for controlling the address of the MCPU program storage means; and MCPU address control circuit means for storing data necessary for input processing to the musical instrument and generation processing of the musical tones. MC to do
PU data storage means, MCPU arithmetic processing circuit means for performing arithmetic processing, and the MC
MCPU operation control circuit means for decoding each instruction of the program of the PU program storage means to control the operations of the MCPU address control circuit means, the MCPU data storage means, and the MCPU arithmetic processing circuit means; Each of the CPUs includes: an SCP that stores a musical tone generation program for generating musical tones based on processing results of inputs to the musical instrument by the input processing program of the MCPU program storage means;
U program storage means, SCPU address control circuit means for controlling the address of the SCPU program storage means, and S for storing data necessary for the musical tone generation process.
CPU data storage means, SCPU arithmetic processing circuit means for performing arithmetic processing, and the SC
SCPU operation control circuit means for decoding each instruction of the program of the PU program storage means and controlling the operations of the SCPU address control circuit means, the SCPU data storage means, and the SCPU arithmetic circuit means. Processing device for electronic musical instruments. (3) In the processing device for an electronic musical instrument according to claim 2, the main CPU performs a first process that is the first part of the musical tone signal generation process, and the sub CPU receives the processing results of the main CPU. A processing device for an electronic musical instrument, characterized in that it performs second processing, which is the remaining part. (4) In the processing device for an electronic musical instrument according to claim 3, the first process is a process including control processing of the entire system and a part of sound source processing, and the second process is a process of the first part. 1. A processing device for an electronic musical instrument, characterized in that the processing device performs sound source processing that receives a processing result from the sound source processing in the above. (5) In the electronic musical instrument processing device according to claim 4, the sound source processing includes envelope processing and waveform processing with envelope addition, the first processing includes the envelope processing, and the second processing includes the envelope processing. A processing device for an electronic musical instrument characterized by including this waveform processing. (6) In the electronic musical instrument processing device according to claim 3,
A processing device for an electronic musical instrument, wherein the first process is a control process for the entire system, and the second process is a sound source process.