JPH0459785B2 - - Google Patents
Info
- Publication number
- JPH0459785B2 JPH0459785B2 JP61069634A JP6963486A JPH0459785B2 JP H0459785 B2 JPH0459785 B2 JP H0459785B2 JP 61069634 A JP61069634 A JP 61069634A JP 6963486 A JP6963486 A JP 6963486A JP H0459785 B2 JPH0459785 B2 JP H0459785B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- semiconductor region
- semiconductor
- carriers
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 98
- 239000000969 carrier Substances 0.000 claims description 23
- 230000004888 barrier function Effects 0.000 claims description 15
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 13
- 238000010586 diagram Methods 0.000 description 9
- 239000012535 impurity Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910001425 magnesium ion Inorganic materials 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000032258 transport Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
- H01L29/7373—Vertical transistors having a two-dimensional base, e.g. modulation-doped base, inversion layer base, delta-doped base
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、改善された特性を有する半導体装置
に関する。特に半導体表面に誘起された空乏ない
しは反転層をベースとするトランジスタに関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device with improved characteristics. In particular, it relates to transistors based on depletion or inversion layers induced on the semiconductor surface.
従来、反転層をベースとするトランジスタは、
たとえば、第45回応用物理学会学術講演会講演番
号14p−Ａ−３に発表されているが、第１図に示
すように、第１の半導体領域１０の表面にトンネ
ル可能な程薄い絶縁膜２０を設け、更に金属電極
３０を設けた構造において、金属電極３０にバイ
アスを印加して生ずる反転層をベースとし、この
反転層の電位を制御するためにベースコンタクト
領域４０を設けたものである。
Traditionally, transistors based on inversion layers are
For example, as announced in the 45th Japan Society of Applied Physics Academic Conference Lecture No. 14p-A-3, as shown in FIG. In this structure, an inversion layer is formed by applying a bias to the metal electrode 30, and a base contact region 40 is provided to control the potential of the inversion layer.
このトラジスタは金属電極３０をエミツタ、第
１の半導体領域をコレクタとして動作するが、エ
ミツタからのキヤリアのベース領域への注入は
SiO2でのキヤリアのFowler−Nordheimトンネ
ルを用いているので、動作電流密度が小さく、し
かも経時変化を生じ易かつた。電流密度が小さい
ことは高集積のLSIにおける単位ゲート、セル等
には有効であるが、負荷容量の大きい負荷を高速
に充放電することができなかつた。
This transistor operates with the metal electrode 30 as an emitter and the first semiconductor region as a collector, but carriers from the emitter are not injected into the base region.
Since the carrier Fowler-Nordheim tunnel in SiO 2 was used, the operating current density was low and it was easy to change over time. A low current density is effective for unit gates, cells, etc. in highly integrated LSIs, but it has not been possible to rapidly charge and discharge loads with large load capacities.
本発明は、これらの問題点を解決するためにな
されたもので、エミツタからのキヤリアの注入機
構として禁制帯内を輸送するトンネルでなく、伝
導帯ないしは価電子帯を通してキヤリアを輸送す
る機構をとることを特徴とする。 The present invention was made to solve these problems, and uses a mechanism for transporting carriers through the conduction band or valence band instead of a tunnel that transports them within the forbidden band as a mechanism for injecting carriers from the emitter. It is characterized by
この機構は、以下の材料的、電子的組合わせに
よつて実現される。すなわち、第１の導電形の第
１の半導体領域と、該第１の半導体領域と接し、
第１の半導体の少数キヤリアに対して障壁を形成
する第２の半導体領域と、該第２の半導体領域と
接する導電領域と、第１の半導体領域と第２の半
導体領域との界面に動作状態で形成される空乏な
いし反転層とからなり、上記導電領域から第２の
半導体領域の伝導帯ないしは価電子帯を通してキ
ヤリアが輸送され、前記反転層を通過して第１の
半導体領域に到達することにより、前記導電領域
をエミツタ、前記空乏ないし反転層をベース、前
記第１の半導体領域をコレクタとして動作する半
導体装置。
This mechanism is realized by the following material and electronic combinations. That is, a first semiconductor region of a first conductivity type, in contact with the first semiconductor region,
a second semiconductor region forming a barrier to minority carriers of the first semiconductor; a conductive region in contact with the second semiconductor region; and an operating state at the interface between the first semiconductor region and the second semiconductor region. carriers are transported from the conductive region through the conduction band or valence band of the second semiconductor region, pass through the inversion layer, and reach the first semiconductor region. A semiconductor device that operates with the conductive region as an emitter, the depletion or inversion layer as a base, and the first semiconductor region as a collector.
本発明の動作を実現するためには、導電領域か
ら有意の数のキヤリアが第２の半導体領域の伝導
帯、価電子帯に励起される必要がある。このため
には、導電領域のフエルミレベルと第２の半導体
領域の伝導帯又は価電子帯のエネルギレベルとの
差ΔEiが20KT以内である必要がある。これは室
温で0.52eVであり77〓で0.13eVである。これに
対して第１の半導体領域と第２の半導体領域の界
面に第２の半導体領域によつて形成される少数キ
ヤリアに対するエネルギバリアの高さΔEBは、
ΔEiより大きいことが注入効率を0.5以上（エミ
ツタ接地の電流増幅率を１以上）とするためには
不可欠である。さて、このような条件を満す材料
関係で構成された、本発明の一実施例の、バンド
ダイアグラムを第２図に示す。図では、第１の半
導体領域１０はｎ形半導体、導電領域３１はn+
半導体、第２の半導体領域２１は、それ自体では
キヤリア濃度は小さく、かつ、第１の半導体領域
より広いエネルギーギヤツプを有する半導体とし
て示されている。実線はフラツトバンド状態での
エネルギバンド図を示し、点線は導電領域３１を
第１の半導体領域に対して更に負にバイアスし
て、導電領域３１から電子が第２の半導体領域２
１の伝導帯を通して第１の半導体領域１０へ注入
されているエネルギバンド図を示す。図において
ECは伝導帯、EVは価電子帯、EFn1、EFp1は第１
の半導体領域１０の電子および正孔のフエルミレ
ベル、EFn3、EFn′3は各バイアス状態での導電領
域３０のフエルミレベルを示す。このバイアス状
態では、第１の半導体領域１０の第２の半導体と
の界面に空乏ないしは反転層１３が形成されてい
る。この空乏ないしは反転層の電位を制御するこ
とによつて、第１の半導体領域へ注入される電子
の数を制御することができる。この制御を行うた
めには、光を第１の半導体まで照射して少数キヤ
リアを発生させ、前記空乏ないしは反転層に蓄積
して少数キヤリアの擬フエルミレベルEFp1を多数
キヤリアのフエルミレベルEFn1と分離させること
により、同一の第１の半導体領域・導電領域間の
バイアス（EFn1−EFn′3に対してもより多くの電
子注入を行わせることができる。このため、本発
明の半導体装置はホトダイオード又はホトトラン
ジスタとしても動作する。更に、この空乏ないし
反転層１３と少数キヤリアの到達距離以内、又は
第２の空乏ないし反転層を介して等空乏ないし反
転層１３と電気接続可能な様態で、第１の半導体
領域の表面上又は内に第１の半導体領域と整流接
合を構成するコンタクト領域を設けて、このコン
タクト領域と導電領域との間にバイアスを印加し
て、第１の半導体領域と導電領域との間に流れる
電流を制御することができる。
In order to realize the operation of the present invention, a significant number of carriers from the conductive region must be excited into the conduction band and valence band of the second semiconductor region. For this purpose, the difference ΔEi between the Fermi level of the conductive region and the energy level of the conduction band or valence band of the second semiconductor region needs to be within 20 KT. This is 0.52eV at room temperature and 0.13eV at 77〓. On the other hand, the height ΔE B of the energy barrier for minority carriers formed by the second semiconductor region at the interface between the first semiconductor region and the second semiconductor region is:
It is essential that ΔEi be larger than ΔEi in order to make the injection efficiency 0.5 or more (current amplification factor of grounded emitter 1 or more). Now, FIG. 2 shows a band diagram of an embodiment of the present invention that is constructed using materials that satisfy such conditions. In the figure, the first semiconductor region 10 is an n-type semiconductor, and the conductive region 31 is an n +
The semiconductor, second semiconductor region 21, is shown as a semiconductor having a lower carrier concentration by itself and a wider energy gap than the first semiconductor region. The solid line shows an energy band diagram in a flat band state, and the dotted line shows the conductive region 31 being biased more negatively with respect to the first semiconductor region, so that electrons from the conductive region 31 are transferred to the second semiconductor region 2.
1 shows an energy band diagram being injected into the first semiconductor region 10 through a conduction band of 1. FIG. In the figure
E C is the conduction band, E V is the valence band, E F n 1 and E F p 1 are the first
The Fermi levels of electrons and holes in the semiconductor region 10, E F n 3 and E F n' 3 indicate the Fermi levels of the conductive region 30 in each bias state. In this bias state, a depletion or inversion layer 13 is formed at the interface between the first semiconductor region 10 and the second semiconductor. By controlling the potential of this depletion or inversion layer, the number of electrons injected into the first semiconductor region can be controlled. In order to perform this control, light is irradiated to the first semiconductor to generate minority carriers, which are then accumulated in the depletion or inversion layer to change the pseudo Fermi level E F p 1 of the minority carriers to the Fermi level E F n of the majority carriers. 1 , more electrons can be injected even for the bias between the same first semiconductor region and conductive region (E F n 1 −E F n′ 3 ) . The semiconductor device of the present invention also operates as a photodiode or a phototransistor.Furthermore, the depletion or inversion layer 13 can be electrically connected to the depletion or inversion layer 13 within the reach of minority carriers, or via a second depletion or inversion layer. providing a contact region forming a rectifying junction with the first semiconductor region on or in the surface of the first semiconductor region in a connectable manner and applying a bias between the contact region and the conductive region; Current flowing between the first semiconductor region and the conductive region can be controlled.
導電領域３１からの第１の半導体領域へのキヤ
リア注入を効率良くするために、第２の半導体領
域２１のエネルギバンドプロフイールを更に工夫
することができる。これは、キヤリアが輸送され
る導電帯ないしは価電子帯が第１の半導体領域近
傍では第１の半導体領域に対してエネルギバリア
を形成するが、導電領域近傍では多数キヤリア
（注入キヤリア）に対するエネルギバリアが前記
バリアより小さい。たとえば、数KT以内か或い
はエネルギバリアが形成されないバンドプロフイ
ールとなるように、第２の半導体領域２１を設計
することにより実現することができる。第３図は
このための一例を示し、同一番号、同一記号は第
２図と同様な機能を果たすものとする。同図にお
いてフラツトバンド状態では、注入キヤリアであ
る電子は導電領域から第２の半導体領域へかなり
の深さまで到達できるが、このバイアス状態では
末だ第１の半導体と第２の半導体の界面にあるエ
ネルギバリアを越えるキヤリアの数は少ない。点
線のエネルギバンドダイアグラムで示すように、
第２の半導体領域の伝導帯がほぼ水平に近くなる
までにバイアスを増加すると、導電領域からのキ
ヤリアは阻止されることなく、第１の半導体領域
へ注入される。このような第２の半導体領域のバ
ンドプロフイールにより大きな電流を流すことが
でき、従つて、相互コンダクタンスｇｍの大きい
高速デバイスを得ることができる。勿論、第３図
の場合も前述のコンタクト領域を設けることによ
り、第１の半導体領域と導電領域との間に流れる
電流を、このコンタクト領域と導電領域との間に
バイアスを印加して制御することができる。第３
図に示すような領域２１を製造するためには、三
元系ないしは四元系化合物半導体の元素の比率を
変化しながら薄膜成長を行う製造技術を用いるこ
とができる。以上の説明では導電領域は高キヤリ
ア濃度半導体を用いて来たが、金属等の低抵抗層
を用いることもできる。 In order to improve the efficiency of carrier injection from the conductive region 31 into the first semiconductor region, the energy band profile of the second semiconductor region 21 can be further modified. This is because the conductive band or valence band through which carriers are transported forms an energy barrier to the first semiconductor region near the first semiconductor region, but forms an energy barrier to majority carriers (injected carriers) near the conductive region. is smaller than the barrier. For example, this can be achieved by designing the second semiconductor region 21 to have a band profile within several KT or a band profile in which no energy barrier is formed. FIG. 3 shows an example for this purpose, and the same numbers and symbols serve the same functions as in FIG. 2. In the same figure, in the flat band state, electrons, which are injected carriers, can reach a considerable depth from the conductive region to the second semiconductor region, but in this bias state, the energy at the interface between the first semiconductor and the second semiconductor is extremely low. The number of carriers that cross the barrier is small. As shown by the dotted energy band diagram,
When the bias is increased until the conduction band of the second semiconductor region is nearly horizontal, carriers from the conductive region are not blocked and are injected into the first semiconductor region. Such a band profile of the second semiconductor region allows a large current to flow, and therefore a high-speed device with a large mutual conductance gm can be obtained. Of course, in the case of FIG. 3 as well, by providing the aforementioned contact region, the current flowing between the first semiconductor region and the conductive region is controlled by applying a bias between the contact region and the conductive region. be able to. Third
In order to manufacture the region 21 as shown in the figure, it is possible to use a manufacturing technique in which thin film growth is performed while changing the ratio of elements of a ternary or quaternary compound semiconductor. In the above description, a high carrier concentration semiconductor has been used for the conductive region, but a low resistance layer such as a metal can also be used.
第４図はGaAs系の結晶材料を用いて、本発明
の第１の実施例を試作した場合の断面構造を示
す。１０は第１の半導体領域で、１１は高電子濃
度のn+基板を示し、その表面に低キヤリア濃度
のGaAs層１１ａが成長されている。２１は第２
の半導体領域としてのAlAs層で、意図的にはド
ーピングしていない。すなわち、低キヤリア濃度
のワイドギヤツプ半導体層である。３１は高電子
濃度のn+GaAs層を示し、導電領域として使用さ
れている。１２は領域３１とセルフアライン状態
で形成されたコンタクト領域でMgの選択イオン
注入により、ｐ形領域として形成されている。こ
のため、第１の半導体領域１０との整流性は良好
である。導電領域３１とセルフアライン状態で形
成されているために領域１２は導電領域３１の第
１の半導体表面に空乏ないし反転層１３が誘起さ
れるとそれと電気的に接続されて、導電領域と第
１の半導体領域の間に流れる電流を制御する機能
を果たす。更に金属薄膜で導電領域、コンタクト
領域、第１の半導体領域に電極が設けられてい
る。図では単一の素子として示されているが、半
絶縁性GaAs基板上に分離された状態で形成さ
れ、集積回路の１素子として用いることもでき
る。低キヤリア濃度GaAs層１１ａの厚さ1.5μｍ、
不純物を添加しないAlAs層２１の厚さ0.01μｍ、
導電領域としてのn+GaAs層の厚さ0.5μｍ、導電
領域の面積50μｍ×50μｍのとき、第５図のよう
な出力特性が得られた。導電領域３１をエミツ
タ、コンタクト領域をベースコンタクト、第１の
半導体領域をコレクタとしてみたときの等価バイ
ポーラトランジスタの電流増幅率は常温で16であ
つた。この素子では反転層の正孔に対して、第２
の半導体領域２１（AlAs）が形成するエネルギ
バリアの高さはΔEB＝0.55eV、電子に対するエネ
ルギバリアの高さΔEi＝0.2eVと見つもられてい
る。
FIG. 4 shows a cross-sectional structure of a first example of the present invention manufactured using a GaAs-based crystal material. 10 is a first semiconductor region, 11 is an n + substrate with high electron concentration, and a GaAs layer 11a with low carrier concentration is grown on the surface thereof. 21 is the second
AlAs layer as a semiconductor region, not intentionally doped. That is, it is a wide gap semiconductor layer with a low carrier concentration. 31 indicates a high electron concentration n + GaAs layer, which is used as a conductive region. A contact region 12 is formed in self-alignment with the region 31 and is formed as a p-type region by selective Mg ion implantation. Therefore, rectification with the first semiconductor region 10 is good. Since the region 12 is formed in a self-aligned state with the conductive region 31, when a depletion or inversion layer 13 is induced on the first semiconductor surface of the conductive region 31, the region 12 is electrically connected to the first semiconductor surface of the conductive region 31, and the region 12 is electrically connected to the first semiconductor surface of the conductive region 31. It functions to control the current flowing between the semiconductor regions of the semiconductor. Furthermore, electrodes are provided in the conductive region, the contact region, and the first semiconductor region using a metal thin film. Although shown as a single element in the figure, it can also be formed separately on a semi-insulating GaAs substrate and used as one element of an integrated circuit. The thickness of the low carrier concentration GaAs layer 11a is 1.5 μm,
The thickness of the AlAs layer 21 without adding impurities is 0.01 μm,
When the thickness of the n + GaAs layer as a conductive region was 0.5 μm and the area of the conductive region was 50 μm×50 μm, output characteristics as shown in FIG. 5 were obtained. The current amplification factor of the equivalent bipolar transistor was 16 at room temperature when the conductive region 31 was considered as an emitter, the contact region as a base contact, and the first semiconductor region as a collector. In this device, the second
The height of the energy barrier formed by the semiconductor region 21 (AlAs) is estimated to be ΔE B =0.55 eV, and the height of the energy barrier to electrons is estimated to be ΔEi = 0.2 eV.
同様な構成は、第１の半導体領域としてｎ形
InxGa1-xAs、第２の半導体領域としてInPを用い
ても実現することができる。更に、第３図の構成
は第２の半導体領域としてｎ形GaAs、第２の半
導体領域としてAlxGa1-xAsを第１の半導体領域
のｎ形GaAsの表面からの距離に従つてｘ＝１〜
０まで連続的に変化させて結晶成長させた結晶
層、導電領域としてSiを添加したn+GaAs層を用
いることによつて実現することができる。この場
合、導電領域と第２の半導体領域の間には電子に
対するバリアはないが、第１の半導体領域と第２
の半導体領域間には正孔に対してΔEB＝0.55eV、
電子に対して0.2eVのエネルギバリアが形成され
る。 A similar configuration can be used for n-type as the first semiconductor region.
It can also be realized by using In x Ga 1-x As or InP as the second semiconductor region. Furthermore, in the configuration of FIG. 3, n-type GaAs is used as the second semiconductor region, and Al x Ga 1-x As is arranged as x according to the distance from the surface of the n-type GaAs in the first semiconductor region. =1~
This can be realized by using a crystal layer grown by continuously changing the crystal value up to 0, and an n + GaAs layer doped with Si as a conductive region. In this case, there is no barrier to electrons between the conductive region and the second semiconductor region, but between the first semiconductor region and the second semiconductor region.
ΔE B =0.55eV for holes between the semiconductor regions of
An energy barrier of 0.2eV is formed for electrons.
以上の説明で明らかなように、本発明の半導体
装置は、第１の半導体領域と第２の半導体領域の
界面近傍に高濃度の不純物層を設ける必要がない
ので、製造時の熱工程に対する制限も少なく、し
かも高不純物濃度領域上での結晶成長に伴う欠陥
の発生もないので、高性能な半導体装置が比較的
容易な製造工程によつて実現することができる。
しかも、上記界面への高不純物濃度領域の挿入を
行わないので、HEMT、SIS電界効果トランジス
タと同一の界面構造を有している。そのために界
面でのキヤリア移動度が大きく、ベース抵抗の小
さな高速素子が得られ、しかも上記電界効果トラ
ンジスタの二次元ガスチヤンネルと接続して使用
することが可能となり、電界効果トランジスタと
混在して集積化することにより、高性能の集積回
路を実現することが可能となる。
As is clear from the above description, the semiconductor device of the present invention does not require a high concentration impurity layer near the interface between the first semiconductor region and the second semiconductor region, so there are no restrictions on the thermal process during manufacturing. Moreover, since defects are not generated due to crystal growth on a high impurity concentration region, a high performance semiconductor device can be realized through a relatively easy manufacturing process.
Moreover, since no high impurity concentration region is inserted into the interface, it has the same interface structure as HEMTs and SIS field effect transistors. As a result, a high-speed device with high carrier mobility at the interface and low base resistance can be obtained, and it can also be used in connection with the two-dimensional gas channel of the above-mentioned field-effect transistor, allowing it to be integrated with the field-effect transistor. This makes it possible to realize high-performance integrated circuits.
第１図は従来の反転層をベースとするトランジ
スタの図、第２図は本発明の第１の実施例のバン
ドダイアグラム図、第３図は本発明の第２の実施
例のバンドダイアグラム図、第４図は本発明の第
１の実施例をGaAs系材料で試作した例の概構成
図、第５図は本発明の第１の実施例をGaAs系材
料で試作した素子の出力特性図である。
図中、１０は第１の半導体領域、１１は高電子
濃度のn+基板、１１ａは低キヤリア濃度のGaAs
層、１２は高電子濃度のn+GaAs層とセルフアラ
イン状態で形成されたコンタクト領域、１３は空
乏層ないし反転層、２０は絶縁膜、２１は第２の
半導体領域（第４図の場合は不純物添加しない
AlAs）、３０は金属電極、３１は導電領域、４０
はベースコンダクト領域である。
FIG. 1 is a diagram of a conventional inversion layer-based transistor, FIG. 2 is a band diagram of a first embodiment of the present invention, and FIG. 3 is a band diagram of a second embodiment of the present invention. Fig. 4 is a schematic configuration diagram of an example of the first embodiment of the present invention fabricated using GaAs-based materials, and Fig. 5 is an output characteristic diagram of an element fabricated using GaAs-based materials in accordance with the first embodiment of the present invention. be. In the figure, 10 is a first semiconductor region, 11 is an n + substrate with high electron concentration, and 11a is GaAs with low carrier concentration.
12 is a contact region formed in a self-aligned state with the n + GaAs layer with high electron concentration, 13 is a depletion layer or inversion layer, 20 is an insulating film, and 21 is a second semiconductor region (in the case of FIG. No added impurities
30 is a metal electrode, 31 is a conductive region, 40
is the base conduction region.
Claims (1)
の半導体領域と接し、第１の半導体の少数キヤリ
アに対して障壁を形成する第２の半導体領域と、
該第２の半導体領域の接する導電領域と、前記第
１の半導体領域と第２の半導体領域との界面に動
作状態で形成される空乏ないし反転層からなり、
前記導電領域から前記第２の半導体領域の伝導帯
ないしは価電子帯を通してキヤリアが輸送され、
前記反転層を通過して前記第１の半導体領域に到
達することにより、前記導電領域をエミツタ、前
記空乏ないし反転層をベース、前記第１の半導体
領域をコレクタとして動作する半導体装置。 ２ 特許請求の範囲第１項記載の半導体装置にお
いて、前記第１の半導体領域の表面上又は内に、
該第１の半導体領域と整流接合を構成し、かつ、
前記反転層と電気接続を有するコンタクト領域を
設けたことを特徴とする半導体装置。 ３ 特許請求の範囲第１項記載の半導体装置にお
いて前記第２の半導体領域は前記第１の半導体領
域の多数キヤリアおよび少数キヤリアに対してエ
ネルギバリアを形成するが、前記導電領域との間
の多数キヤリアに対するエネルギバリアは、前記
第１の半導体領域との間のエネルギバリアより小
さくなるように原子構成を変化させたことを特徴
とする半導体装置。[Claims] 1: a first semiconductor region of a first conductivity type;
a second semiconductor region in contact with the semiconductor region and forming a barrier against minority carriers of the first semiconductor;
comprising a conductive region in contact with the second semiconductor region, and a depletion or inversion layer formed in an operating state at the interface between the first semiconductor region and the second semiconductor region,
Carriers are transported from the conductive region through the conduction band or valence band of the second semiconductor region,
A semiconductor device that passes through the inversion layer and reaches the first semiconductor region, thereby operating with the conductive region as an emitter, the depletion or inversion layer as a base, and the first semiconductor region as a collector. 2. In the semiconductor device according to claim 1, on or within the surface of the first semiconductor region,
forming a rectifying junction with the first semiconductor region, and
A semiconductor device comprising a contact region electrically connected to the inversion layer. 3. In the semiconductor device according to claim 1, the second semiconductor region forms an energy barrier with respect to majority carriers and minority carriers in the first semiconductor region, but the majority carriers between the conductive region and the A semiconductor device, characterized in that an atomic composition is changed so that an energy barrier to carriers is smaller than an energy barrier between the carrier and the first semiconductor region.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61069634A JPS62224969A (en) | 1986-03-27 | 1986-03-27 | Semiconductor device |
| US07/030,747 US4811070A (en) | 1986-03-27 | 1987-03-27 | Heterojunction bipolar transistor with inversion layer base |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61069634A JPS62224969A (en) | 1986-03-27 | 1986-03-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62224969A JPS62224969A (en) | 1987-10-02 |
| JPH0459785B2 true JPH0459785B2 (en) | 1992-09-24 |
Family
ID=13408487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61069634A Granted JPS62224969A (en) | 1986-03-27 | 1986-03-27 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4811070A (en) |
| JP (1) | JPS62224969A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2533541B2 (en) * | 1987-06-08 | 1996-09-11 | 株式会社日立製作所 | Heterojunction bipolar transistor |
| US5311068A (en) * | 1991-05-22 | 1994-05-10 | General Electric Company | Solid-state energy meter with time-of-use rate scheduling and load control circuit |
| KR100275757B1 (en) | 1998-08-31 | 2001-01-15 | 김덕중 | Semiconductor Rectifier and Method of Manufacturing the Same |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4127861A (en) * | 1977-09-26 | 1978-11-28 | International Business Machines Corporation | Metal base transistor with thin film amorphous semiconductors |
| US4380774A (en) * | 1980-12-19 | 1983-04-19 | The United States Of America As Represented By The Secretary Of The Navy | High-performance bipolar microwave transistor |
| JPS59227161A (en) * | 1983-05-25 | 1984-12-20 | アメリカン・テレフォン・アンド・テレグラフ・カムパニー | Bipolar transistor |
| JPH0750714B2 (en) * | 1984-01-30 | 1995-05-31 | 日本電気株式会社 | Bipolar transistor |
| EP0177246B1 (en) * | 1984-09-29 | 1988-08-17 | Kabushiki Kaisha Toshiba | Heterojunction bipolar transistor and method of manufacturing the same |
| JPH063806B2 (en) * | 1985-06-20 | 1994-01-12 | 株式会社東芝 | Heterojunction bipolar transistor |
| US4686550A (en) * | 1984-12-04 | 1987-08-11 | American Telephone And Telegraph Company, At&T Bell Laboratories | Heterojunction semiconductor devices having a doping interface dipole |
| US4691215A (en) * | 1985-01-09 | 1987-09-01 | American Telephone And Telegraph Company | Hot electron unipolar transistor with two-dimensional degenerate electron gas base with continuously graded composition compound emitter |
-
1986
- 1986-03-27 JP JP61069634A patent/JPS62224969A/en active Granted
-
1987
- 1987-03-27 US US07/030,747 patent/US4811070A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US4811070A (en) | 1989-03-07 |
| JPS62224969A (en) | 1987-10-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5962893A (en) | Schottky tunneling device | |
| US4484207A (en) | Static induction transistor and semiconductor integrated circuit using hetero-junction | |
| JPH0541520A (en) | Semiconductor device | |
| JPH0435904B2 (en) | ||
| JP2571208B2 (en) | Low temperature tunnel transistor | |
| KR930002594B1 (en) | Manufacturing method of semiconductor device | |
| KR910004315B1 (en) | Hot electron unipolar transistor | |
| JPH07193081A (en) | Bipolar transistor | |
| US5391897A (en) | Status induction semiconductor device | |
| US4903091A (en) | Heterojunction transistor having bipolar characteristics | |
| KR920010671B1 (en) | Semiconductor devices | |
| US4035824A (en) | Semiconductor device stabilized by an insulating layer formed on a semiconductor region having a low impurity concentration | |
| JPH0459785B2 (en) | ||
| JPS6152990B2 (en) | ||
| JPS61147577A (en) | Complementary semiconductor device | |
| WO1987000692A1 (en) | Semiconductor device | |
| JPH0797638B2 (en) | Field effect transistor | |
| JP3001601B2 (en) | Semiconductor device | |
| JPH0371775B2 (en) | ||
| KR910006751B1 (en) | Semiconductor integrated circuit device and its manufacturing method | |
| JP2500334B2 (en) | Semiconductor device | |
| JPS60136380A (en) | Semiconductor device | |
| JP4108252B2 (en) | Electronic devices | |
| JPH0770706B2 (en) | High-speed semiconductor device | |
| JPH0131314B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |