JPH0459639U - - Google Patents
Info
- Publication number
- JPH0459639U JPH0459639U JP10257990U JP10257990U JPH0459639U JP H0459639 U JPH0459639 U JP H0459639U JP 10257990 U JP10257990 U JP 10257990U JP 10257990 U JP10257990 U JP 10257990U JP H0459639 U JPH0459639 U JP H0459639U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- output
- logic level
- circuit
- pmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 9
Landscapes
- Logic Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10257990U JPH0459639U ( ) | 1990-09-28 | 1990-09-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10257990U JPH0459639U ( ) | 1990-09-28 | 1990-09-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0459639U true JPH0459639U ( ) | 1992-05-21 |
Family
ID=31846952
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10257990U Pending JPH0459639U ( ) | 1990-09-28 | 1990-09-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0459639U ( ) |
-
1990
- 1990-09-28 JP JP10257990U patent/JPH0459639U/ja active Pending