JPH0458546A - Cutting method for semiconductor wafer - Google Patents
Cutting method for semiconductor waferInfo
- Publication number
- JPH0458546A JPH0458546A JP17097590A JP17097590A JPH0458546A JP H0458546 A JPH0458546 A JP H0458546A JP 17097590 A JP17097590 A JP 17097590A JP 17097590 A JP17097590 A JP 17097590A JP H0458546 A JPH0458546 A JP H0458546A
- Authority
- JP
- Japan
- Prior art keywords
- cutter
- wafer
- semiconductor wafer
- cutting
- relief
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 12
- 238000005520 cutting process Methods 0.000 title claims description 22
- 229910000679 solder Inorganic materials 0.000 claims abstract description 16
- 238000010586 diagram Methods 0.000 description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野］
本発明はウェーハ状の半導体装置を個々の独立した半導
体装置にする切断方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for cutting wafer-shaped semiconductor devices into individual independent semiconductor devices.
［従来の技術］
従来のウェーハ切断方法は第２図に示すように、テープ
５に貼付けられたウェーハ６を高速回転のカッターｌで
個々の独立した半導体装置３に切断するようになってい
る。また被切断物である半導体装置は、半導体（Ｓｉ、
ＧａＡｓ）と、チップ状の半導体装置を、外部引出し
用リードフレームに固定するためのソルダ層（Ａｕ）４
からの２層になっている。[Prior Art] As shown in FIG. 2, in a conventional wafer cutting method, a wafer 6 attached to a tape 5 is cut into individual semiconductor devices 3 using a cutter l rotating at high speed. In addition, the semiconductor device that is the object to be cut is a semiconductor (Si,
GaAs) and a solder layer (Au) 4 for fixing the chip-shaped semiconductor device to the external lead frame.
It has two layers.
第２図に示すように、半導体（Ｓｉ、 ＧａＡｓ）とソ
ルダ層（Ａｕ）の異質の２層からなり、かつソルダ層４
は、Ａｕを主成分とした材質であるため、柔らかくカッ
ターの先端が目詰りを起して切れ味が悪くなる。As shown in FIG. 2, it consists of two different layers: a semiconductor (Si, GaAs) and a solder layer (Au), and the solder layer 4
Since the material is mainly composed of Au, it is soft and the tip of the cutter becomes clogged, making it difficult to cut.
そのような状態で切断を続けると、切断面に不具合が発
生して、さらに続けるとストレスが加わり、クラック等
が発生するため、カッター１を交換する必要が生じてく
る。そのため、従来はカッター１を頻繁に交換して切断
を行っていた。If cutting is continued in such a state, defects will occur on the cut surface, and if it continues further, stress will be added and cracks will occur, making it necessary to replace the cutter 1. Therefore, in the past, the cutter 1 had to be replaced frequently for cutting.
Ｃ発明が解決しようとする課題〕
この従来のウェーハ切断方法では、ソルダ層（Ａｕ）
４を切断するため、カッター１の先端に目詰りが生じ、
初期の切断面を維持することが困難であった。また第３
図に示すように切込み深さを調整してソルダ層４に切込
みが入らないようにすると、目詰りが生じなく、切刃へ
の影響はなくなるが、切断の最終目的である個々の半導
体装置３にすることを果たせず、第３図の方法では有効
な対策とならないという問題点があった。Problems to be solved by the invention C] In this conventional wafer cutting method, the solder layer (Au)
4, the tip of cutter 1 gets clogged,
It was difficult to maintain the initial cut surface. Also the third
If the cutting depth is adjusted to prevent cutting into the solder layer 4 as shown in the figure, clogging will not occur and there will be no effect on the cutting blade, but it will cut into individual semiconductor devices 3, which is the ultimate purpose of cutting. The problem was that the method shown in Figure 3 was not an effective countermeasure.
本発明の目的は切刃の目詰りをなくすことにより、従来
の問題点を解決した半導体ウェーハの切断方法を提供す
ることにある。An object of the present invention is to provide a semiconductor wafer cutting method that solves the conventional problems by eliminating clogging of cutting blades.
前記目的を達成するため、本発明に係る半導体ウェーハ
の切断方法においては、逃げ形成工程と、切断工程とを
有する半導体ウェーハの切断方法であって、
逃げ形成工程は、半導体ウェーハ裏面に成膜されるソル
ダ層に、ウェーハ面を露出させた逃げをカッターによる
タイシングラインに対応させて形成する工程であり、
切断工程は、半導体ウェーハを前記逃げに対応したダイ
シングラインに沿ってカッターで切断し、ウェーハ状半
導体装置を個々に独立したチップ状半導体装置に分離す
る工程であ）ノ、また前記逃げの巾は、カッターの巾よ
り広幅としたものである。In order to achieve the above object, a method for cutting a semiconductor wafer according to the present invention includes a relief forming step and a cutting step, wherein the relief forming step is performed by forming a film on the back surface of the semiconductor wafer. This is a step in which a cutout exposing the wafer surface is formed in the solder layer corresponding to the dicing line by a cutter, and the cutting step is to cut the semiconductor wafer with a cutter along the dicing line corresponding to the cutout, This is a step of separating a wafer-like semiconductor device into individual chip-like semiconductor devices, and the width of the relief is wider than the width of the cutter.
〔作用］
本発明は、半導体ウェーハの裏面に成膜されるソルダ層
に、カッターによるダイシングラインに対応させた逃げ
を設け、カッターの切断位置のソルり層をなくすことに
より、カッターの目詰りをなくすものである。[Function] The present invention prevents clogging of the cutter by providing a relief corresponding to the dicing line by the cutter in the solder layer formed on the back surface of the semiconductor wafer and eliminating the solder layer at the cutting position of the cutter. It is something to be eliminated.
以下、本発明の一実施例を図により説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を示す図である。FIG. 1 is a diagram showing an embodiment of the present invention.
図において、半導体ウェーハ６をテープ５に貼付ける前
段階において、半導体ウェーハ裏面に成膜されるソルダ
層４に、ウェーハ面を露出させた逃げ４ａをカッター］
によるダイシングラインに対応させて形成する。尚、実
施例では逃げ４ａは、チップ状半導体装置３を周回する
ように格子状に形成しである。また、逃げ４ａの巾Ｑ１
はカッター１の巾Ｑ１ より広幅に設定しである。In the figure, before attaching the semiconductor wafer 6 to the tape 5, the solder layer 4 formed on the back surface of the semiconductor wafer is cut with a cutout 4a that exposes the wafer surface.]
The dicing line is formed in accordance with the dicing line. In the embodiment, the recesses 4a are formed in a lattice shape so as to go around the chip-shaped semiconductor device 3. Also, the width of the relief 4a Q1
is set wider than the width Q1 of cutter 1.
その後、半導体ウェーハ６の裏面をテープ５に貼付ける
。Thereafter, the back side of the semiconductor wafer 6 is attached to the tape 5.
次に、スピンドル２に軸支したカッター１を高速回転さ
せることにより、カッター１で半導体ウェーハ６の表面
側から該ウェーハ６を逃げ４ａに対応したダイシングラ
インに沿って切断し、ウェーハ状半導体装置を個々に独
立したチップ状半導体装置３に分離させる。Next, by rotating the cutter 1 pivotally supported on the spindle 2 at high speed, the cutter 1 cuts the semiconductor wafer 6 from the front side of the semiconductor wafer 6 along the dicing line corresponding to the wafer 4a, thereby forming a wafer-shaped semiconductor device. The semiconductor devices 3 are separated into individual chip-like semiconductor devices 3.
本発明によれば、カッター１で切断するウェーハ６の裏
面側にウェーハ面が露出しているため、カッター１の先
端にソルダ層４が付着することはなく、カッター１が目
詰りすることはない。According to the present invention, since the wafer surface is exposed on the back side of the wafer 6 to be cut by the cutter 1, the solder layer 4 will not adhere to the tip of the cutter 1, and the cutter 1 will not be clogged. .
尚、実施例ではカッター１として高速回転する円板状の
ブレードを用いたが、これに限定されるものではない。In the embodiment, a disc-shaped blade rotating at high speed is used as the cutter 1, but the invention is not limited to this.
［発明の効果〕
以上説明したように本発明は半導体装置の裏面に成膜さ
れたソルダ層をカッターで切削することがないため、カ
ッターの目詰りを引き起こすことがなく、カッターの寿
命を伸すことかでき、かつ各半導体装置間の切断面にク
ラックやチッピングの発生をなくして切断でき、製造歩
留りを向上できるという効果を有する。[Effects of the Invention] As explained above, the present invention does not use a cutter to cut the solder layer formed on the back surface of a semiconductor device, so the cutter does not become clogged and the life of the cutter is extended. This has the effect that it can be cut without cracking or chipping on the cut surface between each semiconductor device, and that the manufacturing yield can be improved.
第１図は本発明の一実施例を示す図、第２図。
第３図は従来方法を示す図である。
１・・・カッター ２・・スピンドル３・・
・半導体装置 ４・・・ソルダ層５・・・テー
プ ６・・・半導体ウェーハ特許出願人
日本電気株式会社
第
■
図
り
第２図
第
図FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing an embodiment of the present invention. FIG. 3 is a diagram showing a conventional method. 1...Cutter 2...Spindle 3...
・Semiconductor device 4...Solder layer 5...Tape 6...Semiconductor wafer patent applicant
NEC Co., Ltd. Diagram 2 Diagram
Claims (2)
ーハの切断方法であって、 逃げ形成工程は、半導体ウェーハ裏面に成膜されるソル
ダ層に、ウェーハ面を露出させた逃げをカッターによる
ダイシングラインに対応させて形成する工程であり、 切断工程は、半導体ウェーハを前記逃げに対応したダイ
シングラインに沿ってカッターで切断し、ウェーハ状半
導体装置を個々に独立したチップ状半導体装置に分離す
る工程であることを特徴とする半導体ウェーハの切断方
法。(1) A semiconductor wafer cutting method comprising a relief forming step and a cutting step, wherein the relief forming step involves dicing the relief with the wafer surface exposed on a solder layer formed on the back surface of the semiconductor wafer using a cutter. The cutting process is a process of cutting the semiconductor wafer with a cutter along the dicing line corresponding to the relief, and separating the wafer-shaped semiconductor devices into individual chip-shaped semiconductor devices. A method for cutting a semiconductor wafer, characterized in that:
とを特徴とする請求項第（１）項記載の半導体ウェーハ
の切断方法。(2) The method for cutting a semiconductor wafer according to claim (1), wherein the width of the relief is wider than the width of the cutter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17097590A JPH0458546A (en) | 1990-06-28 | 1990-06-28 | Cutting method for semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17097590A JPH0458546A (en) | 1990-06-28 | 1990-06-28 | Cutting method for semiconductor wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0458546A true JPH0458546A (en) | 1992-02-25 |
Family
ID=15914824
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17097590A Pending JPH0458546A (en) | 1990-06-28 | 1990-06-28 | Cutting method for semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0458546A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0464250A (en) * | 1990-07-04 | 1992-02-28 | Rohm Co Ltd | Expansion tape |
| JP2004261625A (en) * | 2003-01-20 | 2004-09-24 | Ngk Insulators Ltd | Method for manufacturing honeycomb structure |
| JP2011035111A (en) * | 2009-07-31 | 2011-02-17 | Disco Abrasive Syst Ltd | Method of manufacturing chip with metal layer |
| US20110057332A1 (en) * | 2009-09-07 | 2011-03-10 | Renesas Electronics Corporation | Semiconductor chip with conductive adhesive layer and method of manufacturing the same, and method of manufacturing semiconductor device |
-
1990
- 1990-06-28 JP JP17097590A patent/JPH0458546A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0464250A (en) * | 1990-07-04 | 1992-02-28 | Rohm Co Ltd | Expansion tape |
| JP2004261625A (en) * | 2003-01-20 | 2004-09-24 | Ngk Insulators Ltd | Method for manufacturing honeycomb structure |
| US8398799B2 (en) | 2003-01-20 | 2013-03-19 | Ngk Insulators, Ltd. | Method of manufacturing honeycomb structure |
| JP2011035111A (en) * | 2009-07-31 | 2011-02-17 | Disco Abrasive Syst Ltd | Method of manufacturing chip with metal layer |
| US20110057332A1 (en) * | 2009-09-07 | 2011-03-10 | Renesas Electronics Corporation | Semiconductor chip with conductive adhesive layer and method of manufacturing the same, and method of manufacturing semiconductor device |
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