JPH0457500A - Balance adjusting circuit - Google Patents

Abstract

PURPOSE:To correct by adjust balance among channels by counting directions according to direction signals after defining the output signal of an oscillation circuit as a clock, and attenuating signals passing through each channel according to the output signal of a decoder which decodes the counted value. CONSTITUTION:An oscillation circuit 21 operates according to a timing signal obtained from a discrimination circuit 20. For example, when right and left stereoscopic signals at almost the same levels are impressed to right and left input terminals 14 and 13, the value of the output signal of a signal generating circuit 19 is close to a reference voltage Vref. Because of this, the output signal of the discrimination circuit 20 goes to an L level, and the oscillation circuit 21 starts the operation. Then, the oscillation circuit 21 continues the oscillation as long as an output signal Vx of the signal generating circuit 19 is within the ranges of reference voltages VA and VB of the discrimination circuit 20. Therefore, a decoder 25 decodes successively the counted value of a counting circuit 24, and controls right and left attenuating circuits 18 and 17 so as to hold a balance state.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a balance adjustment circuit for eliminating imbalance between channels.

(B) Prior Art In a stereo device that transmits left and right stereo signals using different channels, imbalance may occur due to variations in circuits and elements constituting each channel. For example, the anallancer's voice must be localized at the center of the left and right speakers, but if an imbalance occurs between the channels as described above, the voice will be localized to the left or right, impairing the audibility.

For this reason, balance adjustment circuits for balancing left and right channels have been proposed and put into use.

Figure 2 shows an example of such a balance adjustment circuit, where the left stereo signal applied to the left input terminal (1) is
It is led out to the left output terminal (3) via the left attenuation circuit (2). Further, the right stereo signal applied to the right input terminal (4) is led out to the right output terminal (6) via the right attenuation circuit (5). Therefore, the level of the left and right stereo signals obtained at the left and right output terminals (3) and 6) is determined by the detection circuit (7).
are detected and compared with each other. Then, the detection circuit (7
) generates an output signal corresponding to the level difference between the left and right stereo signals. The output signal is held in a holding circuit (8) and applied to a control circuit (9). The control circuit (
9> receives the output signal of the holding circuit (8) and controls the amount of attenuation of the left and right attenuation circuits (2) and (5). Now, if left and right stereo signals corresponding to the anallancer's voice are applied to the left and right input terminals (1) and (4), left and right stereo signals of equal level must be generated at the left and right output terminals (3) and (6). However, if there is an imbalance between the channels, the levels of the left and right stereo signals will not be equal. For example, if the level of the left stereo signal is higher than the level of the right stereo signal, an output signal of a predetermined level or higher is generated from the detection circuit (7) and is applied to the control circuit (9) via the holding circuit (8). be done. Therefore, the control circuit (9
) generates a control signal to increase the attenuation amount of the left attenuation circuit (2) and perform balance adjustment. Conversely, when the level of the left stereo signal is lower than the level of the right stereo signal, the amount of attenuation of the right attenuation circuit (5) is reduced by the output signal of the control circuit (9).

(c) Problems to be Solved by the Invention The balance adjustment circuit shown in Figure 2 is entirely composed of analog circuits, and requires a holding circuit (8) to hold the output signal of the detection circuit (7). Become. As shown in the figure, the holding circuit (8) includes a capacitor (10) and a resistor (1).
1) and (12), it is not possible to hold the output signal of the detection circuit (7) for a long time.
There was a problem. Further, when the level of the output signal of the detection circuit (7) changes rapidly, the capacitor (10) is rapidly charged and discharged, which causes a problem of generating a shock sound.

(d) Means for Solving the Problems The present invention has been made in view of the above points, and includes means for generating a timing signal, means for generating a direction signal, and starting an operation in response to the timing signal. an oscillation circuit to
A counting circuit that uses the output signal of the oscillation circuit as a clock to perform counting in a direction according to the direction signal, a decoder that decodes the counted value of the counting circuit, and a signal that passes through each channel according to the output signal of the decoder. and an attenuation circuit that attenuates the.

(E) Function According to the present invention, the timing signal is used to start the operation of the oscillation circuit and determine the timing of adjustment. Further, the direction of adjustment is determined according to the direction signal. The counting circuit is
The output signal of the oscillation circuit is used as a clock, and the clock is counted in a direction determined by a direction signal. The count value of the counting circuit is decoded by a decoder, and the attenuation amount of the attenuation circuit is controlled by the output signal of the decoder.

(f) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention, (13)
is the left input terminal to which the left stereo signal is applied, (14) is the right input terminal to which the right stereo signal is applied, (15) is the left output terminal from which the left stereo signal is derived, and (16) is the right stereo signal to which it is applied. The derived right output terminal, (17) is the left attenuation circuit inserted in the left transmission line (channel), (18) is the right attenuation circuit inserted in the right transmission line (channel), (1
9) is a signal generation circuit that generates a signal according to the level ratio of the left and right stereo signals obtained at the left and right output terminals (15) and (16), respectively, and (20) is the signal generation circuit (19).
(21) is an oscillation circuit that operates according to a timing signal obtained from the discrimination circuit (20); (22) is the signal generation circuit (19); ) and a reference voltage Vref to generate a direction signal; (23) is an up-down circuit that generates an up signal or a down signal according to the output signal of the comparison circuit (22); (24) is a counting circuit which uses the output signal of the oscillation circuit (21) as a clock and performs counting in a direction according to the output signal of the up-down circuit (23), and (25) is a counting circuit of the counting circuit (24). This is a decoder that decodes the count value.

To simplify the explanation, there are three types of signals applied to the left and right input terminals (13) and (14): left stereo signal only, right stereo signal only, and left and right stereo signals at approximately the same level. (referred to as the center signal).

The first terminal in which only the left input signal is applied to the left input terminal (13)
In this state, an output signal that is sufficiently larger than the reference voltage Vref is generated at the output terminal of the signal generating circuit (19).

The reference voltage vA of the discrimination circuit (20) is the reference voltage V re
It is set to a value larger than f by a predetermined value, and the reference voltage v! Since l is set to a value smaller than the reference voltage Vref by a predetermined value, the discrimination circuit (20) outputs an output signal of "rH" when the input signal is smaller than vA or smaller than 8. When the voltage is between vA and VB, the output signal of LJ is generated.6 However, if the output signal of the signal generation circuit (19) is sufficiently larger than the reference voltage Vref, the discrimination circuit (20)
The output becomes "H" and the oscillation circuit (21) does not start operating. Therefore, the counting circuit (24) also does not start counting.
The left and right damping circuits (17) and (18) are in a non-damping state.

A second terminal in which only the right input signal is applied to the right input terminal (14).
In this state, an output signal sufficiently smaller than the reference voltage Vref is generated at the output terminal of the signal generating circuit (19).

In this case as well, the output of the discrimination circuit (20) becomes "H",
The oscillation circuit (21) does not operate, and the left and right damping circuits 17) and (18) are in a non-damping state.

In the third state where left and right stereo signals of approximately equal levels are applied to the left and right input terminals (13> and (14)),
The value of the output signal of the signal generation circuit (19) becomes near Vref. Therefore, the output signal of the discrimination circuit (20) is r L
, the oscillation circuit (21) starts operating and applies its output signal to the counting circuit (24) as a clock. On the other hand, the output signal of the signal generation circuit (19) is
2) and is compared with the reference voltage V ref.

Now, the output signal of the signal generation circuit (19) is at the reference voltage Vr.
If it is more than ef, the output of the comparator circuit (22) becomes rH'', an up signal is generated from the up/down circuit (23), and the counting direction of the counting circuit (24) is set in the up direction. Therefore, the counting circuit (24) is connected to the oscillation circuit (
21) is used as a clock to perform counting in the up direction. Further, when the output signal of the signal generation circuit (19) is smaller than the reference voltage Vref, the comparison circuit (22)
The output becomes rL, and the counting circuit (24) performs counting in the down direction in response to the down signal generated from the up/down circuit (23).

The decoder (25) sequentially decodes the count value of the counting circuit <24) and drives the left and right attenuation circuits (17) and (18). At that time, the output signal of the decoder (25) is directly applied to the left attenuation circuit (17), and is applied to the right attenuation circuit (18) via the inverter (26), so the left and right attenuation circuits (17) and (18) are controlled in opposite directions.If the level of the left output signal is lower than the level of the right output signal, the counting circuit (24) performs counting in the direction of the A knob, and the left attenuation circuit (17) ) increases, and the attenuation amount of the right attenuation circuit (18) decreases.Conversely, when the level of the left output signal is lower than the level of the right output signal, the counting circuit (24) moves in the down direction. The left attenuation circuit (1
7) decreases, and the attenuation amount of the right attenuation circuit (18) increases. That is, the left and right attenuation circuits (17) and (18
> are controlled in opposite directions.

As mentioned earlier, the oscillation circuit (21) is a signal generation circuit (
19) (7) The output signal Vx satisfies V A > V x >
Oscillation continues as long as it is within the V B (7) range. Therefore, while the oscillation circuit (21) continues to oscillate, the decoder (25) sequentially decodes the count value of the counting circuit (24) and controls the left and right damping circuits (17> and (18)) to maintain a balanced state. keep it.

In addition, the counting circuit (24) is equipped with a limiter function,
It is configured such that once a predetermined count has been performed, no further counts can be made. In addition, the left and right attenuation circuits (1
7) and (18), the left and right output terminals (15
) and (16) are reversed, the counting direction of the counting circuit (24) is reversed and a similar attenuation operation is performed.

Figure 3 shows the counting circuit (24) and decoder (24) in Figure 1.
5) shows a specific circuit example. In Figure 3,
The counting circuit (24) includes four D-FFs (27) to (3
0), eight exclusive OR gates (31) to (38), and four exclusive OR gates (39) to (42). Also,
The decoder (25) includes the first to fourth anime games 1-(4).
3) to (46) and the fifth to eighth AND gates (47
] to (50).

Figure 4 shows specific circuit examples of the left and right attenuation circuits (17) and (18), where (51) is the first left attenuation circuit consisting of four resistors and four gates, and (52) is the first left attenuation circuit consisting of four resistors and four gates. A second left attenuation circuit (53) has a similar configuration, a first right attenuation circuit (54) has a similar configuration, and a second right attenuation circuit (54) has a similar configuration.

In addition, in Figures 3 and 4, the first anime) (
The output A of 43) switches the gate A of the first left attenuation circuit (51) and the first right attenuation circuit (53), and the outputs B to H also switch the corresponding gates in FIG. Connected.

In FIGS. 3 and 4, D-FF (27) to (3
0) (7) If all Q outputs are "0", that is, the count value of the counting circuit (24) is in the initial state of (oooo),
The outputs of the fourth and eighth AND gates (46) and (50) are generated and the gates D and H are opened. When the first clock is applied to the clock input terminal (56) while the up signal rL is input to the up/down input terminal (55), the count value of the counting circuit (24) becomes (1).
000), the output C of the third AND gate (45) is generated, and the gate c is opened. Therefore, the left input signal Li
is slightly attenuated, and the amount of attenuation of the right input signal R10') becomes small. As the clocks count, the gates that become open move sequentially, and when 16 clocks are applied, the outputs A of the first AND gate and the fifth AND gates (43) and (47),
E is generated, gates A and E are opened, and the left input signal L
i is in the maximum attenuation state, and the right input signal Ri is in the non-attenuation state. In actual circuit operation, the comparator circuit (22
) is likely to be inverted and count in the opposite direction.

The first left attenuation circuit (51) and the first right attenuation circuit (53) are
For example, A.

B, C, and D become O, -1, -2, and -3. Also, the second
The left attenuation circuit (52) and the second right attenuation circuit (54) are also given the same weighting, for example, E.

F, G, H are 0. -4. -8. -12.

When the down signal "Hl" is applied to the up/down input terminal (55), the output of the counting circuit (24) is
A down counting state changes as (1111), (0111), etc., and the corresponding gate is opened. Also, the third
In Fig. 4 and Fig. 4, the case where one counting circuit is in a maximum attenuation state and the other attenuation circuit is in an unattenuated state is explained as an initial value, but when the attenuation amount of both attenuation circuits is equal and becomes an intermediate value, may be set as an initial value, and the attenuation amounts may change in opposite directions depending on the output of the decoder.

In the embodiment, a case has been described in which balance adjustment is automatically performed during listening, but listening may be performed after balance adjustment is performed by applying a test signal or a monaural signal. Furthermore, the present invention is applicable not only to 2-channel stereo but also to multi-channel stereo such as 4-channel stereo.

(G) Effects of the Invention As described above, according to the present invention, it is possible to provide a balance adjustment device that can accurately adjust the balance between channels. Since the adjustment is performed by digital processing, it is possible to provide a balance adjustment circuit that has a simple configuration and operates accurately. In particular, digitization makes it easy to hold data, which eliminates the need for a holding circuit using a CR time constant, making it possible to hold the state for a long time and prevent the occurrence of shock noise.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a conventional balance adjustment circuit, and Fig. 3 is a circuit diagram showing a specific circuit example of the counting circuit and decoder shown in Fig. 1. and FIG. 4 is a circuit diagram showing a specific circuit example of the attenuation circuit shown in FIG. 1. (17) (18)...Attenuation circuit, (19)...Signal generation circuit, (20)...Discrimination circuit, (21)...
・Oscillation circuit, (22)...Comparison circuit, (24)・
... Counting circuit, (25) ... Decoder. Figure 2

Claims (5)

[Claims] (1) A balance adjustment circuit for adjusting the balance between at least two channels, comprising means for generating a timing signal for determining an adjustment period, and means for generating a direction signal for determining an adjustment direction. , an oscillation circuit that starts operating in response to the timing signal, a counting circuit that uses the output signal of the oscillation circuit as a clock to count in a direction according to the direction signal, and a decoder that decodes the count value of the counting circuit. A balance adjustment circuit comprising: first and second attenuation circuits arranged in each of the channels and attenuating a signal according to the output of the decoder. (2) The means for generating the direction signal includes a signal generation circuit that generates a signal according to the level ratio of the signals passing through each channel, and a comparison circuit that compares the output signal of the signal generation circuit with a reference voltage. The balance adjustment circuit according to claim 1, characterized in that it comprises: (3) The balance adjustment circuit according to claim 1, wherein the first and second attenuation circuits are controlled by mutually opposite output signals obtained from a decoder. (4) The first and second attenuation circuits each include a plurality of resistors connected in series between a signal path and the ground, and a gate connected between the signal path and one end of the resistor, controlling opening and closing of the gate according to the output of the decoder,
2. The balance adjustment circuit according to claim 1, wherein the balance adjustment circuit adjusts the amount of attenuation. (5) The balance according to claim 1, wherein the timing signal generating means generates the timing signal when a level ratio of the signals passing through each channel is within a predetermined range. Adjustment circuit.