JP2994726B2 - Balance adjustment device - Google Patents

Description

The present invention relates to a balance adjusting device for adjusting imbalance between channels of left and right stereo signals, and more particularly to a test mode for applying a test signal to balance adjustment. The present invention relates to a balance adjusting device that is devised so as not to have an adverse effect.

(B) Conventional technology In a stereo apparatus that transmits left and right stereo signals using different channels, imbalance may occur due to variations in circuits and elements constituting each channel. For example, the voice of the announcer must be localized at the center of the left and right speakers, but if the imbalance occurs between the channels as described above, it will be localized at a position offset to the left or right, and impair hearing.

Therefore, conventionally, a balance adjusting device for balancing the left and right channels has been proposed and used. As the signal source of the stereo device, there are various sources such as a compact disk player and a video disk player, and the amount of imbalance between channels differs depending on each player. Therefore, in the above-described balance adjustment device of the stereo device, the balance adjustment is switched for each player. FIG. 2 shows an example of such a balance adjusting device. By switching first and second switches (1) and (2) which operate in conjunction with each other, a compact disk player (3), a video disk The outputs of the player (4) and the test signal generator (5) are selectively applied to a balance adjustment circuit (6). The two selected signals are controlled by the balance adjustment circuit (6) so that the levels are equal, and the left and right stereo signals having the same level are output from the L (left) output terminal (7) and the R (right) output terminal (8). Is obtained.

Incidentally, a recent stereo apparatus is provided with a test signal generator (5) for generating a test signal that is exactly the same on the left and right for testing whether sound is output at the same volume from the right and left loudspeakers that correspond properly. . Thereby, the left and right imbalance caused by the circuit at the subsequent stage of the balance adjustment circuit (6) can also be corrected.

(C) Problems to be Solved by the Invention However, in the circuit shown in FIG. 2, the test signal generator (5) is temporarily turned on while the compact disc player (3) or the video disc player (4) is being selected. If you select), it may take time to readjust after the recovery.

The balance adjustment circuit (6) in FIG. 2 can adjust the balance only when a monaural signal (when the input left and right stereo signals are equal to each other) is applied. That is, the balance adjustment operation cannot always be performed, and may be adjusted only occasionally depending on the source. For that reason,
Once the test signal generator (5) is selected and returned again, it may take a long time to adjust the balance again, causing a problem.

(D) Means for Solving the Problems The present invention has been made in view of the above points, and has a function of performing a balance adjustment of a signal from a signal source requiring a balance adjustment between channels and holding the adjustment value. What is claimed is: 1. A balance adjustment apparatus comprising a balance adjustment circuit capable of adjusting a balance between channels. A test signal generator which does not require balance adjustment between channels, and a test signal from the test signal generator being applied to the balance adjustment circuit. A detection circuit for detecting, the adjustment value of the balance adjustment circuit being taken and held in accordance with a first detection output signal of the detection circuit, and the adjustment value being held in accordance with a second detection output signal of the detection circuit; And a first register for returning to the balance adjustment circuit.

(E) Operation According to the present invention, the adjustment value of the balance adjustment circuit is held in the first register during a period in which the test signal is applied, and after the end of the period, the held adjustment value is stored in the balance adjustment circuit. I'm back.

(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention.
A second register built in the balance adjustment circuit (6) and holding an adjustment value according to a level difference between the left and right stereo signals;
(10) is a first register for holding the data held in the second register (9) during test signal application, and (11) is a rising edge detection circuit (12) and a falling edge detection circuit (13). And a detection circuit for shaping the waveform of the switching control signal from the control terminal (14).

In FIG. 1, the same circuit elements as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 1, for example, an "L" level control signal is applied to a control terminal (14), and both the first and second switches (1) and (2) are switched to the "a" side. Is assumed to be selected. The selected left and right stereo signals are controlled by the balance adjustment circuit (6) so that the levels are equal to each other, and the control amount, that is, the adjustment value at that time is held in the second register (9). As a result, left and right stereo signals having the same level are obtained at the L and R output terminals (7) and (8).

In the state described above, the test mode is temporarily set. In the test mode, an "H" level control signal is applied to the control terminal (14), and its waveform is shown as in FIG. The signal shown in FIG. 3A is a rising edge detection circuit (12)
, The output becomes as shown in FIG.
Rising signal at time t ₁ of FIG. 3 (b) is applied to the clock (CL) terminal of the first register (10). Then, the first register (10) captures and holds the data of the second register (9) at that time. Then, at time t _2, the falling signal of FIG. 3 (b) is applied to the reset (R) terminal of the second register (9). When the second register (9) is reset, the adjustment value becomes zero, and the balance adjustment circuit (6) does not perform left / right balance adjustment. on the other hand,
At this time, in response to the "H" level signal in FIG.
Since the first and second switches (1) and (2) are switched to the b side and the test signal is selected, the test signal is not controlled at all and the L and R output terminals (7) and (8) Occurs.

When the signal of FIG. 3 (A) falls after the test signal period, the falling edge detection circuit (13) detects the fall and generates the signal of FIG. 3 (C). Times of Day
Figure 3 of t ₃ rising signal (c), the second register (9)
Clock terminal. Then, the second register (9) captures and holds the data of the first register (10) at that time. Since this data is the same as that which the second register (9) had immediately before the test signal period,
The adjustment can be performed as soon as the first and second switches (1) and (2) are switched and the left and right stereo signals from the compact disc player (3) are applied. In other words, the balance adjustment circuit (6) does not need to perform re-adjustment, and becomes in an unnecessary adjustment state.

Therefore, according to the circuit of FIG. 1, even if the mode is temporarily switched from a certain mode to the test mode, the balance adjustment is not adversely affected.

FIG. 4 shows a specific example of the balance adjustment circuit (6) of FIG. 1, wherein (15) is a left input terminal to which a left stereo signal is applied, and (16) is a right input terminal to which a right stereo signal is applied. An input terminal, (17) is a left output terminal from which a left stereo signal is derived, (18) is a right output terminal from which a right stereo signal is derived,
(19) is a left attenuation circuit inserted in a left transmission line (channel), (20) is a right attenuation circuit inserted in a right transmission line (channel), (21) is a left and right output terminal (17) and (18) (22) is a signal generation circuit that generates a signal corresponding to the level ratio of the left and right stereo signals obtained respectively.
(1) a discriminating circuit for discriminating whether or not the output signal level is within a predetermined range; (23) an oscillating circuit which operates according to a timing signal obtained from the discriminating circuit (22); Compare the output signal of (21) with the reference voltage Vref,
A comparison circuit for generating a direction signal, (25) is a comparison circuit (2
An up-down circuit that generates an up signal or a down signal in accordance with the output signal of 4), and (26) is the oscillation circuit (2).
A counting circuit for counting the direction according to the output signal of the up-down circuit (25) using the output signal of (3) as a clock, and (27) a decoder for decoding the count value of the counting circuit (26). .

Now, for simplicity of explanation, there are three types of signals applied to the left and right input terminals (15) and (16); (A monaural signal).

The first in which only the left input signal is applied to the left input terminal (15)
In this state, an output signal sufficiently higher than the reference voltage Vref is generated at the output terminal of the signal generation circuit (21). Reference voltage V _A of the discrimination circuit (22), than the reference voltage Vref is set to a predetermined value large becomes a value, the reference voltage V _B is set to a predetermined value small becomes a value than the reference voltage Vref, the determination circuit (22) an output signal of "H" when the small than the large or V _B than the input signal V _a, the input signal to generate an output signal of "L" when it is between V _a and V _B . Thus, when the output signal of the signal generation circuit (21) is sufficiently higher than the reference voltage Vref, the output of the determination circuit (22) becomes "H" and the oscillation circuit (23) does not start operating. Therefore, the counting circuit (26) does not start counting, and the left and right attenuating circuits (19) and (20) are in the non-attenuated state.

The second in which only the right input signal is applied to the right input terminal (16)
In this state, an output signal sufficiently smaller than the reference voltage Vref is generated at the output terminal of the signal generation circuit (21). Also in this case, the output of the discrimination circuit (22) becomes "H", the oscillation circuit (23) does not operate, and the left and right attenuation circuits (19) and (20) are in the non-attenuation state.

In the third state where the left and right stereo signals of substantially the same level are applied to the left and right input terminals (15) and (16), the value of the output signal of the signal generation circuit (21) is near Vref. Therefore, the output signal of the discrimination circuit (22) becomes "L", the oscillation circuit (23) starts operating, and applies the output signal to the counting circuit (26) as a clock. On the other hand, the output signal of the signal generation circuit (21) is also applied to the comparison circuit (24) and is compared with the reference voltage Vref. Now, assuming that the output signal of the signal generation circuit (21) is higher than the reference voltage Vref, the output of the comparison circuit (24) becomes "H", and an up signal is generated from the up / down circuit (25). The counting direction of the counting circuit (26) is set to the up direction. Therefore, the counting circuit (26)
Performs counting in the up direction using the output signal of the oscillation circuit (23) as a clock. When the output signal of the signal generation circuit (21) is smaller than the reference voltage Vref, the output of the comparison circuit (24) becomes "L" and the up-down circuit (25)
The counting circuit (26) counts in the down direction in response to the down signal generated from.

The decoder (27) sequentially decodes the count value of the counting circuit (26) and drives the left and right attenuating circuits (19) and (20).
At this time, the output signal of the decoder (27) is
9) and the right attenuation circuit (20) is connected to the inverter (2
8) Since it is applied via the left and right attenuation circuit (19)
And (20) are controlled in opposite directions. If the level of the left output signal is higher than the level of the right output signal, the counting circuit (26) counts up, and the left attenuating circuit (1
The attenuation of 9) increases, and the attenuation of the right attenuation circuit (20) decreases. Conversely, when the level of the left output signal is lower than the level of the right output signal, the counting circuit (26) counts down, the attenuation of the left attenuation circuit (19) decreases, and the right attenuation circuit The attenuation of (20) increases. That is, the left and right attenuation circuits (19) and (20) are controlled in opposite directions.

As previously mentioned, the oscillation circuit (23), the output signal V _X of the signal generating circuit (21) is, as long as the range of _{V A> V X> V B} ,
Oscillation continues. Therefore, while the oscillation of the oscillation circuit (23) continues, the decoder (27) sequentially decodes the count value of the counter circuit (26) and controls the left and right attenuating circuits (19) and (20) to keep the balance state. Keep. Note that the counting circuit (26) has a limiter function, and is configured such that when a predetermined count is performed, no further counting can be performed.
Also, according to the control of the left and right attenuation circuits (19) and (20),
When the levels of the left and right stereo signals obtained at the left and right output terminals (17) and (18) are reversed, the counting direction of the counting circuit (26) is reversed, and a similar attenuation operation is performed.

The counter circuit (26) in FIG. 4 corresponds to the second register (9) in FIG. 1, and the value may be set to an intermediate value between up and down in response to the reset signal.

In addition, the present invention is not limited to two-channel stereo,
It is also applicable to multi-channel stereo such as 4-channel stereo.

(G) Effects of the Invention As described above, according to the present invention, readjustment of the balance adjustment circuit is unnecessary even in the test mode, and the adjustment time can be reduced. Further, since the adjustment is performed by digital processing, it is possible to provide a balance adjustment device which operates simply and has a simple structure.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional balance adjusting device, and FIGS. 3 (a) to 3 (c) are waveforms used for explaining FIG. FIG. 4 and FIG. 4 are specific circuit examples of the balance adjusting circuit (6) in FIG. (3)… compact disk player, (5)… test signal generator, (6)… balance adjustment circuit, (9)
… Second register, (10)… first register, (11)
... Detection circuit.

Claims (2)

(57) [Claims] 1. A balance adjustment device comprising a balance adjustment circuit capable of adjusting the balance of a signal from a signal source requiring balance adjustment between channels and holding the adjustment value, wherein the balance adjustment between channels is performed. An unnecessary test signal generator; a detection circuit for detecting that a test signal from the test signal generator is applied to the balance adjustment circuit; and a balance according to a first detection output signal of the detection circuit. And a first register that captures and holds the adjustment value of the adjustment circuit, and returns the adjustment value held in accordance with the second detection output signal of the detection circuit to the balance adjustment circuit. Adjustment device. 2. The balance adjustment circuit includes a second register. The first detection output signal is applied as a clock signal to the first register and a reset signal to a second register, and the second detection output signal is applied to the second register. 2. The balance adjusting device according to claim 1, wherein the output signal is applied to the second register as a clock signal.