JPH0456397B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory, particularly a MOSFET.
(Metal−Oxide−Semiconductor Field−Effect
MISFET (Metal
Insulator Semiconductor Field Effect
The present invention relates to a semiconductor memory configured with a Transistor (hereinafter abbreviated as MOS).

In addition, below, P-channel MOSFET and N-channel MOSFET are R-MOS and N-MOSFET, respectively.
A complementary MOSFET that combines both is called a CMOS.
Furthermore, a pair of data lines connected to a sense amplifier that are formed parallel to each other will be called a folded data line.

One object of the present invention is to provide a semiconductor memory that can reduce the probability of malfunction due to alpha rays.

An object of the present invention is to provide a sense amplifier that can stably obtain an output potential close to both power supply voltages for both logic "1" read information and logic "0" read information during sensing. .

Another object of the present invention is to provide a semiconductor memory in which the sense amplifier that operates stably and the memory cell that is resistant to alpha rays can be obtained through the same manufacturing process.

Another object of the present invention is to provide a semiconductor memory that can increase the speed of reading information from memory cells and reduce power consumption.

Another object of the present invention is to provide a novel semiconductor memory in which the above-mentioned sense amplifier that operates stably is connected to the folded data line and can reduce noise.

Another object of the present invention is to provide a small-sized semiconductor memory in which a complementary sense amplifier is connected to a folded data line to efficiently perform chip layout.

According to one embodiment of the present invention, a plurality of N-type well regions formed in the same process are provided on a P-type semiconductor substrate, and a P-well region serving as a memory cell is provided on the surface of each of the N-type well regions.
A semiconductor memory is provided in which a P-channel FET pair of a channel MISFET and a complementary sense amplifier is formed. With such a memory, a memory cell that is resistant to alpha rays and a high-speed and stable sense amplifier can be obtained at the same time just by using a normal complementary MOS IC process.

In addition, by making the memory cell P-MOS and changing the word voltage within the range of the power supply voltage V _CC and (V _CC − | V _thp |), it is possible to select information “1” or “0”. , a memory capable of high-speed operation is obtained.

According to another embodiment of the present invention, a semiconductor memory is provided in which a complementary sense amplifier is connected to a folded data line. With such a memory, there is a layout area that is approximately twice as large as that of a conventional memory in the data line pitch direction, making it possible to achieve high integration.

According to another embodiment of the present invention, a semiconductor memory is provided which includes means for precharging the folded data line to a potential intermediate between logic "1" and "0" of the memory cell. According to such a memory, the read time is determined by a change in the potential of the data line by half of the potential of logic "1" and "0", so a high-speed memory with low power consumption can be obtained.

Further, the coupling noise between the word line and the data line is canceled out because plus and minus noises are generated on the folded data line, respectively.

Furthermore, since the data line is precharged to a potential intermediate between the logic "1" and "0" of the memory cell and used as a reference potential, dummy cells can also be omitted, and a memory with a small chip area can be obtained.

According to another embodiment of the present invention, the positive feedback operation of the P-channel FET pair of the sense amplifier and the positive feedback operation of the N-channel FET pair of the sense amplifier are started at different times, so that there is no through current and the power consumption is reduced. Gain power memory.

According to another embodiment of the present invention, the P channel FET pair of the complementary sense amplifier and the N
A semiconductor memory is provided in which a channel FET pair is arranged at both ends of a memory array. With such a memory, the layout within the chip can be separated into a P channel group and an N channel group, so that efficient integration is possible.

According to another embodiment of the present invention, the folded data line is made of Al, so that the wiring resistance is extremely low and highly reliable operation is possible.

According to another embodiment of the present invention, a semiconductor memory is provided in which an N-type well region forming a memory cell has an epitaxial structure. According to such a memory, it is possible to obtain a uniform well with a desired concentration, so that the threshold voltage can be controlled and the junction capacitance can be made smaller than in the case of diffusion, so that a high-speed memory can be obtained. Furthermore, since the well surface concentration can be made smaller than in the case of diffusion, a memory with high breakdown voltage can be obtained.

According to another embodiment of the present invention, there is provided a semiconductor memory in which well bias wiring is formed in the plurality of N-type well regions in parallel with the data line. According to such a memory, the well voltage becomes substantially uniform and the well resistance can be reduced, so that a memory with less influence of noise can be obtained.

According to another embodiment of the present invention, a semiconductor memory is provided in which a well region forming the memory cell and a well region forming the sense amplifier are separated. With this kind of memory, the noise generated by the sense amplifier does not affect the memory cells, so
Highly reliable operation is possible.

[Configuration and operation of dynamic memory system]

The configuration of the dynamic memory system will be explained with reference to FIG. First, the block diagram surrounded by dotted lines shows a dynamic memory system, and this system consists of a D-RAM IC.
It consists of an interface circuit between ARRAY (hereinafter referred to as D-RAM) and the central processing unit of the computer (hereinafter referred to as CPU, not shown) and D-RAM.

Next, the above dynamic memory system and CPU
The input/output signals between the First, address signals _A0 to _Ak are signals for selecting the address of the D-RAM. REFGRNT is a refresh instruction signal for refreshing memory information in the D-RAM. is the write enable signal, and D
- Data read and write command signals in RAM. MS is a memory activation signal that starts the memory operation of the D-RAM. _D1 to _D8 are
This is input/output data on a data bus connecting the CPU and D-RAM. REFREQ is a refresh request signal for D-RAM memory information.

Next, the dynamic memory system is D-RAM.
and the above-mentioned interface circuit will be explained separately.
First, D-RAM is an nk-bit integrated circuit (hereinafter referred to as nk
It is called. Note that 1k bits indicates 2 ¹⁰ =1024 bits. ) are arranged in m columns and B in rows, and (n
×m) A matrix of words × B bits is constructed.
It consists of an IC array.

Next, the interface circuit will be explained. RAR
is a row address receiver that receives address signals A ₀ to A _i out of address signals A ₀ to A _k sent from the CPU and converts them into address signals with timing suitable for D-RAM operation, and CAR is the above-mentioned row address receiver. Among address signals A ₀ to A _k , address signals A _i+1 to _{A j}
ADR receives address signals A _j+1 to A _k from among the above address signals A ₀ to A _k , This is an address receiver that converts address signals to timing appropriate for D-RAM operation.

DCR is a chip selection control signal (hereinafter referred to as CS ₁ to CS _n) for selecting a D-RAM chip.
m=2 ^kj ).

RAS-CT is a RAS control circuit that sends out a chip selection signal and a row address capture signal at timings suitable for the operation of the D-RAM.

ADM uses the above address signals A ₀ ~A _i and A _i+1 ~
This is an address multiplexer that multiplexes A _j in time series and sends it to the D-RAM.

RSG is a refresh synchronization generating circuit that determines the timing for refreshing memory information in the D-RAM.

RAC is a refresh address counter that sends refresh address signals R ₀ to _{R l} to refresh memory information in the D-RAM.

DBD is a data bus driver in which data input/output between the CPU and D-RAM is switched by signals.

C-CT is the above RAC, ADM, RAS-CT,
This is a control circuit that sends out signals that control CBD and D-RAM.

Next, the function of address signals within the dynamic memory system will be explained.

Address signals _A0 to Ak sent from the CPU are address signals _A0 to _Ak within the dynamic memory system.
It is separated into two functions: ~A _j and address signal A _j+1 ~ _{A k} .

That is, address signals A ₀ -A _j are used as address signals for the memory matrix within each chip of the D-RAM.

Further, address signals A _j+1 to A _k become chip selection signals for selecting whether or not to select the entire chip when viewed from the D-RAM chip.

Here, the address signals A ₀ to A _j are the address signals A 0 to A j according to the matrix in the D-RAM IC chip.
A ₀ ~ A _i for IC chip array row selection, A _i+1 ~
It is designed to assign A _j to column selection of IC chip array.

Next, the circuit operation within the dynamic memory system will be explained.

First signal, ₁ to _n signal,
The RAS _a and _b signals are row address strobe signals, and the RAS signal is a column address strobe signal.

First, address signals A ₀ to _{A i} and A _i+1 to A _j are applied to ADM via RAR and CAR, respectively.

In ADM, when _{the b} signal reaches a certain level, row address signals _A0 to _Ai are sent out, and D-
Applied to the RAM address pin. At this time,
Column address signals A _i+1 to A _j are not sent out.

Next, when _{the b} signal becomes the opposite level to the above, column address signals A _i+1 to A _j are sent from the ADM.
Applied to the above address terminal. At this time, the row address signals A ₀ to A _i are not sent out from the ADM.

In this way, the above address signals A ₀ to A _i and
A _i+1 to A _j are applied to the address terminals of the D-RAM in time series depending on the level of _{the b} signal.

In addition, the refresh control signal is applied to ADM and RAC.
Since R _cs is not applied, the refresh address signals R ₀ to _{R l} are not sent out from the ADM.

In addition, the chip selection signals A _j+1 to A _k are converted through the DCR into chip selection control signals CS 1 to CS n (m=2 kj) that mainly select chips in the D-RAM, and are further converted to chip selection control signals CS ₁ to CS _n (m=2 ^kj ) by _{the a} signal. The signals are then converted into ₁ to _n signals with controlled timing and used as chip selection signals and row address capture signals.

Next, the operation of setting addresses within the chip in each column of the D-RAM will be explained.

First, row address signals A ₀ -A _i are applied to the address terminals of all IC chips of the D-RAM.

After that, it is assumed that when _one signal, for example, one signal among the ₁ to _n signals reaches a certain level, the top B ICs are selected. At this time, the row address signals A ₀ -A _i are taken into the row addresses of the memory matrix array in the IC (IC ₁₁ , CI ₁₂ , -IC _1B ) chips. Here, the reason why the row address signals A ₀ to _{A i} are applied to the IC before _{the 1} signal is that if the ₁ signal is applied before the row address signals A ₀ to _{A i} ,
This is because there is a possibility that a signal other than the row address signal may be taken in.

Next, column address signals A _i+1 to _{A j} are applied to D-RAM
applied to the address pins of all IC chips.

Thereafter, when the signal delayed from _{the 1} signal reaches a certain level, the column address signals A _i+1 to A _j of the column address of the memory matrix array in the top nk, B IC chips are taken in. Here, the above column address signals A _i+1 to _{A j} are
The reason why it is applied to the IC before the CAS signal is the same as the reason above.

Also, the function of the signal is the row address signal.
The purpose is to distinguish which signal is being sent, A ₀ to A _i or column address signals A _i+1 to _{A j} .

By the above operation, the top stage nk of D-RAM, B
In-chip addresses are set.

In addition, the ICs excluding the top stage of D-RAM are ₂ ~
Since the RAS _n signal is at the opposite level to the level of ₁ , it is not selected.

Next, the data write and read operations at the addresses set above will be explained.

Data write and read operations are designed to be determined by the high level or low level of a write enable signal (hereinafter referred to as a signal).

A write operation is performed by sending data D _I1 from the CPU to the address set above when the signal is at a certain level.
~D _IB is applied.

The read operation is performed by outputting the data D ₀₁ to D _0B of the respective addresses for which writing has been completed in B bits when the signal is at the opposite level.

[Function of control signal]

Abbreviations mean the function of the signal, and those with an inverted symbol (bar) above the abbreviation indicate the function of the meaning of the abbreviation when the signal is “0” (Low Level). is executed, and if there is no bar symbol, it means that it will be executed when it is “1” (High Level).

C-CT is a command signal from the CPU, i.e.
Receives REFGRNT signal, signal, MS signal,
CAS signal, _a signal, _b signal signal, R _cs
Send each signal. The functions of these sent control signals will be explained.

Which of the row address signals A ₀ to _{A i} or column address signals A _i+1 to _{A j} is D−?
This is a signal to determine whether the signal is being sent to each chip in the RAM, and a signal to take in the column address signal of the IC chip.

_a is a signal for supplying the CS ₁ to CS _n signals to the IC chip array in the D-RAM at the same timing.

The signal is a signal for deciding whether to read data from or write data to a memory cell in the D-RAM IC chip.

The R _cs signal is a signal for starting the refresh operation and prohibiting the sending of the address signals A ₀ to _{A i} , A _i+1 to A _j in the ADM, and for sending the refresh address signals R ₀ to _{R l} from the RAC. It is.

_{The b} signal is the row address signal A ₀ ~ from ADM.
It is a switching timing signal for converting A _i and column address signals A _i+1 to _{A j} into time-series multiplexed signals, and one of the ( ₁ to _n ) signals.
is selected, the switching timing of row addresses A ₀ to _{A i} and column address signals A _i+1 to A _j is determined from signal a so that row address signals A 0 to _A i are output _from ADM. The signal is delayed.

Next, the relationship between the signals and the data bus driver (DBD) will be explained.

The signal sent from C-CT is applied to D-RAM and DBD. For example, when the signal is at a high level, a read mode is entered, and data in the D-RAM is output and sent to the CPU via the DBD.
At this time, the input data is controlled by a signal so as not to be taken in from the DBD to the D-RAM.
When the signal is at a low level, the write mode is entered, and input data from the CPU is applied to the data input terminal of the D-RAM via the DBD, and data is written to the set address. At this time D-
The data output of RAM is controlled by a signal so that it is not output from DBD.

[Refresh operation]

A D-RAM memory cell circuit retains information by storing charge in a MOS capacitor, and this charge disappears over time due to leakage current. The problem here is information “1”
(High Level) charge disappears and becomes lower than the reference level for distinguishing between information "1" and "0" (Low Level), information "1" will be discriminated as "0" and a malfunction will occur. be. Therefore, in order to continue storing information "1", it is necessary to refresh the charge before it decreases below the reference level. This refresh operation must be performed within the information storage time of the memory cell. Therefore, this refresh mode has priority over read mode and write mode.

Next, the refresh operation will be explained with reference to FIG.

First, the refresh synchronization generation circuit (hereinafter referred to as
It is called RSG. ) sends a refresh request signal (hereinafter referred to as REFREQ) to (information storage time)/
It is sent to the CPU every (number of refresh cycles). (Note that the number of refresh cycles is equivalent to the number of word lines connected to the column data line.) Upon receiving the above REFREQ, the CPU sends out a refresh instruction signal (hereinafter referred to as REFGRNT). At this time, the CPU does not send out a write enable signal (hereinafter referred to as a signal) and a memory activation signal (hereinafter referred to as MS).
The above REFGRNT is the control circuit (hereinafter referred to as C
- Referred to as CT. ), its output signal, the refresh control signal (hereinafter referred to as R _cs ), is applied to the address multiplexer (hereinafter referred to as ADM
It is called. ) and a refresh address counter (hereinafter referred to as RAC). Then, the ADM sends address signals R _{0 -R l exclusively} for refresh to the D-RAM in place of the address signals A ₀ -A j for random access, using the R _cs signal.

Refresh methods for D-RAM can be roughly divided into two. One method is to sequentially refresh each column of the IC chip array (IC ₁₁ , IC ₁₂ , . . . , IC _1B is one column). This method has the advantage that the power consumption required for refreshing is small, but has the disadvantage that it takes time for refreshing.

Another method is to refresh the entire D-RAM IC chip array at the same time. Although this method is not shown in Fig. 1, the address signals A _j+1 to A _k from the address receiver are sent to the RAS control circuit (hereinafter referred to as RAS-CT) without passing through the decoder (hereinafter referred to as DCR). ), and all output signals of RAS-CT ₁ ~
When RAS _n reaches a certain level, all columns of D-RAM
Refreshing is performed by simultaneously selecting ICs.

The advantage of this is that the time required for refreshing is short, and the disadvantage is that it consumes a lot of power.

Next, the refresh operation in the matrix array in the D-RAM IC will be explained.

Refresh address signals R ₀ to R _l are applied from ADM to the address terminals of D-RAM, and then
When the RAS signal reaches a certain level, 2l ⁺¹ row addresses of the IC matrix array are sequentially selected.
At this time, the signal is at the opposite level to the above. Therefore, refreshing is performed by amplifying the information in the memory cells connected to the selected row address using a sense amplifier (not shown) so as to widen the level difference between "1" and "0". There is.

Note that the signal is D- during the refresh operation.
Since it is not sent to RAM and DBD, DBD
No data is input or output from the .

[Function of RAS system signals and CAS system signals]

RAS system signals (hereinafter referred to as RAS-φ) and
The function of the CAS system signal (hereinafter referred to as CAS-φ) will be explained with reference to FIG.

(1) RAS- _φφAR is an address buffer control signal, which is applied to an address buffer (hereinafter referred to as ADB) and latched to ADB. Levels a ₀ , ₀ , ... corresponding to row address signals A ₀ to A _i
a _i , _i is a row/column decoder (hereinafter referred to as RC-
This is a signal that determines whether or not to send data to the DCR.

φ _x is the word line control signal, which is RC−
DCR is applied to the memory array (hereinafter referred to as M-
It is called ARY. This signal determines whether or not to send one signal selected for selecting the row address of ) to M-ARY.

_φPA is a sense amplifier control signal, which is applied to the sense amplifier and drives the sense amplifier.

(2) CAS−φ φ _AC is the address buffer control signal, which is applied to ADB and latched to ADB.
Levels corresponding to column address signals A _i+1 to A _j
This is a signal that determines whether or not to send a _i+1 , _i+1 , ...aj, to the RC-DCR.

φ _Y is the column switch control signal, which is
This signal is applied to RC-DCR and selects the column switch connected to the M-ARY column data line by one selected signal.

φ _OP is the data output buffer and output amplifier control signal, which is referred to as the data output buffer (hereinafter referred to as
It is called DOB. ) and an output amplifier (hereinafter referred to as OA), and is a signal sent to a data ( _Dput ) terminal that outputs read data from the M-ARY.

φ _RW is a data input buffer control signal, which is a data input buffer (hereinafter referred to as DIB).
This signal is applied to the input data (D _io ) terminal and causes the write data from the input data (D io ) terminal to be sent to the M-ARY.

is the data output buffer control signal,
This is a signal applied to DOB to prevent read data from being output to the data output ( _Dput ) terminal during a write operation.

[D-RAM configuration and operation]

The configuration of the D-RAM will be explained with reference to FIG.
A block surrounded by a dotted line indicates a D-RAM integrated circuit (hereinafter referred to as IC).

In the above IC, the block surrounded by the two-dot chain line is the timing pulse generation block, and D-
It consists of circuits that generate signals that control the operation of each circuit in the RAM.

Next, the operation of each circuit of the D-RAM will be explained according to the timing diagram of FIG.

When the row address signals A ₀ -A _i are taken into an address buffer (hereinafter referred to as ADB) and latched, the signals become low level with a delay from the row address signals A ₀ -A _i . Here, the reason why the signal is delayed from the low level signals A ₀ to _{A i} is to ensure that the row address signals A ₀ to A _i are taken in as the row address in the memory array.

Next, the signal φ _AR delayed from the signal is applied to ADB, and the levels a ₀ , _{0 ,} . ). When the above-mentioned levels a ₀ , ₀ , a _i , and _i are applied to RC-DCR, only the selected RC-DCR remains at high level, and the unselected one remains at low level.

Then, when the signal φ _X delayed from φ _AR is applied to RC-DCR, the selected signal is M-ARY
sent to. Here, the reason why _φX is delayed from _φAR is that the RC-DCR is operated after the ADB operation is completed. In this way, the row address in M-ARY is one of the 2 ^{i + 1} output signals of RC-DCR.
Since one line will be at a high level, the corresponding M
-Set by selecting one row address line in ARY.

Next, “1” of the memory cell connected to the selected one row address line in M-ARY
Alternatively, "0" information is amplified by a sense amplifier (hereinafter referred to as SA). This SA operation starts when φ _PA is applied.

After that, column address signals A _i+1 ~ _{A j} are ADB
Column address signal
The signal becomes low level with a delay from A _i+1 to A _j . Here, the signal is column address signal A _i+1
The reason for delaying ~A _j is to ensure that the column address signal is taken in as the column address in the memory array.

Next, when the signal φ _AC delayed from the signal is applied to ADB, the levels a _i+1 , _i+1 , . . . aj, corresponding to the column address signal are sent to the RC-DCR. Then, RC-DCR performs the same operation as above. The selected signal is sent to the column switch (hereinafter referred to as C-SW) when the signal φ _Y delayed from φ _AC is applied to RC-DCR.
Thus, the column address in M-ARY is AD
- Since one of the 2 ^ji output signals of DCR becomes high level, one C-SW is selected, and the column address line, that is, the data line connected to this C-SW, is selected. Set by.

In this way, one address within the M-ARY is set.

Next, read and write operations for the addresses set as described above will be explained.

In read mode, the signal is at high level. This signal is designed to go high before going low.
This is because when the signal goes to low level, one address of M-ARY is set as a result, so the signal is set to high level before that to prepare for the read operation and shorten the read start time. .

Also, when the CAS system signal φ _OP is applied to the output amplifier, the output amplifier becomes active, the information at the address set above is amplified, and the data is output via the data output buffer (hereinafter referred to as DOB). ( _Dput ) terminal. Reading is performed in this manner, and the read operation is completed when the signal becomes high level.

Next, in the write mode, the signal becomes low level. The signal φ _RW created by this low level signal and the low level signal becomes high level and the data input buffer (hereinafter referred to as DIB
It is called. ), DIB becomes active and the write data from the input data (D _io ) terminal is sent to the address set in the M-ARY, thereby performing a write operation.

At this time, an inverted signal of the above-mentioned φ _RW , that is, a low level signal _RW is applied to DOB to control so that data is not read out during the write operation.

[Configuration and operation of D-RAM transistor circuit]

FIG. 4A shows one of the circuit configurations of the D-RAM of the present invention.
An example is shown. The present invention will be explained below based on Examples.

1 Configuration of memory cell M-CEL A 1-bit M-CEL consists of a capacitor C _S for information storage and a P-MOSQ _M for address selection. Information of logic “1” and “0” is sent to the capacitor C _S. It is stored as having or not having a charge.

The gate of P-MOS Q _M is connected to the word line,
One of the source and drain is connected to the data line, and the other to the capacitor _CS .

2 Switching operation of memory cell M-ECL The gate voltage, that is, the word voltage of P-MOS _QM changes from the power supply voltage V _cc to the threshold voltage V _thp (P-
When the threshold voltage of MOS Q _M decreases by
MOS Q _M is turned on, and memory cell M-CEL can be selected.

In addition, when using N-MOS for the memory cell (not shown), the word voltage can be changed from 0V to (V _cc −
V _tho ) (V _tho ; threshold voltage of N-MOS Q _M ), N-MOS Q _M is turned on and memory cell selection becomes possible.

Therefore, the switching speed of P-MOS Q _M is
Since logic “1” and “0” information can be determined only between V _cc and |V _thp |, the switching speed is considerably faster than that of N-MOS _QM .
A detailed explanation of the switching operation of _QM is available in patent application 54-
119403, so it will be omitted.

3 Sense amplifier configuration Sense amplifiers SA ₁ and SA ₂ convert the difference in potential change that occurs on the folded data lines DL _1-1 and _{DL 1-1} during address into the sensing period determined by the timing signals φ _PA and _PA (sense amplifier control signal). It is an expanding sense amplifier, and its input/output nodes are coupled to a pair of parallelly arranged folded data lines DL _1-1 , _1-1 .

Sense amplifiers SA ₁ and SA ₂ are connected in parallel and can be considered as one sense amplifier, but while SA ₁ is composed of N-MOS, SA ₂ is of the opposite conductivity type. The difference is that it is composed of P-MOS. Each sense amplifier is connected to a pair of cross-connected FETs and its source side for positive feedback differential amplification operation.
It consists of a FET for controlling positive feedback differential amplification operation.

As mentioned above, sense amplifiers SA ₁ and SA ₂ can be considered as one complementary sense amplifier, so they can be placed next to each other. However, considering the arrangement and shape of wiring, transistors, well regions, etc. For efficient accumulation, space them apart from each other (for example, at both ends of the M-ARY) as shown in Figure 4A.
It can also be placed.

In other words, the sense amplifier SA ₂ composed of P-MOS, the sense amplifier SA ₁ composed of the memory array M-ARY and N-MOS, and the precharge circuit PC can be arranged separately, so that the circuit inside the chip can be separated. The arrangement can be separated into a P-MOS section and an N-MOS section, allowing efficient integration.

Folded data line DL _1-1 , _1-1 is Al, Au, Mo,
It is made of metal such as Ta or W. Since the metal has a very low resistance value, the voltage drop of the data line during operation is small and no malfunction occurs.

4 Precharge circuit configuration The precharge circuit PC connects the data line to the power supply voltage V _cc
A pair of N-MOS Q _S2 and Q _S3 for precharging to about half of (V _DP )
These N-MOSs are designed to have a lower threshold voltage than other N-MOSs, as indicated by the symbol * in the _figure .

The numbers of memory cells coupled to the folded data lines DL _1-1 and _{DL 1-1} are made equal to increase detection accuracy. Each memory cell is coupled between one word line WL and one of the folded data lines. each word line
Since WL crosses a pair of data lines, even if a noise component generated on word line WL is transferred to the data line due to capacitive coupling, the noise component appears equally on both data lines, and the differential type sense Amplifier SA ₁ ,
offset by SA ₂ .

5 Circuit Operation The circuit operation of FIG. 4 will be explained with reference to the operation waveform diagram of FIG. 4B.

When the precharge control signal φ _PC is at a high level (higher than V _cc ) before reading the storage signal of the memory cell, the N-MOS Q _S2 and Q _S3 become conductive, and the folded data lines DL _1-1 and _1-1 are turned on. Stray capacitance C ₀ , ₀ is approximately 1/2V _cc
will be pre-charged. At this time, N-MOS Q _S1
are conductive at the same time, so even if an imbalance occurs in the precharge voltages caused by the N-MOS Q _S2 and Q _S3 , the folded data lines DL _1-1 and _{DL 1-1} are short-circuited and set to the same potential. The V _th of N-MOS Q _S1 to Q _S3 is set lower than that of transistors without an asterisk so as to prevent voltage loss between the respective sources and drains.

On the other hand, the capacitor C _S in the memory cell maintains a potential of approximately zero volts when the written information is a logic "0", and maintains a potential of approximately V _cc when the written information is a logic "1". The precharge voltage V _DP is set between both storage potentials.

_Therefore , when the read line control signal _φ
becomes higher than V _DP when information of “1” is read, and becomes lower than V _DP when information of “0” is read. By comparing the potential of the above data line with the potential of the other data line that maintains the V _DP potential, the information of the addressed memory cell is set to "1".
It can be determined whether it is "0" or "0".

The positive feedback differential amplification operation of the sense amplifiers SA ₁ and SA ₂ starts when FET Q _S7 Q _S8 starts conducting by the timing signal (sense amplifier control signal) φ _PA , and Based on the potential difference, the higher data line potential (V _H ) and the lower data line potential (V _L ) change toward V _cc and zero potential V _GND , respectively, and the difference widens. N-
Sense amplifier SA ₁ consisting of MOS Q _S7 , Q _S8 , Q _S9
contributes to lowering the potential of the data line to the zero potential V _GND , and the sense amplifier SA ₂ consisting of P-MOS, Q _S4 , Q _S5 , and Q _S6 raises the potential of the data line to V _cc . contributes to Each sense amplifier SA ₁ and SA ₂ operates in source common mode.

In this way, the potential of (V _L −V _GND ) changes to the sense amplifier.
When the threshold voltage V _tho of the N-MOS Q _S7 and Q _S8 of SA ₁ becomes equal, the positive feedback operation of the sense amplifier SA ₁ ends. Furthermore, when the potential of (V _cc −V _H ) becomes equal to the threshold voltage of P-MOS Q _S5 and Q _S6 of sense amplifier SA ₂ and V _thp , the positive feedback operation of sense amplifier SA ₂ ends. . Eventually, V _L reaches zero potential and V _H reaches V _cc , becoming stable in a low impedance state.

Note that sense amplifiers SA ₁ and SA ₂ may start operating at the same time, SA ₁ may start operating before SA ₂ , or SA ₂ may start operating before SA ₁ . In terms of read speed, it is faster to operate SA ₁ and SA ₂ simultaneously, but power consumption increases due to the flow of through current. On the other hand, by making the operation start timings of SA ₁ or SA ₂ different, there is an advantage that through current is eliminated and power consumption is reduced, but the read speed is slightly inferior to the above.

FIG. 4C shows another embodiment of the circuit configuration of the D-RAM of the present invention. Portions corresponding to those in FIG. 4A are designated by the same reference numerals. The difference from FIG. 4A is that the positive feedback operation control means of _SA1 is composed of N-MOS Q _S9 and Q _S10 connected in parallel.

The operation of sense amplifiers SA ₁ and SA ₂ will be explained according to FIG. 4D. The return data line is approximately 1/2 in advance.
Assume that it is charged to V _cc .

FET for positive feedback operation control means of sense amplifier SA ₁
When Q _S10 is made conductive by the sense amplifier control signal φ ₁ , only one of FET Q _S7 or FET Q _S8 is made conductive, and the potential (V _L ) of the lower data line is slightly lowered toward the zero potential V _GND . let At this time,
The potential (V _H ) of the higher data line does not change because either FET Q _S7 or FET Q _S8 is non-conducting.
Note that the conductance of FET Q _S10 is designed to be smaller than that of FET Q _S9 .

Next, the FET is controlled by the sense amplifier control signal _φPA.
When Q _S9 starts to conduct, the sense amplifier SA ₁ starts a positive feedback operation and changes the potential V _L toward the zero potential V _GND .

In other words, after slightly widening the potential difference between the folded data lines using the sense amplifier control φ ₁ , the sense amplifier control signal φ _PA is applied, and the sense amplifier SA ₁
If the positive feedback operation of the sense amplifier is performed, even if the potential difference between the folded data lines is small, the sense amplifier
It becomes possible to amplify with SA ₁ . In other words, the sensitivity of the sense amplifier improves.

Next, the positive feedback differential amplification operation of sense amplifier SA ₂ is
It begins when FET Q _S4 begins to conduct by sense amplifier control signal φ _PA or φ ₁ , and the potential of the higher data line (V _H ) rises toward V _cc .

The potential of the data line is finally _VL , which is zero potential.
V _H reaches V _cc and becomes stable in a low impedance state.

FIG. 4E shows another embodiment of the circuit configuration of the D-RAM of the present invention. Portions corresponding to those in FIG. 4A are designated by the same reference numerals. The difference from FIG. 4A is that a dummy cell D-CEL is connected to the folded data line.

The configuration of the dummy cell D-CEL consists of a series connection circuit of P-MOS Q _D1 and P-MOS Q _D2 .
The gate of MOS Q _D1 is connected to the dummy word line, one of the source and drain is connected to the data line, and the other is connected to the P-
It is connected to one of the source and drain of MOS Q _D2 , and the other is grounded.

The dummy cell D-CEL does not require a capacitor C _ds to store the reference potential. This is because the data line is precharged with the reference potential. Dummy cell D-CEL has the same manufacturing conditions as memory cell M-CEL,
Made with the same design constants.

The dummy cell D-CEL has the function of canceling out various noises generated on the folded data line during memory information writing and reading operations.

[Time-series operation of D-RAM transistor circuit]

The time-series operation of the D-RAM transistor circuit will be explained according to FIG. 4A.

1 Read signal amount To read information, turn on P-MOS Q _M and turn on C _S
to the common column data line DL, and connect the data line to the common column data line DL.
This is done by sensing how the potential of DL changes depending on the amount of charge accumulated in _CS . If the potential previously charged in the stray capacitance _C0 of the data line DL is set to half the power supply voltage, that is, 1/2V _cc , the information stored in C _S becomes "1".
(potential of V _cc ), the potential of data line DL (V _DL ) “1” at the time of address is V _cc・(C ₀ +
2C _S )/2(C ₀ +C _S ), which is “0” (0V)
When the temperature is high, (V _DL ) “0” is V _cc・C ₀ /2 (C ₀ +
C _S ). Here, the difference between logic "1" and logic "0", that is, the detected signal amount △V _S is △V _S = (V _DL ) "1" - (V _DL ) "0" = V _cc・C _S /(C ₀ +C _S )=(C _S /C ₀ )・V _cc /{1+(C _S /C ₀ )}.

Since the memory cells are made small and many memory cells are connected to a common data line to create a highly integrated and large-capacity memory matrix, C _S ≪ C ₀ , that is, (C _S /C ₀ ) is smaller than 1. The value is almost negligible. Therefore, the above formula is △V _S V _cc・
It is expressed as (C _S /C ₀ ), and ΔV _S is an extremely small signal.

2 Read operation Precharge period This is exactly the same as the precharge operation described above.

Row address period timing signal (address buffer control signal)
The row address signals A ₀ to A _j supplied from the address buffer ADB at the timing of φ _AR (see Figure 3) are decoded by the row/column decoder RC-DCR, and are synchronized with the rising edge of the word line control signal _φ At the same time, addressing of memory cell M-CEL is started.

As a result, a voltage difference of approximately ΔV _S occurs between the folded data lines DL _1-1 and _1-1 based on the stored contents of the memory cells, as described above.

Sensing timing signal (sense amplifier control signal) When N-MOS Q _S9 starts conducting due to φ _PA , sense amplifier SA ₁ starts a positive feedback operation and amplifies the detection signal of ΔV _S generated at the time of address. At the same time as this amplification operation or after the start of the amplification operation, the sense amplifier SA ₂ starts a positive feedback operation by the timing signal φ _PA and restores the logic "1" level to _Vcc .

Data output operation timing signal (address buffer control signal) Column address signals A _i+1 to A _j sent from the address buffer ADB in synchronization with φ _AC are decoded by the row/column decoder RC-DCR, and then Timing signal (column switch control signal)
The information stored in the memory cell M-CEL at the column address selected by φ _Y is transferred to the common input/output lines CDL ₁ , ₁ via the column switch C-SW ₁ .
transmitted to.

Next, the timing signal (data output buffer and output amplifier control signal) φ _CP is used to control the output amplifier
The data output buffer OA&DOB operates and the read memory information is sent to the chip's output terminal D _put . Note that this OA&DOB is a timing signal (data output buffer control signal) when writing _RW
is disabled by

3 Write Operation Row Addressing Period The precharge, addressing, and sensing operations are exactly the same as the read operation described above. Therefore, regardless of the logic value of the input write information D _io , the storage information of the memory cell to which writing is originally to be performed is read to the folded data lines DL _1-1 , _1-1 .
Since this read information is to be ignored in the write operation described later, the operation up to this point can be considered to be essentially row address selection.

Write period Similar to the read operation, the folded data lines DL _1-1 , _1-1 located in the selected column are connected to the common input via column switch C-SW ₁ in synchronization with the timing signal (column switch control signal) _φY . output line
Combined with CDL ₁ , ₁ .

Next, complementary write input signals d io _{and io} supplied from the data input buffer DIB in synchronization with the timing signal (data input buffer control signal) φ _RW are applied to the memory cell M- through the column switch C- _SW1 .
Written to CEL. At this time, the sense amplifier
SA is also working, but the output impedance of the data input buffer DIB is low, so the data line is folded back.
The information appearing in DL _1-1 and _1-1 is determined by the information in D _io .

4. Refresh operation The refresh operation is to temporarily read the information that is being lost stored in the memory cell M-CEL to the column common data line DL, and then restore the read information to the restored level by the sense amplifiers SA ₁ and SA ₂ . This is done by writing to memory cell M-CEL. Therefore, the refresh operation is similar to the row addressing or sensing period operation described in the read operation. However, in this case, the column switch C- _SW1 is made inactive and refresh is performed simultaneously for all columns and for each row in turn.

[2-mat type 64K-D-RAM circuit configuration] Figure 5A shows approximately 64K-bit memory cells each having a storage capacity of 128 columns (rows) x 256 rows (columns) = 32768 bits (32K bits). memory cell matrix (memory array M-ARY ₁ , M
_-ARY2 ) is shown. The main blocks in this figure are drawn according to their actual geometrical arrangement.

The row address selection line (word line WL) of each memory array M-ARY ₁ , M-ARY ₂ has 2 ⁷ = 128 which is obtained based on the row address signals A ₀ to _{A 6} .
The corresponding decode output signals are applied from each row decoder (and word driver) R-DCR ₁ and R-DCR ₂ .

The column decoder C-DCR provides 128 decoded output signals based on column address signals _A9 to _A15 . This column selection decode output signal is common to the left and right memory arrays and adjacent upper and lower columns in each memory array, that is, to a total of four columns.

Address signals A ₇ and A ₈ are assigned to select any one of these four columns. For example, A ₇ is assigned to left/right selection, and A ₈ is assigned to top/bottom selection.

The φ _yij signal generation circuit φ _yij -SG decodes four combinations based on the address signals A ₇ and A ₈ , and the columns are decoded based on the output signals φ _y00 , φ _y01 , φ _y10 , and φ _y11 . The column switch selectors CSW-S ₁ and CSW-S ₂ are used for switching.

In this way, the decoder for selecting a column of the memory array includes the column decoder C-DCR and the column switch selectors CSW-S ₁ and CSW-
It is divided into two stages of S ₂ . The purpose of dividing the decoder into two stages is, first, to prevent unnecessary blank areas from occurring within the IC chip. In other words, the vertical arrangement interval (pitch) of the NOR gates, which have a relatively large area and carry the pair of left and right output signal lines of the column decoder C-DCR, is made to match the column arrangement pitch of the memory cells. That is, by dividing the decoder into two stages, the number of transistors forming the NOR gate can be reduced, and the area occupied by the NOR gate can be reduced.

The second aim of dividing the decoder into two stages is to
By reducing the number of NOR gates connected to one address signal line, the load on one address signal line is reduced and switching speed is improved.

The address buffer ADB receives eight multiplexed external address signals _A0 to _A7 ;
A ₈ to _{A 15} are respectively converted into eight types of complementary pair address signals (a ₀ , ₀ ) to (a ₇ , ₇ ); (a ₈ , ₈ ) to (a ₁₅ ,
_a15 ) and sent to the decoder circuit at timings φ _AR and φ _AC that match the operations within the IC chip.

[Two-mat type 64K-D-RAM circuit operation] The circuit operation in the address setting process in the two-mat type 64K-D-RAM will be explained with reference to FIGS. 5A and 5B.

First, when the row-related address buffer _control signal φ _AR rises to a high level, seven types _{of complementary pair row address signals (a 0 , 0 ) to} (a ₆ , ₆ ) are applied from the address buffer ADB to the row decoders R- _DCR1 and R- _DCR2 via the row address line R-ADL.

Next, the word line _control signal _φ
DCR ₂ becomes active and each memory array M-
One each of the word lines WL of ARY ₁ and M-ARY ₂ is selected and set to high level.

Next, the column system address buffer control signal φ _AC
By rising to high level, seven types of complementary pair column address signals ( _{a9 , 9} ) to ( _a15 , ₁₅ ) corresponding to column address signals A9 to _A15 are transferred from the address buffer ADB to the column. Address line C-
It is applied to the column decoder C-DCR via ADL.

As a result, one pair of the 128 pairs of output signal lines of the column decoder C-DCR becomes high level, and this high level signal is transmitted to the column switch selector CSW-
Applied to S ₁ and CSW−S ₂ .

Next, when the column switch control signal φ _Y rises to a high level, the φ _yij signal generating circuit φ _yij -SG becomes operational.

On the other hand, when the address buffer control signal φ _AR becomes high level, the complementary pair signal (a ₇ , ₇ ) corresponding to the address signal A ₇ becomes the complementary pair signal (a ₈ , 7 ) corresponding to the address signal A ₈ . , ₈ ) are respectively applied to the φ _yij signal generating circuit φ _yij −SG when the address buffer control signal φ _AC becomes high level. Therefore, when the column switch control signal φ _Y goes high, almost simultaneously φ _yij
Signal generation circuit φ _yij −SG is column switch selector
Sends signals to CSW-S ₁ and CSW-S ₂ .

In this way, the column switches C-SW ₁ , C
One pair out of a total of 512 transistor pairs in -SW ₂ is selected, and a pair of data lines DL in the memory array are connected to the common data line CDL.

[Two-pin D-RAMIC layout pattern] The so-called two-pin D-RAMIC layout pattern has a memory array divided into two parts within one IC chip.
The RAMIC layout pattern will be explained according to FIG.

First, two
The two memory arrays M-ARY ₁ and M-ARY ₂ are arranged spaced apart from each other in the IC chip.

A common column decoder C-DCR is arranged in the center of the IC chip between M-ARY ₁ and M-ARY ₂ .

Column switch C-SW ₁ for M-ARY ₁ is located between M-ARY ₁ and C-DCR.

On the other hand, column switch C- for M-ARY ₂
SW ₂ is placed between M-ARY ₂ and C-DCR.

The sense amplifiers SA ₁ and SA ₂ are affected by noise, such as C-
They are placed at the left and right ends of the IC chip to prevent malfunctions caused by signals applied to the DCR and to facilitate wiring layout.

On the upper left side of the IC chip, there is a data input buffer DIB, a read/write signal generation circuit, and an R/W-
SG, RAS signal generation circuit RAS-SG, and RAS system signal generation circuit _SG1 are arranged. Then, a signal application pad P- is placed close to these circuits.
RAS, signal application pad P-, and data signal application pad P- _Dio are arranged.

On the other hand, on the upper right side of the IC chip, a data output buffer DOB, a CAS signal generation circuit CAS-SG, and a CAS system signal generation circuit _SG2 are arranged. In close proximity to these circuits, a V _SS voltage supply pad P-V _SS signal application pad P-, a data signal take-out pad P-D _put , and an address signal are connected.
A ₆ supply pad P-A ₆ is located.

A main amplifier MA is arranged between the RAS signal generation circuit SG ₁ and the CAS signal generation circuit SG ₂ .

The V BB generation circuit V _{BB -G} is installed above circuits that occupy a large area such as the RAS signal generation circuit SG ₁ , the CAS signal generation circuit SG ₂ , or the main amplifier MA.
is located. This is because V _BB −G generates minority carriers, and M
There is a risk that the memory cells forming -ARY ₁ and M-ARY ₂ will undergo undesired information inversion. Therefore, to prevent this, the V _BB generation circuit V _BB −G
As mentioned above, is placed as far away from M-ARY ₁ and M-ARY ₂ as possible.

A row decoder R-DCR ₁ for M-ARY ₁ is arranged on the lower left side of the IC chip. and,
Address signal supply pads P-A ₀ , P-A ₁ , P-A ₂ and _Vcc voltage supply pad P-V _cc are arranged adjacent to R-DCR ₁ .

On the other hand, a row decoder R-DCR ₂ for M-ARY ₂ is arranged on the lower right side of the IC chip. Address signal application pads P- _{A 3 ,} P-A ₄ ,
P-A ₅ and P-A ₇ are arranged.

An address buffer ADB is arranged between R-DCR ₁ and R-DCR ₂ .

[Layout pattern diagram of power supply line]

A layout pattern diagram of a portion of a 64K-bit D-RAM centering on the memory array M-ARY and sense amplifiers SA ₁ and SA ₂ will be explained with reference to FIG. 7A. M-ARY and SA ₂ are formed in separate N-channel type well regions surrounded by dashed lines. In addition, column decoder C-DCR
Since M-ARY and SA ₂ etc. have a line-symmetrical layout with
ARY, SA ₁ , SA ₂ , etc. are omitted.

Since the N-channel well power supply voltage _Vcc is supplied, a power supply line Vcc _-L is formed as shown in FIG. 7A.

In FIG. 7A, assuming that M-ARY _1-1 is one row, power supply lines are formed for every 32 rows of M-ARY.

Since the well voltage becomes uneven as the distance between power supply lines increases,
- Just form it for each ARY line. Since the chip area becomes large, it is preferable to form them at equal intervals for each M-ARY, for example, every 8 rows, every 16 rows, every 32 rows, every 64 rows, etc.

In order to make the well voltage uniform, the power supply line is made of Al, Au, M, Mo,
It is made of metal such as Ta. When a power supply line made of the above-mentioned metal is formed in a well, it is preferably arranged in parallel with the data line made of Al so as not to be short-circuited to the data line.

The reason why the N-channel type well region is separated into the memory array M-ARY and the sense amplifier _SA2 is as follows.

A voltage drop occurs between the power supply line in the well region of the sense amplifier SA ₂ and the positive feedback operation control means (not shown) in the sense amplifier SA ₂ , and the voltage drop occurs in the sense amplifier SA ₂ farther from the power supply line. The voltage drop becomes large, and this voltage drop becomes noise. If the memory array M-ARY and sense amplifier SA ₂ are formed in the N-type well region, the well potential will decrease due to the voltage drop, and the P-MOS Q _M (not shown) of the memory cell will decrease. This lowers the threshold voltage V _TH . In this case, the P-MOS Q _M is likely to turn on, causing malfunction.

By independently forming the N-channel type well regions forming the memory array M-ARY and the sense amplifier SA ₂ , the sense amplifier
Prevent noise generated by SA ₂ from affecting memory operations.

Figure 7B shows the memory array M-ARY and sense amplifiers SA ₁ and SA ₂ in a 64K-bit D-RAM.
This figure shows some layout pattern diagrams centered on .

Parts corresponding to those in FIG. 7 are given the same reference numerals. 7th
The difference from FIG. A is that the memory array M-ARY and sense amplifier _SA2 are formed in the same well region.

In terms of chip area, there is an advantage that the chip area is smaller than that of the layout shown in FIG. 7A. just,
As explained above, there is a drawback that the noise generated in the sense amplifier SA ₂ tends to affect the memory operation.

[Memory cell element structure]

FIG. 8A is a perspective cross-sectional view showing the element structure of one memory cell M-CEL, in which 1 is a P-type semiconductor substrate, 2 is a relatively thick insulating film (hereinafter referred to as field insulating film), and 3 is a relatively thin insulating film. film (hereinafter referred to as gate insulating film), 4 and 5 are P ⁺ type semiconductor regions,
6 is a first polycrystalline silicon layer, 7 is a P-type surface inversion layer, 8 is a second polycrystalline silicon layer, 9 is a PSG (phosphorus silicate glass) layer, 10 is an aluminum layer, and 100 is an N-type well region. show.

MOS Q _M in one memory cell M-CEL is
The substrate, well region, drain region, source region, gate insulating film, and gate electrode are the above-mentioned P type semiconductor 1, N type well region 100, P ⁺ type semiconductor region 4, P ⁺ type semiconductor region 5, and gate insulating film 3. and second polycrystalline silicon layer 8, respectively. The second polycrystalline silicon layer 8 is used, for example, as the word line WL _1-2 shown in FIG. 4A. The aluminum layer 10 connected to the P ⁺ type semiconductor region 5 is, for example, a data line shown in FIG. 4A.
Used as DL _1-1 .

On the other hand, in the storage capacitor C _S in the memory cell M-CEL, one electrode, the dielectric layer, and the other electrode are connected to the first polycrystalline silicon layer 6 and the gate insulating film 3.
and P-type surface inversion layer 7, respectively. That is, since the ground voltage V _SS is applied to the first polycrystalline silicon layer 6, this ground voltage
V _SS induces a P-type surface inversion layer 7 on the surface of the N-type well region 100 due to the electric field effect via the gate insulating film 3 .

In addition. MOS Q _M in the above memory cell M-CEL
shows the case of P-channel type, but if all the above conductivity types are changed to different conductivity types, it becomes N-channel type.
MOS Q _M can be formed.

[Dummy cell element structure]

FIG. 8B is a perspective cross-sectional view showing the element structure of one dummy cell D-CEL. In Figure 8B,
In particular, 11, 12, 14 are P ⁺ type semiconductor regions, 1
7 and 18 are second polycrystalline silicon layers, and 19 is an aluminum layer.

MOS Q _D1 in one dummy cell D-CEL is
The substrate, well region, source region, drain region, gate insulating film and gate electrode are P type semiconductor substrate 1, N type well region 100, P ⁺ type semiconductor region 11, P ⁺ type semiconductor region 12, gate insulating film 3
and a second polycrystalline silicon layer 17, respectively. This second polycrystalline silicon layer 17 extends over the N-type well region 100 as, for example, a dummy word line DWL _1-2 shown in FIG. 4E. The aluminum layer 19 connected to the P ⁺ type semiconductor region extends on the P type semiconductor substrate 1 as, for example, a dummy data line DL _1-1 shown in FIG. 4E.

MOS Q _D2 in dummy cell D-CEL is its substrate,
The well region, source region, drain region, gate insulating film, and gate electrode are P-type semiconductor regions 1, N
type well region 100, P ⁺ type semiconductor region 12, P ⁺
The semiconductor region 14 is composed of a semiconductor region 14, a gate insulating film 3, and a second polycrystalline silicon layer 18, respectively. Then, the discharge signal φ _dc shown in the dummy cell D-CEL in FIG. 4E, for example, is applied to this polycrystalline silicon layer 18.

In addition, MOS Q _D1 in the above dummy cell D-CEL
and Q _D2 show the case of P channel type,
By changing all the above conductivity types to different conductivity types, N-channel type MOS Q _D1 and Q _D2 can be formed.

[Memory array layout pattern]

The layout pattern of memory array M-ARY will be explained with reference to FIG. 9A.

The memory array M-ARY shown in FIG. 9A is
A plurality of memory cells M-CEL shown in figure A are N
They are arranged in a mold well region 100.

First, the memory array M-ARY is configured as follows.

In order to isolate a plurality of memory cells M-CEL each consisting of a MOS Q _M and a storage capacitor C _S on the surface of the N-type well region 100, a field insulating film 2 is formed based on the pattern shown in FIG. 9B. It is formed.

A field insulating film 2a is exceptionally disposed below a contact hole CH ₀ for applying a ground voltage V _SS to the first polycrystalline silicon layer 6 . Therefore, the aluminum-silicon alloy formed based on the interaction between the aluminum layer and the polycrystalline silicon layer near this contact hole CH ₀ penetrates the insulating film directly under the contact hole CH ₀ and forms the N-type well region 100. Accidents of reaching surfaces undesirably can be prevented.

This field insulating film 2 and gate insulating film 3
A first polycrystalline silicon layer 6 used as one electrode of the storage capacitor C _S in the memory cell M-CEL is formed thereon based on the pattern shown in FIG. 9C.

Further, on the first polycrystalline silicon layer 6, a ninth
The word line formed by the second polycrystalline silicon layer 8 in FIG. 8A along the vertical direction of the figure.
WL _1-1 to WL _1-6 extend.

Furthermore, a power supply line V _SS-L for supplying the ground voltage V _SS to the polycrystalline silicon layer 6 as one electrode of the storage capacitor _CS through the contact hole CH ₀ is provided as shown in FIG. 9A. Extends laterally.

On the other hand, the data lines DL _1-1 , _1-1 formed by the aluminum layer 10 in FIG.
As shown in FIG. 9A, it extends substantially parallel to the power supply line V _SS-L . Data line DL _1-1 is connected to memory cell M-CEL through contact hole CH ₁ .
Connected to the source region of MOS Q _M , data line
_1-1 is connected to the source region of MOS _QM in another memory cell M-CEL via a contact hole _CH2 . Further, the data lines DL _1-2 , _1-2 extend in the horizontal direction of FIG. 9A similarly to the data lines DL _1-1 , _1-1 , and are connected to the memory cell M-CEL through contact holes at predetermined portions. is connected to the source region of MOS Q _M.

In order to bias the N-type well region 100 to the power supply voltage V _CC , a power supply line V _CC-L extends in the lateral direction of FIG. 9A at the end of the memory array M-ARY substantially parallel to the data line.

[Memory array and dummy array layout pattern]

Memory array M-ARY and dummy array D
-ARY layout pattern is shown in FIG. 9D.
Portions corresponding to those in FIG. 9A are given the same reference numerals. 9th
The difference from diagram A is that dummy array D-
The point is that ARY was added.

The dummy cell D-CEL shown in FIG. 9D is configured as follows.

A field insulating film 2 is formed on a part of the surface of the N-type well region 100.
A gate insulating film 3 is formed on the other part of the surface of 0.

The P ⁺ type semiconductor region 14 has a plurality of dummy cells D−
Used as a common ground line for CEL.

A dummy word line DWL _1-1 formed by the second polycrystalline silicon layer 17 in FIG. 8B extends over the field insulating film 2.

Dummy word line DWL _1-1 is dummy cell D-CEL
It forms the gate electrode of MOS Q _D1 inside. On the other hand, in order to apply the discharge control signal φ _dc shown in FIG. 4E, the control signal line φ _dc-L1 formed by the second polycrystalline silicon layer 18 in FIG. 8B is connected to the dummy word line DWL. It is separated from _1-1 and extends parallel to it. The control signal line φ _dc-L1 constitutes the gate electrode of MOS Q _D1 in the dummy cell D-CEL. Similarly, dummy word line
Dummy word line DWL _1-2 and control signal line φ _dc-L2 extend in parallel with DWL _1-1 and control signal line φ _dc-L1 .

And data lines DL _1-1 , _1-1 , DL _1-2 ,
_1-2 is the memory array M- as shown in FIG. 9D.
Extends from ARY. _1-1 is the MOS in the dummy cell D-CEL via the contact hole CH ₂
It is connected to the source region of Q _D1 , and _1-2 is also connected to other D-CEL through contact hole _CH4 .
Connected to the source region of MOS Q _D1 .

[C-MOS dynamic RAM manufacturing process]

The manufacturing process of a complementary type (hereinafter referred to as C-MOS) dynamic RAM having an N-MOS and a P-MOS will be described with reference to FIGS. 10A to 10W. In each figure, _X1 is a process cross-sectional view of the _X1 - _X1 section of the memory array M-ARY shown in FIG. 9A, and _X2 is the sense amplifier shown in FIG. 4A.
FIG. 3 is a process cross-sectional view of the CMOS circuit portion of SA.

(Oxide film forming step) As shown in FIG. 10A, an oxide film 102 is formed on the surface of the semiconductor substrate 101. Semiconductor substrate 101
As preferred specific materials for the oxide film 102, a P-type single crystal silicon (Si) substrate having a (100) crystal plane and a silicon dioxide (SiO ₂ ) film are used, respectively.

(Selective Oxide Film Removal Step) As shown in FIG. 10B, in order to form a well region of a conductivity type different from that of the semiconductor substrate, the SiO ₂ film 102 is removed on the semiconductor substrate 101 in the well formation region. To do this, first, a silicon nitride (Si ₃ N ₄ ) film 103 is selectively formed on the surface of the SiO ₂ film as an etching mask. In this state, the SiO ₂ film that is not covered by the Si ₃ N ₄ film 103 is removed using an etchant.

(Selective Substrate Removal Step) As shown in FIG. 10C, in order to form a well region of a conductivity type different from that of the semiconductor substrate in the semiconductor substrate 101, the semiconductor substrate is etched using the Si ² N ₄ film 103 as an etching mask. The substrate 101 is etched to a desired depth by wet etching or dry etching.

(N-type well region forming step) As shown in FIG. 10D, Si single crystal is grown epitaxially in the etched region in the semiconductor substrate 101. Also dope with arsenic at the same time.

In this way, an N-type well region with an impurity concentration of about 10 ¹⁵ cm ^-3 is formed on the semiconductor substrate 101. After that, the SiO ₂ film 10 on the semiconductor substrate 101 is
2 and remove the Si ₃ N ₄ film.

Forming an N-type well region has the following advantages.

(1) In order to prevent stored information from being inverted due to alpha rays being absorbed by the capacitor C _S of the memory cell, if the memory cell is configured within an N-type well region, the The holes generated are reflected by the barrier at the PN junction, eliminating the effect of the holes on the capacitor C _S.

Furthermore, by forming the well region epitaxially, the following advantages can be obtained compared to forming it by diffusion.

(1) Since the concentration in the well can be easily controlled, the concentration can be made uniform.

(2) The junction capacitance on the well surface can be reduced, increasing the speed of memory operation.

(3) Since the concentration on the well surface can be lowered, the withstand voltage can be increased.

(4) Threshold voltage can be easily controlled.

(5) The depth of the well can be adjusted with high precision.

Next, the process of forming an N-type well region by another method will be explained with reference to FIGS. 10X to 10Z.

In FIG. 10X, a Si single crystal is epitaxially grown while doping the entire surface of a semiconductor substrate 101 with arsenic. The impurity concentration of arsenic is 10 ¹⁵ cm ^-3 . In this way, an N-type well region with a depth of 3 μm is formed on the semiconductor substrate 101.

In FIG. 10Y, a SiO ₂ film 102 and a photoresist film 104 are formed on the N-type well formation region to form a desired N-type well region. Thereafter, using the SiO ₂ film and the photoresist film 104 as a mask, boron having an impurity concentration of 2×10 ¹⁵ cm ^-3 is ion-implanted onto the surface of the N-type well, and thermal diffusion is performed to diffuse the boron into the semiconductor substrate 101. The same P-type region is formed.

In FIG. 10Z, the SiO ₂ film 102 and photoresist film 104 are removed, and a desired N-type well region is formed in the semiconductor substrate 101.

Note that the method for forming the N-type well region is not limited to the above two types of methods, and other methods may of course be used. Of course, the well region may also be formed by diffusion.

(Step of forming oxide film and oxidation-resistant film) As shown in FIG. 10E, a SiO ₂ film 102 and an oxygen-impermeable insulating film, that is, an oxidation-resistant film 103, are formed on the surfaces of the semiconductor substrate 101 and the N-type well 100.

A silicon nitride (Si ₃ N ₄ ) film is used as a preferred specific material for the oxidation-resistant film 103 .

The SiO ₂ film 102 is attached to the Si substrate 10 for the following reasons.
It is formed to a thickness of about 500 Å by surface oxidation of 1. That is, the Si ₃ N ₄ film 103 is directly attached to the Si substrate 10.
When formed on the surface of Si substrate 101 and Si ₃ N ₄
Due to the difference in thermal expansion coefficient with the film 103, the Si substrate 1
Apply thermal strain to the surface of 01. For this reason, Si substrate 1
Give crystal defects to the surface of 01. To prevent this, the SiO ₂ film 102 is formed before the Si ₃ N ₄ film 103 is formed.
It is formed on the surface of the Si substrate 101. On the other hand, Si ₃ N ₄
The film 103 is formed on the Si substrate 101 as will be described in detail later.
For use as a mask for selective oxidation, it is formed to a thickness of about 1400 Å by, for example, CVD (Chemical Vapor Deposition).

(Selective removal of oxidation-resistant film and ion implantation process) Si ₃ N ₄ film 10 on the surface of the Si substrate 101 on which a relatively thick insulating film, that is, a field insulating film is to be formed.
In order to selectively remove the Si ₃ N ₄ film 10, the photoresist film 104 is first used as an etching mask.
selectively formed on the surface of 3. In this state, exposed portions of the Si ₃ N ₄ film 103 are removed by, for example, plasma etching, which allows for highly accurate etching.

Next, in order to prevent a layer of the opposite conductivity type from that of the substrate, so-called inversion layer, from being formed on the surface of the Si substrate 101 where the field insulating film is formed.
As shown in FIG. 10F, impurities of the same conductivity type as the substrate, that is, P-type impurities, are introduced into the Si substrate 101 through the exposed SiO ₂ film 102 with the photoresist film 104 remaining. Ion implantation is preferred as a method for introducing this P-type impurity. For example, boron ions, which are P-type impurities, are implanted into the Si substrate 101 with implantation energy of 75 keV. The ion dose at this time was 3×10 ¹² atoms/cm ² .

(Field insulating film forming process) A field insulating film 105 is formed on the surface of the Si substrate 101.
selectively formed. That is, after removing the photoresist film 104 as shown in FIG. 10G,
Using the Si ₃ N ₄ film 103 as a mask, the surface of the Si substrate 101 is selectively oxidized by thermal oxidation to a thickness of approximately 9500 mm.
A SiO ₂ film 105 (hereinafter referred to as a field SiO ₂ film) with a thickness of 100 Å is formed. This field SiO ₂ film 1
During the formation of 05, the ion-implanted boron is Si
A P-type anti-inversion layer (not shown) is stretched and diffused into the substrate 101 and has a predetermined depth.
It is formed directly under the SiO ₂ film 105.

(Oxidation-resistant film and oxide film removal process) In order to expose the surface of the Si substrate 101 where the field SiO ₂ film 105 is not formed,
The Si ₃ N ₄ film 103 is removed using, for example, hot phosphoric acid (H ₂ PO ₄ ) solution. Subsequently, the SiO ₂ film 102 is removed using, for example, a hydrofluoric acid (HF) solution, and
As shown in the figure, the surface of the Si substrate 101 is selectively exposed.

(First gate insulating film forming step) A first gate insulating film 106 is formed on the exposed surfaces of the Si substrate 101 and the N-type well 100 to obtain the dielectric layer of the capacitor C _S in the memory cell M-CEL. Form as shown. That is, by thermally oxidizing the exposed surfaces of the Si substrate 101 and the N-type well, a first gate insulating film 106 having a thickness of about 430 Å is formed on the surfaces. Therefore, the first
The gate insulating film 106 is made of SiO ₂ .

(First conductor layer adhesion step) The first conductor layer 107 is attached to the Si substrate 10 to be used as one electrode of the capacitor C _S in the memory cell.
1 as shown in FIG. 10J. That is, as the first conductor layer 107, for example, a polycrystalline silicon layer is formed over the entire surface of the Si substrate 101 by CVD. The thickness of this polycrystalline silicon layer is approximately 4000
It is about Å. Subsequently, polycrystalline silicon layer 10
In order to reduce the resistance value of the polycrystalline silicon layer 107, an N-type impurity such as phosphorus is introduced into the polycrystalline silicon layer 107 by a diffusion method. As a result, the resistance value of the polycrystalline silicon layer 107 is approximately 16Ω/hole.

(Selective removal step of first conductor layer) First conductor layer, that is, first polycrystalline silicon layer 10
In order to form electrode 7 into a predetermined shape, first polycrystalline silicon layer 107 is selectively removed by photoetching as shown in FIG. 10K, and electrode 108 is formed. As a method for selectively removing the first polycrystalline silicon layer 107, plasma etching is suitable because it allows for highly accurate etching. Subsequently, the exposed first gate SiO ₂ film 106 is also etched to partially expose the surface of the N-type well 100.

(Second gate insulating film formation process) Memory array M-CEL, dummy array D-
A second gate insulating film 109 is first deposited on the exposed surfaces of the Si substrate 101 and the N-type well 100 to obtain gate insulating films for the MOS in the CEL and peripheral circuit sections.
Form as shown in the 0L diagram. That is, by thermally oxidizing the exposed surfaces of the Si substrate 101 and the N-type well 100, a second gate insulating film 109 having a thickness of about 530 Å is formed on the surfaces. Therefore, the second gate insulating film 109 is made of SiO ₂ .
Second gate insulating film, that is, second gate SiO ₂ film 1
At the same time as the formation of electrode 09, the surface of electrode 108 made of first polycrystalline silicon is also oxidized, and a thickness of approximately
A SiO ₂ film 110 of 2200 Å is formed. This _SiO2
The film 110 serves as interlayer insulation between the electrode 108 and a second electrode made of polycrystalline silicon, which will be described later.

(Threshold voltage control ion implantation step) As shown in FIG. -P-type impurities are introduced into the surface of the Si substrate 101 on which the MOS is to be formed by ion implantation. For example, boron is used as the P-type impurity. The implantation energy is 30keV and the ion dose is
4.5×10 ¹¹ atoms/cm ² is preferred.

(Second conductor layer deposition process) The second conductor layer 113 is attached to the Si substrate 10 to be used as the gate electrode and wiring layer of all MOS.
1. Form on the entire surface. That is, as shown in FIG. 10N, a polycrystalline silicon layer, for example, is formed as the second conductor layer 113 over the entire surface of the Si substrate 101 by the CVD method. The thickness of this polycrystalline silicon layer 113 is approximately 3500 Å. Subsequently, in order to reduce the resistance value, an N-type impurity such as phosphorus is introduced into this polycrystalline silicon layer 113 by a diffusion method. As a result, the resistance value of the polycrystalline silicon layer 113 is approximately
10Ω/mouth.

(Selective removal process of second conductor layer) Second conductor layer, that is, second polycrystalline silicon layer 11
3 is selectively removed by photoetching in order to form a predetermined electrode or wiring shape. In other words, as shown in FIG. 100, the silicon layer 113 after photoetching forms the word line shown in FIG. 9D.
WL _1-1 ~ WL _1-6 , dummy word line DWL _1-1 ,
DWL _1-2 , control signal lines φ _dc-L1 and φ _dc-L2 are formed.
Further, the exposed second gate SiO ₂ film 109 is removed to expose the surfaces of the Si substrate 101 and the N-type well 100.

(Surface oxidation process) In order to avoid contamination of the surface where the source and drain regions of the MOS are to be formed, the first
As shown in the 0P diagram, the exposed Si substrate 101 and N
A SiO ₂ film 115 with a thickness of 100 Å is formed on the surface of the mold well 100 by thermal oxidation of the surface. At the same time as the SiO ₂ film 115 is formed, word lines WL _1-1 to WL _1-6 and dummy word lines made of second polycrystalline silicon are formed.
DWL _1-1 , DWL _1-2 , control signal line φ _dc-L1 , φ _dc-L2 ,
The surfaces of the complementary MOS gate electrodes are also oxidized, resulting in a SiO ₂ film 11 approximately 300 Å thick on their surfaces.
6 is formed as shown in FIG. 10P.

(Source/drain region formation process) First, the source/drain regions of the N-MOS are formed using Si.
The 10th Q is selectively formed in the substrate 101.
As shown in the figure, an ion implantation mask, for example, a CVDSiO ₂ film 119, is formed on the N-type well 100.
An N-type impurity, for example, arsenic, is introduced into the Si substrate 101 through the SiO ₂ film 115 in a region where the CVDSiO ₂ film 119 is not present. Ion implantation is preferred as a method for introducing this N-type impurity. For example, arsenic ions are implanted into the Si substrate 101 with an implant energy of 80 keV. The ion dose at this time was 1×10 ¹⁶ atoms/cm ² . Subsequently, heat treatment is performed, and the implanted arsenic impurities are stretched and diffused into N ⁺ type semiconductor regions 120 and 12 having a predetermined depth.
1 is formed. These N ⁺ type semiconductor regions 120,
121 is a source/drain region.

Next, in order to selectively form P-MOS source/drain regions in the N-type well 100,
As shown in Figure R, an ion implantation mask, for example, is placed on the Si substrate 101 other than on the N-type well 100.
A CVDSiO ₂ film 119 is formed and the N-type well 10
A P-type impurity, for example, boron, is introduced into the N-type well through the SiO ₂ film 115 on the SiO 2 film 115 by ion implantation. For example, boron ions are implanted with energy
It is implanted into the N-type well at 80keV. The ion dose at this time was 3×10 ¹⁵ atoms/cm ² .

Subsequently, heat treatment is performed, and the ion-implanted boron impurity is stretched and diffused, forming P ⁺ -type semiconductor regions 122 to 127 having a predetermined depth.

These P ⁺ type semiconductor regions 122 to 127 become source and drain regions.

Note that the source and drain of P-MOS are N type.
The reason why it is formed after the source and drain of the MISFET is to perform the above heat treatment process only once to prevent boron from diffusing more than necessary.

(Contact hole formation step (1)) First conductor layer, that is, first polycrystalline silicon layer 10
A contact hole for connecting 8 and a third conductor layer to be described later is formed in the SiO ₂ film 110. That is,
Contact hole CH ₁₀₁ as shown in Figure 10S
using a photoresist film (not shown) as a mask.
It is selectively formed in the SiO ₂ film 110. Note that this contact hole CH ₁₀₁ corresponds to the contact hole CH ₀ shown in FIG. 9A.

The reason why only the contact hole CH ₁₀₁ for connecting the first polycrystalline silicon layer 108 and the third conductor layer is formed is as follows. That is, as described above, the thickness of the SiO ₂ film 110 formed on the surface of the first polycrystalline silicon layer 108 is 300 Å. On the other hand, Si
The thickness of the SiO ₂ film 115 formed on the surfaces of the substrate 101 and the N-type well 100 is 100 Å. Therefore,
If these SiO ₂ films 110 and 115 are etched at the same time, there is a risk that the SiO ₂ film 115 will be overetched before the first polycrystalline silicon film 108 is completely exposed.

In order to prevent this, the contact hole CH ₁₀₁ is formed independently as described above.

(Contact hole forming step (2)) Contact holes for connecting the source/drain regions and the third conductor layer are formed in the SiO ₂ film 115.
That is, using a predetermined mask, the SiO ₂ film 115 is
By selective etching, contact holes CH ₁₀₂ to _{CH 107} are formed as shown in FIG. 10T.

Although the above mask also has an opening in a portion corresponding to the contact hole CH ₁₀₁ , overetching of the SiO ₂ film 110 in the contact hole CH ₁₀₁ does not actually pose a problem.

Note that contact hole CH ₁₀₂ corresponds to contact hole CH ₁ in FIG. 9A.

(Interlayer insulating film forming step) An interlayer insulating film is formed on the entire surface of the Si substrate 101.
That is, as shown in FIG. 10U, the interlayer insulating film 1
18. For example, phosphorus silicate with a thickness of about 8000 Å
A glass (PSG) film is formed on the entire surface of the Si substrate 101. This PSG film 118 also serves as a getter for sodium ions that affect the characteristics of the MOS.

(Contact hole formation step (3)) Contact holes are formed in the PSG film 118 to connect between the second polycrystalline silicon layer and the third conductor layer and between the source/drain region and the third conductor layer. .

That is, as shown in FIG. 10V, the PSG film 1
18 is selectively etched and the contact hole is
Forms CH ₁₀₁ to _{CH 107} . The mask used to form the contact holes CH ₁₀₁ to _{CH 107} is the same as the mask used to form the contact holes CH ₁₀₁ to _{CH 107} in the contact hole forming step (2). . Continuing,
In order to planarize the PSG film 118, the PSG film 118 is heat-treated at a temperature of about 1000°C.

By the way, the formation of contact holes in the SiO ₂ film 115 described in the above contact hole formation step (2) can be accomplished simultaneously with the formation of contact holes in the PSG film 118. However, while the contact hole for the SiO ₂ film 115 is being completed, the PSG film 118 is also etched. That is, overetching of the PSG film 118 occurs. Therefore, in order to prevent this overetching, the PSG film 118 is
contact hole formation and SiO ₂ film 115
It is preferable to form contact holes for the two separately.

(Third conductor layer formation process) Power supply line V _SS-L and data line shown in Figure 9A
In order to form DL _1-1 , _1-1 , DL _1-2 , _1-2, first, a third conductor layer, for example, an aluminum layer with a thickness of 12000 Å, is formed over the entire surface of the Si substrate 101 .
Next, this aluminum layer is selectively etched, and the power supply lines V _SS-L ,
A data line DL _1-1 and a wiring layer 127 are formed.

[Brief explanation of drawings]

Figure 1 is a dynamic memory system diagram, Figure 2 is a diagram of the dynamic memory system.
The figure is a D-RAM block diagram, FIG. 3 is a timing diagram of D-RAM, FIG. 4A is a D-RAM block diagram of an embodiment of the present invention, and FIG. 4B is a D-RAM block diagram of an embodiment of the present invention.
FIG. 4C is a D-RAM block diagram of another embodiment of the present invention; FIG. 4D is a D-RAM timing diagram of another embodiment of the present invention; FIG. 4E is a D-RAM timing diagram of another embodiment of the present invention; Figure 5A is a circuit configuration diagram of a 2-mat type 64KD-RAM, Figure 5B is a timing diagram of a 2-mat type 64KD-RAM, and Figure 6 is a 2-mat type 64KD-RAM block diagram.
RAMIC layout pattern diagram, Figure 7A, Figure 7
Figure B is a partial diagram of the 2-mat D-RAMIC layout pattern, Figure 8A is a diagram of the element structure of a memory cell, Figure 8B is a diagram of the element structure of a dummy cell, and Figure 9A is a diagram of the element structure of a dummy cell.
The figure is a memory array layout pattern diagram, No. 9.
Figure B is a pattern diagram of the field insulating film, Figure 9C is a diagram of the electrode pattern of the storage capacitor C S, and Figure 9D is a diagram of the electrode pattern of the memory capacitor C _S.
The figure is a layout pattern diagram of a memory array and a dummy array, and Figures 10A to 10Z are C-
It is a manufacturing process diagram of MOS dynamic RAM. SA ₁ , SA ₂ ...Sense amplifier, PC...Precharge circuit, CDL,...Common data line, M-CEL
...Memory cell, D-CEL...Dummy cell, MA...Main amplifier, MS...Memory activation signal, nk...NK bit integrated circuit, X ₁ ...Memory array forming section, X ₂ ...
CMOS forming part, CH...contact hole, V _CC-L
…well power supply line, V _SS-L …ground voltage supply line, DL, …data line, WL…word line,
REFGRNT…Refresh instruction signal, REFREQ
...Refresh request signal, ...Write enable signal, CS ₁ to CS _n ...Chip selection control signal, 10
0... N-type well region, 2,105... Field insulating film, 3... Gate insulating film, 6... First polycrystalline silicon layer, 7... P-type surface inversion layer, 8, 17, 18, 1
14...Second polycrystalline silicon layer, 9,118...
PSG layer, 10, 19, 127...aluminum layer,
4, 5, 11, 12, 14...P ⁺ type semiconductor region,
116...SiO ₂ film.

Claims (1)

[Scope of Claims] 1. A memory array having a plurality of data lines, a plurality of word lines and a plurality of memory cells each intersecting both of the data line pairs, and A semiconductor memory comprising a differential amplifier that performs positive feedback operation to amplify a difference, a control means for controlling the operation of the differential amplifier, and a precharge circuit, wherein the differential amplifier includes a first Consisting of a differential amplifier and a second differential amplifier, the first differential amplifier is composed of a first P channel FET and a second P channel FET, and the gate of the first P channel FET is connected to the drain of the second P channel FET. is,
And the gate of the second P channel FET is the same as the gate of the second P channel FET.
The second differential amplifier is configured to be connected to the drain of the 1P channel FET, and the sources of the first and second P channel FETs are commonly connected. The gate of the first N-channel FET is connected to the drain of the second N-channel FET, and the gate of the second N-channel FET is connected to the drain of the first N-channel FET, and the sources of the first and second N-channel FETs are common. The above 1st P channel shall be configured to be connected.
The drain of the FET and the drain of the first N-channel FET are coupled to one of the pair of data lines, and the drain of the second P-channel FET and the drain of the second N-channel FET are coupled to one of the pair of data lines.
The drain of the channel FET is coupled to the other of the pair of data lines, and the precharge circuit connects each pair of data lines to an intermediate potential of the binary information stored in the memory cell before the positive feedback operation is started. The control means is configured to control a first power source to which a first power supply voltage is supplied.
a first control means provided between a power supply terminal and the sources of the first and second P-channel FETs; a second power supply terminal to which a second power supply voltage lower than the first power supply voltage is supplied; and the first, a second control means provided between the source of the second N-channel FET, and a first operation timing signal supplied to the first control means and a second operation timing signal supplied to the second control means.
an operation timing signal, wherein the first operation timing signal and the second operation timing signal are supplied at different timings. 2. The semiconductor memory according to claim 1, wherein the second operation timing signal is supplied earlier than the first operation timing signal. 3. The semiconductor memory according to claim 1, wherein the first operation timing signal is supplied earlier than the second operation timing signal.