JPH0456348A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To build both circuits into a single semiconductor device by respectively locating a first circuit in a first semiconductor region and a second circuit in a third semiconductor region and operating both circuits under the condition that the reference voltage of external circuit is given to the first semiconductor region and non-reference voltage to the external circuit of the second and third semiconductor region. CONSTITUTION:A second semiconductor region 2 and a third semiconductor region 3 having different conductivity types are connected in the same potential by short- circuiting at the surfaces thereof with an electrode film for terminal Te and allows application of the non-reference voltage Vo. In the side of the first circuit C1, the reference voltage E is applied to the first semiconductor region l through the electrode film for terminal Te. Thereby, since a voltage difference between the reference voltage E and non-reference voltage Vo is applied in the backward bias direction to the pn junction between the first semiconductor region 1 and the second semiconductor region 2 having different conductivity types, the potential Vo of the third semiconductor region 3 is floated from the potential E of the first semiconductor region l and thereby the first circuit C1 in the first semiconductor region l and the second circuit C2 in the third semiconductor region 3 can operate independently without any interference under the different potentials Eo and Vo.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device in which a plurality of circuit sections that operate on mutually different potentials of an external circuit are incorporated into the same chip.

[Conventional technology]

As is well known, most semiconductor integrated circuit devices normally operate under a power supply voltage of several volts, or at most several tens of volts, and when used by connecting them to an external circuit, the external circuit may be used for power, for example. If the operating voltage of the circuit is higher than the operating voltage of the integrated circuit, there may be restrictions on the manner of connection.

This example will be explained with reference to FIG. 5 and subsequent figures.

FIG. 5 shows an example in which a three-phase inverter 30 drives a power load such as a motor 40. 3
1 is connected in a three-phase bridge as usual, and receives a DC voltage of several hundred volts between a pair of power supply potential points ■ and 8, and converts it into three output voltages Vo that drive the motor 40. Output. In order to open and close these six transistors 31 in a predetermined order and at a predetermined timing, a base drive circuit C, the main part of which is illustrated in FIG. 6, is connected to their bases.

The base drive circuit C shown in FIG. 6 consists of an output section 5C and an operation section 60 for the output section 5C. The output section 50 has two transistors 51 connected in a push-pull manner between a pair of electric terminals Tv and Te that receive a voltage of about several volts, and the operating section 60 controls the bases of these transistors 51, respectively. transistors 62 along with each resistor 63 at both power supply terminals T
It is connected between ν and Te, and these transistors 62 are alternately opened and closed by the control command C3 and its complementary signal via two inverters 61. As a result, an output terminal TO is led out from the interconnection point of the two transistors 51 in the output section 50, which are alternately opened and closed, and connected to the bases of the transistors 31 corresponding to each base drive circuit C in FIG. be done.

Now, in the example of the inverter 30 shown in FIG. 1, the six transistors 31 are of the npn type, so for the three transistors in the lower row, the corresponding three base drive circuits C are connected to one transistor. It is sufficient to fabricate it in the integrated circuit device 11 and apply a potential E on the ground side to the substrate in this example.

However, for the three transistors 31 arranged in the upper row, output voltages Vo that vary independently of each other are applied to their emitters, so the base drive circuits C to be connected to them are separated from each other as shown in the figure. It is necessary to separate the integrated circuit devices 12 into individual integrated circuit devices 12 and apply the potential of each output voltage Vo to each of the substrates.

FIG. 7 shows the sixth integrated circuit device 11 and 12 for reference.
This figure shows the conventional and ordinary structure of the part incorporating the output section 50 of the space drive circuit C shown in the figure.

For example, an n-type substrate l is used as shown in the figure, and for the two transistors 51, in this example, a P-type buried layer 4p for junction isolation and an n-type buried layer 4p for the collector are formed on the surface of the substrate l for the two transistors 51.
An n-type epitaxial layer 5 is grown after a buried layer 4n of a shape is diffused in advance, and an n-type junction isolation layer 6 is deeply buried so as to surround the area in which each transistor is to be formed from the surface of the epitaxial layer 5. By diffusing until reaching the layer 4p, the epitaxial layer 5 is junction-separated as a collector g region for each transistor 51.

In this example, each npn-type transistor 51 has an n-type collector connection layer 7, a p-type base layer 8, and an n-type emitter layer 9 diffused into the n-type collector region to reach the buried layer 4n. These transistors 51 are interconnected as shown in the figure and connected to a pair of power supply terminals Tν.
, Te and the output terminal To are derived. Note that the two base terminals Tb for control are connected to the operating section 60 shown in FIG.

In order to operate such an integrated circuit device normally, it is necessary to connect one of the terminals a! Since it is necessary to place the terminal Te at the same potential as the substrate l, three base drive circuits C are built into the integrated circuit device 11 of FIG.
In this example, it is sufficient to apply the ground potential E, which is a constant reference potential to It becomes necessary to operate with each output voltage Vo, which constantly fluctuates over time, individually applied to the power supply terminal Te, which has the same potential as the substrate 1, that is, on each independent potential.

[Problem to be solved by the invention]

When incorporating multiple circuits, such as the upper base drive circuit, into an integrated circuit device and connecting them to external circuits,
If the operating potential of each circuit, that is, the potential of the integrated circuit device's substrate, differs, it is necessary to separate the integrated circuit device into circuits with different operating potentials, which increases the effort and cost of manufacturing and packaging each integrated circuit device. However, it also requires extra space and effort to implement.

To solve this problem, for example, 3 in the upper row of Figure 1
If the transistors 31 are of the pnp type, the base drive circuits C of the three integrated circuit devices 12 can be incorporated into one integrated circuit device, but it is necessary to apply the potential of the power supply voltage to the substrate. , and must be separated separately from the integrated circuit device 11.

An object of the present invention is to solve the rJ1 problem and to integrate a plurality of circuit sections that are to operate on mutually different potentials in an external circuit.
The objective is to enable it to be incorporated into individual integrated circuit devices.

[Means for resolving divisions and companies]

According to the present invention, this purpose is to combine the first circuit section to be connected to the reference potential side of the G external circuit as described above and the second circuit section to be connected to the non-reference potential side into a single integrated circuit device. a first semiconductor region of one conductivity type, a second semiconductor region of the other conductivity type built into the first semiconductor region, and one conductivity type built into the second semiconductor region. the third
a semiconductor region, and a first circuit portion within the first semiconductor region.

The second circuit sections are built in the third semiconductor regions, and the reference potential of the external circuit is provided in the first semiconductor regions.

This is achieved by operating both turning sections while applying non-reference potentials from an external circuit to the second and third semiconductor regions, respectively.

Note that the first semiconductor region is formed of a substrate of an integrated circuit device or the like. Both the first and second circuit sections usually consist of a plurality of circuits, of course the first circuit section operates on the reference potential side of the external circuit, but the second circuit section operates on the reference potential side of the external circuit, while the second circuit section has a non-standard circuit that can change independently. The number of electrodes corresponding to the number of potentials is provided.

[Effect]

Hereinafter, the effect of the configuration of the present invention described in the previous section will be explained with reference to the principle diagram shown in FIG. However, in order to simplify the diagram, both the first circuit section C1 and the second circuit section C2 are represented by a single transistor, and it is assumed that the first semiconductor region 61, which is the substrate of the integrated circuit device, is of P type. It is assumed that the illustrated circuit sections CI and 02 are connected, for example, to the inverter 30 of FIG. 2, which is the same as that of FIG. 5 described above.

In the present invention, within the first semiconductor region 1 of one conductivity type which is P type, there is a second semiconductor region 2 of N type which is the other conductivity type, and within the first semiconductor region 1 which is of one conductivity type which is P type. The third semiconductor regions 3 of FIG. The two circuit parts C1 and 02 in Figure 0, which respectively form the second circuit part C2 that operates under a non-reference potential that is the output voltage Vo, have an n-type collector region 5, a p-type base layer 8, and an n-type collector region 5. n with emitter layer 9
pn) is a transistor.

Next, in order to operate the second circuit section C2 under a potential independent from the first circuit section CI, in the present invention, a second circuit section C2 having a different conductivity type is operated.
The semiconductor region 2 and the third semiconductor subregion 3 are connected to the same potential by, for example, short-circuiting their surfaces with an electrode film for the terminal Te as shown in the figure, thereby providing a non-reference potential Vo. Of course, on the side of the first circuit section C1, the reference potential E is applied to the first semiconductor region 1 in which the first circuit section C1 is formed via the electrode film for the terminal Te, as usual. As a result, the potential difference between the reference potential E and the non-reference potential vO is applied in the reverse bias direction to the pn junction between the first semiconductor region 1 and the second semiconductor region 2 having different conductivity types, so that the potential of the third semiconductor region 3 ν
0 floats from the potential E of the first semiconductor region 1, and the first circuit portion C1 in the first semiconductor region 1 and the second circuit portion C2 in the third semiconductor head region 3 are under different potentials E and Vo. They can now operate completely independently of each other without mutual interference.

Therefore, in the present invention, the first circuit section C1 and the second circuit section C2 can all be incorporated into a single integrated circuit device IO as shown in FIG.

Note that the reference potential E is commonly applied to the first semiconductor region 1 for the first circuit section C1 in this integrated circuit device 10 as shown in the figure, and the reference potential E is commonly applied to each third semiconductor region 3 for the second circuit section C2. are individually given non-reference potentials vO that can vary independently of each other as shown in the figure.

〔Example〕

The present invention will be described in detail below with reference to FIGS. 3 and 4. Similar to FIG. 7 described above, these diagrams show a cross section of a portion of FIG. 6 in which the output section 50 is incorporated, and corresponding parts to those in FIG. 7 are given the same reference numerals. In both embodiments, it is assumed that integrated circuits are fabricated within a wafer on which an epitaxial layer is grown on a substrate.

In the example of FIG. 1, two transistors 51 are formed for each of the first circuit section C1 and the second circuit section C2. The substrate 1 of the integrated circuit device in this embodiment is of P type, and an N type second semiconductor region 2 is formed on the surface of the substrate 1, which is used as the first semiconductor region according to the present invention, within the area where the second circuit portion C2 is to be formed. is diffused into a dish shape, and then a P-type third semiconductor region 3 is diffused therein into a dish shape.

Further, a P-type buried layer 4p for junction isolation of the transistor 51 and an n-type buried layer 4n for the collector are both diffused with high impurity concentration in a predetermined range on the surface, and then
Next, grow an epitaxial layer 5 of the shape on the entire surface of the wafer.
The shaped junction isolation layer 6 is deeply diffused in a pattern surrounding the area where each transistor 51 is to be formed until it reaches the P-type buried layer 4p.

As a result, in the first semiconductor region 1 and the third semiconductor region 3, the n-type epitaxial layer 5 divided by the junction separation layer 6 is used as a collector region for the npn transistor 51 for the first circuit section CI and the second circuit section C2. The second semiconductor region 2 is surrounded from the inside and outside by the junction isolation layer 6 of the n-type epitaxial layer 5, and the annular portion continuous therewith is used as an extension of the second semiconductor region 2.

Each transistor 51 is formed by diffusing an n-type collector connection layer 7, an n-type base layer 8, and an n-type emitter layer 9 that reach the buried layer 4n in each n-type collector region of the epitaxial layer 5. It will be done.

In both circuit sections CI and C2, the two transistors 51 are connected in series as shown in the figure, and connected to power supply terminals Tν and T.
6 and an output terminal TO are derived, and a pair of base terminals Tb
is connected to other circuits within the integrated circuit device.

On the first circuit section C1 side, the power supply terminal Te is connected to the substrate 1, which is the first semiconductor region, via an electrode film in contact with the surface of the junction separation layer 6, and the reference potential E shown in FIG. 2 is applied thereto. . The power supply terminal Te on the second circuit section C2 side has its electrode film in common contact with the surfaces of the epitaxial layer 5 and the junction separation layer 6, and has an n-type second semiconductor region 2 and a p-type third semiconductor region. 3, and the non-reference potential ν0 shown in FIG. 2 is applied thereto.

In this example, since the non-reference potential Vo of the power supply terminal Te of the second circuit section C2 is more positive than the reference potential E of the power supply terminal To of the first circuit section C1, the potential difference between them is A reverse bias is applied to the pn junction between CI and second semiconductor region 2, thereby separating the operating potentials of both circuit portions CI and 02 from each other and preventing operational interference.

In the embodiment of FIG. 4, the Darlington transistor 52 shown in FIG. 6 is used as the transistor of the output section 50 of FIG.
4 is shown for each of the first circuit section C1 and the second circuit section C2 in the figure (al).The only difference from the embodiment shown in FIG. 3 is the transistors 53 and 54.
A buried layer 4n and a collector connection layer 7 are shared by both transistors, a base layer 8 and an emitter layer 9 are provided separately, and then Darlington connections are made as shown.

Also in this embodiment, on the second circuit section 02 side, the non-reference potential Vo is applied to the second semiconductor region 2 and the third semiconductor region 3 via the electrode film of the terminal Te, and the first
Similarly to the embodiment shown in FIG. 3, a reverse bias is applied to the pn junction between the semiconductor 8N region 1 and the second semiconductor region 2 due to the difference in potential between the two regions.

In any of the above embodiments, by appropriately selecting the impurity concentration and diffusion depth of the second semiconductor region 2, a sufficient breakdown voltage value can be maintained between the first circuit section C1 and the second circuit section C2. be able to.

The present invention is not limited to the embodiments described above, and the present invention can be implemented in various embodiments. The conductivity type shown in the figure is of course arbitrary and can be selected as appropriate. In addition, in the embodiment, the reference potential is set to the ground potential E in FIG. 2, but in some cases it may be set to the power supply potential Can be connected to a circuit.

(Effects of the Invention) As is clear from the above, in the present invention, since the first circuit section connected to the reference potential of the external circuit and the second circuit section connected to the non-reference potential are incorporated into the integrated circuit device, one of the conductive A second semiconductor region of the other conductivity type and a third semiconductor region of one conductivity type are sequentially nested from the surface of the first semiconductor region in a predetermined range to form the first circuit portion within the first semiconductor region. Then, a second circuit portion is formed in each third semiconductor region, and
By operating both circuit sections with the reference potential of the external circuit applied to the first semiconductor head region and the non-reference potential of the external circuit applied to the second and third semiconductor regions w4, the following effects can be achieved. .

(a) The second and third semiconductor regions are connected to the same potential and a non-reference potential is applied to the first semiconductor region and the second semiconductor region having different conductivity types.
By applying a potential difference between a reference potential and a non-reference potential in a reverse bias direction to the pn junction between the semiconductor region and the third semiconductor region, the third semiconductor region is potential-leveraged from the first semiconductor region. can be incorporated into a single semiconductor device.

(b) The first circuit section in the first semiconductor region and the second circuit section in the third semiconductor region can be operated completely independently under different potentials without mutual interference.

(C) By appropriately selecting the impurity concentration and diffusion depth of the second semiconductor region, a sufficiently high breakdown voltage can be achieved between the first circuit section in the first semiconductor region and the second circuit section in the third semiconductor region. It can have a value.

Thus, the present invention makes it possible to integrate in a single integrated circuit device a large number of circuit sections that must be connected to a non-reference potential that can vary independently in addition to the reference potential in an external circuit. This not only reduces the cost of the integrated circuit itself, but also contributes to reducing mounting space and labor.

[Brief explanation of drawings]

1 to 4 relate to the present invention; FIG. 1 is a cross-sectional view showing the principle of a semiconductor integrated circuit device according to the present invention, FIG. 2 is a circuit diagram showing an example of its application, and FIG. 3 is a diagram illustrating the present invention. FIG. 4 (a
) is an enlarged cross-sectional view of a main part of an integrated circuit device according to a different embodiment, and FIG. 3 ) is a circuit diagram of a Darlington transistor built therein. 5 and subsequent figures relate to the prior art, and FIG. 5 is a circuit diagram showing a conventional integrated circuit device and an example of its application;
FIG. 6 is a circuit diagram showing a circuit section or base drive circuit incorporated in an integrated circuit device, and FIG. 7 is an enlarged sectional view of a main part of a conventional integrated circuit device incorporating this circuit. In these figures, 1: the first semiconductor region or the substrate of the integrated circuit device; 2: the substrate of the integrated circuit device;
2nd semiconductor region, 3: third semiconductor region, 4n: n-type buried layer, 4p: p-type buried layer, 5: epitaxial layer or collector region, 6: junction separation layer, 7: collector connection layer, 8
: base layer, 9: emitter layer, 10: integrated circuit device according to the present invention, 11.12: conventional integrated circuit device, 30: inverter as an example of external circuit, 31: internal transistor, 32: freewheeling diode , 4o: Load such as motor, 50: Output section, 51: Transistor, 52
; Darlington transistor, 53, 54: Transistor constituting the Darlington transistor, 60: S production section, 61: Inverter, 62: Transistor, 63: Resistor, C: Base drive circuit, C1: First circuit section, C2: Second Circuit section, E: Reference potential or ground potential of external circuit,
Tb: Base terminal of the circuit section, Te: Power terminal of the circuit section,
To = output terminal of the circuit section, Tν: power supply terminal of the circuit section, ■
: power supply potential point of the external circuit, vo: non-reference potential or output voltage of the external circuit. 3rd Thousand Years, 4th Chapter, 4th Part 8th, 2nd Thousand Prisoners of War, 4th Powder, Figure 1, Cow Leading Tashishasa A, Figure 2, Funeral Illustration

Claims (1)

[Claims] An integrated circuit device incorporating a first circuit section to be connected to a reference potential side of an external circuit and a second circuit section to be connected to a non-reference potential side, the integrated circuit device comprising: a first semiconductor region of one conductivity type; A second semiconductor region of the other conductivity type built in the first semiconductor region.
a semiconductor region and a third semiconductor region of one conductivity type formed in the second semiconductor region, the first circuit part is in the first semiconductor region, and the second circuit part is in the third semiconductor region. 1. A semiconductor integrated circuit device, wherein the first semiconductor region is connected to a reference potential point of an external circuit, and the second and third semiconductor regions are connected to a non-reference potential point of an external circuit.