GB2113915A

GB2113915A - Semiconductor integrated circuit device

Info

Publication number: GB2113915A
Application number: GB08301731A
Authority: GB
Inventors: Setsuo Ogura; Shizuo Kondoh
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 1982-01-25
Filing date: 1983-01-21
Publication date: 1983-08-10
Also published as: SG36587G; FR2520555A1; JPH0334661B2; GB2133622B; FR2520555B1; KR910002036B1; JPS58127363A; MY8700613A; GB8301731D0; HK71287A; KR840003536A; IT8319236A0; HK70687A; GB8403188D0; IT1160470B; GB2133622A; DE3302206A1; GB2113915B

Abstract

A cross-under wiring construction comprises a semiconductor layer 5 forming a cross-under wiring, and an isolating semiconductor layer 3 formed in a semiconductor region 2, wherein a potential is applied to layer 3 so that operation of parasitic transistor (Qp) is suppressed, the construction is particularly for use in stacked I<2>L integrated circuits comprising blocks of I<2>L elements. Layers 3 may have potentials set to equal those of regions 2, but in the case of stacked I<2>L that requires a plurality of cross- under wiring layers formed close to each other in a P-type layer (3), it is desirable that the layers 3 are connected to a lower potential e.g. the regions 2 in the I<2>L block of a previous stage. A device of highly integrated form may be fabricated by ensuring that the wiring layers which extend from low potential driving I<2>L blocks to high potential driving I<2>L blocks do not use cross-under wiring, such wiring only being used within a single I<2>L block. The cross-under wiring may have significant resistance and may act as a resistance element. <IMAGE>

Description

SPECIFICATION Semiconductor integrated circuit device BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and more specifically to the wiring construction of an 12L (integrated injection logic) semiconductor integrated circuit device.

The number of gates in such devices increases with the increase in the range of uses to which they are put, and the consumption of electric power increases correspondingly.

An 12L circuit construction which is called stacked 12L has been employed in order to reduce the power consumption of 12L circuits which have increased numbers of gates. The stacked l2L construction consists of a plurality of 12L blocks, each formed of a plurality of 12L elements that provide a logic structure in an electrically isolated semiconductor region, the 12L blocks being connected in series between a reference potential (ground potential) and a predetermined supply potential.

In order to increase the degree of freedom in the wiring layout of stacked 12L devices and to increase the degree of integration, it is possible to attempt to form many cross-under wirings, which utilize a diffusion layer in the semiconductor.

The inventors of the present invention have previously proposed cross-under wirings of the construction shown in Fig. 1 for use in stacked 12L devices. As shown in Fig. 1the cross-under wiring is formed by forming an N±type diffusion wiring layer 5, which crosses an aluminum'wiring 4, on a portion of the surface of an N-type epitaxial layer 2 in a P--type silicon substrate 1, with an intermediate P-type diffusion layer 3. The reason for using the N±type diffusion wiring layer 5 as a cross-under wiring is because the N±type diffusion wiring layer 5 is formed simultaneously with the formation of the collector region (N±type diffusion layer) of the inverse transistor of an 12L element, and because the N±type diffusion wiring layer 5 has an impurity concentration greater than that of the Ptype diffusion layer 3 and, hence, has a low sheet resistance, lending itself well for being used as a cross-under wiring.

In stacked 12L devices, it is accepted practice to electrically connect the 12L. blocks by utilizing cross-under wirings, and to extend the wiring layer in a given 12L block into other 12L blocks by detour.

With reference to Fig. 2, N--type epitaxial layers 2a, 2b and 2c electrically isolated by the P-type isolation layer 6 are used as 12L blocks having quite different potentials from each other For instance, in the case of a three-stage stacked 12L IC shown in Fig. 2, the N-type epitaxial layer 2a has a potential V2a= 1.4 volts, the N=type epitaxial layer 2b has a potential V2b=0.7 volts, and the N--type epitaxial layer 2c has a potential V2c=O volt. Therefore, when the N±type diffusioncross-under wiring layers 5a 5b, Sc are formed in the N--type epitaxial layers 2a, 2b, 2c, the N±type diffusion cross-under wiring layers being in contact with the wiring layers that electrically connect the 12L blocks and being further in contact with the detouring wiring layers, there arises a problem with regard to potentials of the P-type diffusion layers 3a, 3b, 3c that are formed to provide PN junctions to electrically isolate the N±type diffusion cross under wiring layers from the N--type epitaxial layers 2a, 2b, 2c. The cause, it has been found, is that part of the cross-under wiring construction serves as a parasitic NPN transistor Qp which is made up of N±type diffusion wiring layer 5, P-type diffusion layer 3 and N--type epitaxial layer 2 as shown in Fig. 1. Here, it is supposed that the cross-under wiring construction of Fig. 1 exists in an 12L block (a third stage block) in which the operational voltage ranges from 1.4 volts to 2.1 volts. That is, it is supposed that the cross-under wiring construction exists in the N=type epitaxial layer 2a shown in Fig.

2. In Fig. 1, furthermore, the wiring layer M extends from the second stage 12L block in which the operational voltage lies between 1.4 volts and 0.7 volts (i.e. extends from the 12L block that exists in the N--type epitaxial layer 2b shown in Fig. 2) and connects to the N±type diffusion wiring layer 5. In the above-mentioned cross-under wiring construction, the P-type diffusion layer 3 has a potential of 1.4 volts, which is the same as the potential of the N--type epitaxial layer 2. When the wiring layer M has a potential of 0.7 volts, therefore, a forward bias is applied to the PN junction J between the N±type diffusion layer 5 and the P-type diffusion layer 3, and the parasitic NPN transistor Qp operates.

Operation of such a parasitic NPN transistor becomes a problem in a portion where the wiring layer which extends from a low-potential driving l2L block to a high-potential driving 12L block, crosses under the diffusion layer in the high-potential driving l2L block. The action of the parasitic NPN transistor makes it impossible to properly operate the inverse transistor of an 12L element that is connected via the cross-under diffusion layer.

SUMMARY OF THE INVENTION One aspect of the present invention provides a semiconductor integrated circuit device comprising a first semiconductor layer of a first type of conductivity (e.g. N-type), a second semiconductor layer of a second type of conductivity (e.g. P-type) which is in contact with the first semiconductor layer, and a third semiconductor layer of the first type of conductivity (e.g. N-type) which is in contact with the second semiconductor layer, wherein two metal wiring layers are connected to the third semiconductor layer at spaced positions, and a predetermined potential is applied to the second semiconductor layer so that a forward bias will not be applied across the first semiconductor layer and the second semiconductor layer.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a perspective view showing a cross-under wiring (resistance); Fig. 2 is a sectional view which schematically illustrates the cross-under wiring formed in a laminated semiconductor region; Fig. 3 is a diagram of a stacked l2L circuit to which the present invention can be applied; Fig. 4 is a sectional view showing a cross-under wiring in an 12L block; Fig. 5 is a plan view of a stacked 12L IC according to a first embodiment of the present invention; Fig. 6 is a sectional view which corresponds to Fig. 5; Fig. 7 is a plan view of a stacked l2L IC according to a second embodiment of the present invention Fig. 8 is a sectional view showing a portion of the cross-under wiring of Fig. 7; Fig.9 is a plan view of a stacked 12L IC according to a third embodiment of the present invention; and Fig. 10 is a plan view showing a portion of the cross-under wiring according to a further embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, below is briefly described the construction of a stacked 12L circuit to which the present invention may be applied.

Fig. 3 shows a portion of the stacked 12L circuit, and illustrates 12L blocks of the n-th stage, (n-1 )th stage, and the first stage, as well as the manner in which they are interconnected. In Fig. 3, thick solid lines represent metal wiring layers for connecting 12L elements within the 12L blocks and for connecting the 12L blocks. Resistors R1, R3 equivalently demonstrate cross-under wiring layers (diffusion layers) formed in a semiconductor integrated circuit device. A resistor R2 has a resistance greater than those of the resistors R,, R3, works to shift the level and to properly operate the transistor Q of the (n-l)th stage, and further works as a cross-under wiring.

The l2L block in each stage has been independently formed in an N=type epitaxial semiconductor layer 2 which is electrically isolated from its counterparts by a P--type semiconductor substrate 1 and a P-type isolation layer 6, as shown in Fig. 4. That is P-type semiconductor layers 7, 8, and N±type semiconductor layers 9, 1 0 are selectively formed in the isolated N--type epitaxial semiconductor layer 2. The P-type semiconductor layer 7 serves as an injector region, i.e. serves as an emitter of a lateral PNP transistor, the N--type epitaxial semiconductor layer 2 serves as a base of the transistor, and the P type semiconductor layer 8 serves as a collector of the transistor. Moreover, the N--type epitaxial semiconductor layer 2 serves as an emitter of an inverse NPN transistor, the P-type semiconductor layer 8 serves as a base of the transistor, and the N±type semiconductor layer 9 serves as a collector of the transistor. Thus, an l2L element (a circuit element having a logic function) is constructed. Therefore, a plurality of the thus constructed l2L elements are formed in each of the epitaxial semiconductor layers that are isolated from each other, to constitute the individual l2L blocks.

In Fig. 4, the N±type semiconductor layer 5 formed in the P-type semiconductor layer 3 serves as a diffusion resistance for shifting the level, which also serves as a cross-under wiring, as mentioned above, and forms a resistor R2 as shown in Fig. 3.

In accordance with the present invention, the stacked 12L circuit is formed in a semiconductor substrate as illustrated in the following embodiments.

Embodiment 1: Fiq. 5 illustrates a stacked 12L IC in which the P-type layers 3a, 3b and 3c are connected to a minimum potential or to ground potential (GND) in order to isolate cross-under wiring layers (N±type' layers) 5a, 5b and Sc from the N--type epitaxial layers 2a, 2b and 2c.

The stacked 12L IC of Fig. 5 consists of 12L blocks in three stages. In this case, potentials of the N- type epitaxial layers in the l2L block of the n-th stage (third stage), 12L blocks of the (n-1)th stage (second stage) and 12L block of the first stage, are held at 1.4 volts, 0.7 volts and 0 volt, respectively. In each of: the 12L blocks as will be obvious from Fig. 5, furthermore, potentials of the P-type layers 3a, 3b, 3c where cross-under wiring layers 5a, Sb, Sc are formed under the metal wiring layers (aluminum layers) La, Lb, Lc, are maintained at a minimum potential, i.e. maintained at ground potential (0 volt) being connected through wirings 1 a, 1 b ,1 1 c. This makes it possible to prevent the parasitic transistor operation that will be established by the cross-under wiring layers (N±type layers) which have a high potential, the P-type layers and the N--type epitaxial layers, That is, a metal wiring layer M1 which extends from the l2L block of the (n-1 )th stage is connected to the cross-under wiring layer 5a.

Accordingly, the cross-under wiring layer 5a has applied to it a potential (0.7 volts to 1.4 volts) which is higher than the potential (0 volt) of the P-type layer 3a. Therefore, a reverse bias is applied across the cross-under wiring layer 5a and the P-type layer 3a, and no parasitic transistor operation takes place at the position of the cross-under wiring layer 5a. Further, a metal wiring layer M2 extending from the 12L block of the n-th stage is connected to the cross-under wiring layer 5b. Therefore, the cross-under wiring layer 5b has applied to it a potential (1.4 volts to 2.1 volts) which is higher than the potential (0 volt) of the P-type layer 3b. Consequently, a reverse bias is applied across the cross-wiring layer 5b and the P-type layer 3b, so that no parasitic transistor operation takes place at the position of the cross under wiring layer 5b. Furthermore, a metal wiring layer3 in the 12L block of the first stage is connected to a cross-under wiring layer 5c. Therefore, the cross-under wiring layer Sc has applied to it a potential (0.7 volts) which is equal to, or greater than, the potential (0 volt) of the P-type layer 3c.

Accordingly, no forward bias is ever applied across the cross-under wiring layer Sc and the P-type layer 3c.

As mentioned above, no forward bias is applied across the cross-under wiring layers 5a,-5b, 5c and the P-type regions 3a, 3b, 3c, and, hence; no parasitic transistor operation takes place. Fig. 6 is a sectional view which schematically illustrates the wiring circuit of Fig. 5.

According to the above-mentioned embodiment, the P,7type layers 3a, 3b and 3c are maintained at ground potential in order to prevent the occurrence of parasitic transistor operation. Therefore, the number of metal wiring layers connected to the P-type layers increases, resulting in a decrease in the degree of integration of the semiconductor integrated circuit device.

In preventing the occurrence of parasitic transistor operation, it will be understood that the P-type layers in the 12L blocks need not necessarily be maintained at a minimum voltage, provided the wiring layers extending from the low-potential driving 12L blocks to the high-potential driving 12L blocks, do not cross under the metal wiring layers in the high-potential driving 12L blocks. The following embodiment is to realize a semiconductor integrated circuit device which is constructed in a highly integrated form compared with the above-mentioned embodiment 1, by taking this point into consideration.

Embodiment 2: Fig. 7 illustrates a stacked 12L IC in which the P-type regions 3a, 3b, 3c where cross-under wiring layers (N±type layers) 5a, 5b, Sc of each of the blocks are formed, have potentials that are set to be equal to the potentials of the N--type epitaxial layers 2a, 2b, 2c.

In Fig. 7, P-type layers 3a, 3b, 3c are electrically connected to the N--type epitaxial layers 2a, 2b, 2c by metal wiring layers (aluminum layers) 12a, 1 2b, 1 2c, respectively. In practice, each of the metal wiring (aluminum layer) 4 formed in an SiO2 film 13 traverses the cross-under wiring layer type epitaxial layer 2 to the P-type layer 3, like a metal wiring layer (electrode) 12 of Fig. 8, 8, in which a metal wiring layer (aluminium layer) 4 formed in an SiO2 film 13 traverses the cross-under wiring layer 5, and corresponds to the metal wiring layer La of Fig. 7. The metal wiring layer 4 (La) extends from the 12L block (low-potential driving 12L block) of the (n-l)th stage to the l2L block (high-pote'ntial driving 12L block) of the n-th stage, and does not use a cross-under wiring layer in the 12L block of the n-th stage.

The N±type layer 5 allows the wiring layer M4 in the 12L block of the n-th stage to cross under the metal wiring layer 4 (La).

Table 1 shows potentials Kepi, Vp and VN of the N--type epitaxial layer, P-type layer and N±type layer in the cross-under wiring layers Sa, 5b (diffusion resistors R,1, R2) of the stacked l2L IC thus constructed.

TABLE 1

R,, R, Potential Vepi of N--tyrje epitaxial layer (fixed potential) in volts (n-1) VF (n-2) VF Potential V of P-type layer (fixed potential) in volts (n-1) VF (n-2) F VF Potential VN of cross under wiring layer (variable potential) In volts (n1) VF to n .VF (n-1) VF to n VF VF': forward bias = 0.7 volts n : number of stages As will be obvious from Table 1, the potential of the P-type layer never becomes lower than the potential of the cross-under wiring layer. According to this embodiment, therefore, no parasitic transistor operation'develops even when the potential of the P-type layer is changed from ground potential to the potential of the N--type epitaxial layer in which the P-type layer is formed. For instance, in the case of the stacked 12L IC of three stages as shown in Fig. 7 the potential of the P-type layer 3a in which the cross-under wiring layer 5a (diffusion resistance R1,) is formed, is 1.4 volts which is equal to the potential of the N--type epitaxial layer. On the other hand, the cross-under wiring layer 5a is provided with a potential of 1.4 volts to 2.1 volts. Therefore, forward bias is never applied across the cross-under wiring layer 5a and the P-type layer 3a. The potential of the P-type layer 3b in which the cross-under wiring layer 5b (diffusion resistance R2) is formed, is 0.7 volts which is equal to the potential of the N--type epitaxial layer. The cross-under wiring layer 5b, on the other hand, is connected to the metal wiring layer M2 which extends from the 12L block of the third stage, and is provided with a potential of 1.4 volts to 2.1 volts. Therefore, forward bias is never applied across the cross-under wiring layer 5b and the P-type layer 3b.

In the stacked 12L IC of this embodiment, the wiring regions can be greatly reduced compared with the stacked l2L IC of the above-mentioned first embodiment That is, since the potential of the P-type layer is set to be equal to the potential of the N--type epitaxial layer in which the P-type region is formed, a long wiring for ground potential can be eliminated, and the shortest wiring is required to connect to the neighbouring N--type epitaxial layer. To realize a semiconductor integrated circuit device of a highly integrated form while preventing the occurrence of parasitic transistor operation, according to this embodiment, the wiring layer which extends from a low-potential driving 12L block to a highpotential driving l2L block should not use cross-under wiring, and the cross-under wiring layer should be connected to a metal wiring layer which accomplishes electrical connection within a single l2L block only.

In the case of a wiring layer M2 extending from a high-potential driving 12L block to a low-potential driving l2L block as will be obvious from the above-mentioned embodiments 1 and 2, no parasitic transistor operation takes place even when the cross-under wiring layer 5b is used. Below is mentioned an embodiment in which this technical idea is positively utilized.

Embodiment 3 Fig. 9 illustrates a stacked 12L IC in which the metal wiring layer Ms of the high-potential driving l2L block is allowed to run into a low-potential driving 12L block in detour due to the requirement of wiring layout, and use is made of the cross-under wiring layer 5b.

In Fig. 9, potentials of the P-type layers 3b, 3c in which cross-under wiring layers (diffusion resistances) 5b, Sc are formed, are set to be equal to the potentials of the N--type epitaxial layers 2b, 2c in which the P-type layers are formed. The potentials of the P-type layers 3b, 3c may instead be maintained at a minimum potential (ground potential).

The above stacked 12L IC prevents the operation of a parasitic transistor that will be established by the N--type epitaxial layer 2b, P-type layer 3b, and cross-under wiring layer (NX-type layer) 5b, because of the same reasons as mentioned in the embodiment 2. In particular, the potentials of the N--type expitaxial layer 2b and the P-type layer 3b do not become equal to the potential of the cross-under wiring layer 5b, but are necessarily smaller than the potential of the cross-under wiring layer 5b by at least a forward bias voltage level (0.7 volts), to provide increased margin. In this circuit, also, the wiring regions can be greatly reduced on account of the same reasons as mentioned in the second embodiment.

The stacked 12L IC of the third embodiment can be modified as mentioned below.

(1 ) In Fig. 9, the cross-under wiring layer 5b contacting the metal wiring layer M5 may be formed in the 12L block in which the cross-under wiring layer Sc has been formed.

In this case, the potential of the P-type layer 3c is lower than the potential of the P-type layer 3b, and the parasitic transistor does not operate.

(2) The cross-under wiring layer 5b may be formed in the N--type epitaxial layer 2a (12L block of the n-th stage) instead of the N--type epitaxial layer 2b (l2L block of the (n-l)th stage), and the potential of the P-type layer may be set to be equal to the potential of the N--type epitaxial layer 2b (l2L block of the (n-l)th stage) to isolate the cross-under wiring layer 5b from the N--type epitaxial layer 2a.

In this case, the potential of the P-type layer is lower than the potential of the N--type layer 2a, and forward bias is not applied across the P-type layer and the N--type epitaxial layer 2a. The crossunder wiring layer is provided with a potential higher than the potential of the P-type layer, and forward bias is not applied across the cross-under wiring layer and the P-type layer. It is therefore possible to prevent the occurrence of parasitic transistor operation.

When the potential of the P-type layer is set to be lower than the potential of the N--type epitaxial layer, it is possible to form a plurality of cross-under wiring layers close to each other in the P-type layer. This point will be described below in detail.

Fig. 10 illustrates a portion of a sjacked-l2L IC in which two cross-under wiring layers 5aX, 5a2 are formed close to each other in a P-type layer 3.

When the two cross-under wiring layers 5aa, 5a7 are formed close to each other in the P-type layer 3 as shown in Fig. 10, however, there arises the problem of a parasitic lateral transistor Op made up of the two cross-under wiring layers (N±type layers) 5a1, spa2, and the P-type layer 3. Namely, parasitic lateral transistor operation will develop (case A), or will not develop (case B), depending upon the conditions.

Table 2 shows potentials of the cross-under wiring layers spa1, spa2, and of the P-type layer in these cases A and B.

TABLE 2

Case A Case B Potential VN1 of first cross-under wiring layer 5a (varying potential) in volts (n-1).V F ton.V F (n-l) VF Potential Vp of P-type layer 3 (fixed potential) in volts (n-1) VF (n2) F Potential VN2 of second cross-under wiring layer 5a2 (varying potential) in volts (n-1) VF to n .VF (n-1) VF to n VF The above mentioned cases A and B will be described below in detail in connection with a threestage stacked i2L IC (n = 3).

(1) Case A: As shown in dotted lines in Fig. 10, the P-type layer 3 is connected to the N--type epitaxial layer 2 through an electrode 1 4A, to maintain the potential of the P-type layer 3 at 1.4 volts. When the potential of the first cross-under wiring layer 5a1 is VN1 = 2.1 volts, and the potential of the second cross-under wiring layer 5a2 is Vw2 = 1.4 volts, the potential of a portion of the P-type layer (base) 3 rises, so that the parasitic lateral transistor Qp will operate. This is because the P-type layer 3 has a low impurity concentration and, hence, has resistance R5 which causes the potential VPR of a portion of the P-type layer 3 to become greater than 1.4 volts. Therefore, a voltage greater than 0.7 volts is applied across the P-type layer (base) 3 and the second cross-under wiring layer (emitter) 5a2, so that the transistor Qp will operate. Further, when the first cross-under wiring layer 5a1 has a potential VNt = 1.4 volts, and the second cross-under wiring layer 5a2 has a potential of Vn2 = 2.1 volts, the parasitic lateral transistor Op will also operate. In this case, the first cross-under wiring layer 5a, serves as an emitter, and the second cross-under wiring layer 5a2 serves as a collector.

(2) Case B: As shown in bold lines in Fig. 1 0, the potential of the P-type layer 3 is set to be equal to the potential (0.7 volts) of the N--type epitaxial layer in the 12L block of the (n - 1 )th stage by a metal wiring layer 1 4B. That is, the potential of the P-type layer 3 is set to be lower than the potential of the N--type epitaxial layer 2.

When the first cross-under wiring layer 5a1 has a potential VN1 = 2.1 volts, and the second cross under wiring layer Sa2 has a potential VN2 = 1.4 volts, the potential of a portion of the P-type layer (base) 3 rises as illustrated in the case A. However, since the potential of the rest of the P-type layer 3 remains at 0.4 volts, the potential VPR at this portion of the P-type layer never rises about 1.4 volts.

Therefore, the parasitic lateral transistor Qp does not operate.

When the potential of the P-type layer is set to be lower than the potential of the N--type epitaxial layer as in the above-mentioned case B, the parasitic lateral transistor does not operate even when a plurality of cross-under wiring layers are formed in the P-type layer close to each other.

Therefore, in the case of a stacked 12L which requires a plurality of cross-under wiring layers formed close to each other in the P-type layer, it is desired that the P-type layer is electrically connected to a lower potential, e.g. to the N'-type epitaxial layer in thel2L block of the previous stage.

Claims

1. A semiconductor integrated circuit device comprising a first semiconductor layer of a first type of conductivity, a second semiconductor layer of a second type of conductivity which is in contact with said first semiconductor layer, and a third semiconductor layer of the first type of conductivity which is in contact with said second semiconductor layer, wherein two metal wiring layers are connected to said third semiconductor layer at spaced positions, and a predetermined potential is applied to said second semiconductor layer such that a forward bias will not be applied across said first semiconductor layer and said second semiconductor layer.

2. A semiconductor integrated circuit device comprising a plurality of semiconductor regions that are electrically isolated from each other, circuit elements formed in a portion of each of the regions, metal wiring layers for connecting said circuit elements formed in the regions, cross-under semiconductor layers which cross under said metal wiring layers and which are formed in other portions of the semiconductor regions, and an isolating semiconductor layer which has a conductivity type opposite to that of the cross-under semiconductor layers and which acts to electrically isolate said cross-under semiconductor layers from said regions, wherein a predetermined potential is applied to said isolating semiconductor layer such that a forward bias will not be applied between said cross-under semiconductor layers and said isolating semiconductor layer.

3. A semiconductor integrated circuit device according to claim 2, wherein said circuit element is an integrated injection logic element.

4. An integrated injection logic semiconductor integrated circuit device comprising: first, second and third semiconductor regions that are electrically isolated from each other; a first integrated injection logic block consisting of a plurality of integrated injection logic elements formed in the first semiconductor region; a second integrated injection logic block consisting of a plurality of integrated injection logic elements formed in the second semiconductor region; a third integrated injection logic block consisting of a plurality of integrated injection logic elements formed in the third semiconductor region; first, second and third metal wiring layers that are formed said first, second and third integrated injection logic blocks, respectively; a first cross-under semiconductor layer which-crosses under the first metal wiring layer formed In the first semiconductor region; a second cross-under semiconductor layer which crosses under the second metal wiring layer formed in the second semiconductor region; a a third cross-under semiconductor layer which crosses under the third metal wiring layer formed in the third semiconductor region; a first isolating semiconductor layer which has a conductivity type opposite to that of said first cross-under semiconductor layer, and which acts to electrically isolate said first cross-under semiconductor layer from said first semiconductor region; a second isolating semiconductor layer which has a conductivity type opposite to that of said second cross-under semiconductor layer, and which acts to electrically isolate said second crossunder semiconductor layer from said second semiconductor region; and a third isolating semiconductor which has a conductivity type opposite to that of said third crossunder semiconductor layer, and which acts to electrically isolate said third cross-under semiconductor layer from said third semiconductor region; wherein predetermined potentials are applied to said first, second and third semiconductor regions, the potentials being different from each other, such that forward bias will not be applied between said first cross-under semiconductor layer and said first isolating semiconductor layer, between said second cross-under semiconductor layer and said isolating second semiconductor layer, or between said third cross-under semiconductor layer and said third isolating semiconductor layer.

5. An integrated injection logic semiconductor integrated circuit device according to claim 4, wherein the potential of said second semiconductor region is maintained higher than the potential of said first semiconductor region, and the potential of said third semiconductor region is maintained higher than the potential of said second semiconductor region.

6. An integrated injection logic semiconductor integrated circuit device according to claim 5, wherein the potentials of said first, second and third semiconductor layers are maintained equal to the potential of said first semiconductor region.

7. An integrated injection logic semiconductor integrated circuit device according to claim 5, wherein said first, second and third semiconductor layers are electrically connected to said first, second and third semiconductor regions, respectively.

8. An integrated injection logic semiconductor integrated circuit device according to claim 5, wherein said third semiconductor layer is electrically connected to said second semiconductor region.

9. An integrated injection logic semiconductor integrated circuit device according to claim 8, wherein a fourth cross-under semiconductor layer having the conductivity type same as that of said third cross-under semiconductor layer, is formed in said third semiconductor layer close to said third cross-under semiconductor layer.

1 0. An integrated injection logic semiconductor integrated circuit device according to any one of claims 5 to 9, wherein said third metal wiring layer is electrically connected to an integrated injection logic element in the second integrated injection logic block 1 A stacked l2L semiconductor integrated circuit device comprising first and second 12L blocks each consisting of a plurality of l2L elements, wherein said second 12L block is arrayed on a semiconductor substrate at a position in advance of said first 12L block, and use is made of cross-under wiring layers composed of a semiconductor material formed in the semiconductor substrate to electrically connect 12L elements in said first and second 12L blocks.

1 2. A semiconductor integrated circuit device substantially as any described herein with reference to Figs. 5 to 10 of the drawings.