JPH0455775A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a device to be scan-tested by controlling combination of signal values of slave-clock, scan.clock and master.clock of a flip-flop. CONSTITUTION:When a clock signal is applied through a control circuit for limiting a combination of clock signal values of clocks CK1, CKT, CK2 of a master/slave type scan testing flip-flop, at least two of combinations of three signal values become 'L'. That is, even if a rule of combinations of the clock signal is kept by the control circuit and a test pattern is generated by an arbitrary algorithm, an oscillation, collision of signals can be prevented in a test using the test pattern to efficiently test it.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor integrated circuit devices, and more particularly to a test circuit for semiconductor integrated circuit devices capable of scan testing.

BACKGROUND OF THE INVENTION In recent years, as semiconductor integrated circuits have become larger and more highly integrated, testing for their failures has become extremely difficult and time-consuming. For this reason, in this type of semiconductor integrated circuit, certain improvements are sometimes made to the circuit configuration to facilitate failure testing. According to the conventional method, flip-flops, which originally exist as internal storage elements, are interconnected to add the function of a shift register to this type of semiconductor integrated circuit. It is possible to set the internal state of the circuit or read it externally. This allows sequential circuits to be tested as easily as combinational circuits. This circuit configuration method called the scan method will be explained below using figures.

A master-slave flip-flop for scan testing is shown in FIG. Scan to this flip-flop
If clock CKT and master clock CK2 are applied alternately, it operates as a shift register, and if the scan clock is stopped during normal operation, it becomes a normal master-slave flip-flop. A scan type logic circuit constructed using this flip-flop is shown in FIG. Q terminal of flip-flop FF+ and DTI of FF2
A shift register is constructed by connecting the children. The operation of this circuit during testing will be described below. First, during scan operation, the shift clock CKT
, CK2 are applied alternately, a test signal is input from an external terminal Sl, and a signal is set to each flip-flop. Next, input the normal signal from the external terminal DATA and clock CKI.
.

CK 2 is applied alternately once to execute normal logic operations, and the results are stored in each flip-flop or output to the external terminal OUT. Finally, each flip-flop is connected to the shift clock CKT,
By applying CK2, it is output to the external terminal SO.

The above is the operation when testing a scan type logic circuit, but if all flip-flops in the circuit are connected as shift registers, sequential circuits can be tested in the same way as combinational circuits, and the test pattern can also be set using the D algorithm. It can be automatically generated using a program such as

On the other hand, attempts have recently been made to automatically generate test patterns for sequential circuits, and some programs have already been put into practical use. Using this type of program, it is possible to employ a partial scan method in which only some flip-flops in the circuit are used for scan testing, and the rest are regular flip-flops.

Problems to be Solved by the Invention In a master-slave scan test flip-flop as shown in FIG.
The possible combinations of signal values of CKT and CK2 must be limited. That is, clock CK1. C
The combination must be such that the signal values of KT and CR2 are all 'L', or one of the three is 'H' and the other two are 'L'. This is because if a combination of clock signals is input, oscillation or signal collision may occur.

For example, if there is a path where the output signal of a flip-flop enters the input of the same flip-flop, if clocks CKI and CR2 or clocks CKT and CR2 become °H at the same time, the signal will pass through the flip-flop. Oscillations may occur in the asynchronous feedback loop created. Or clock CK
When I and CKT become H” at the same time, the flip-flop FF
Either the + input terminal or the signal input to the DT is destroyed and is not propagated to the output of the flip-flop.

When generating test patterns using the so-called full scan method, in which all flip-flops in a circuit are scanned, test patterns are first generated for only the combinational circuit from which flip-flops have been removed, and then , it is only necessary to add the shift operation during testing as described in the related art.

However, when generating test patterns using a partial scan method in which only some flip-flops in a circuit are scanned, it is necessary to generate test patterns for sequential circuits including flip-flops. In this case, depending on the algorithm for automatic test pattern generation, there is a possibility that a test pattern may be generated without following the above-described combination rules for clock signals of flip-flops. Therefore,
When testing using the generated test pattern, oscillations and signal collisions occur.

Means for Solving the Problems This invention provides clocks CK1 and CK of flip-flops.
By providing a circuit that can control the signal values of T and CR2, it is possible to limit the possible combinations of clock signal values.

Effect: According to the present invention, even if a test pattern is generated using an arbitrary algorithm for a sequential circuit including a master-slave scan test flip-flop,
When testing using this test pattern, it is possible to prevent oscillations and signal collisions that could occur with conventional techniques.

Embodiment Master-slave scan test flip-flop clock CK1. A control circuit for CKT and CK2 is shown in FIG. Moreover, the truth table of this logic circuit is shown in FIG. As can be seen from this truth table, CK1. C
When the KT and CK2 clock signals are applied through this control circuit, the combination of three signal values is small (both two are L''. Therefore, a full scan circuit as shown in Figure 5 or a partial scan circuit) first in the circuit
If the control circuit shown in the figure is connected as shown in FIG. 3, the above-mentioned problem will be solved.

In other words, by adding this control circuit, the rules for clock signal combinations are observed, and even when testing is performed using a test pattern generated by an arbitrary algorithm,
There is no risk of oscillation or signal collision.

Effects of the Invention As described above, according to the present invention, even when a test pattern for a full-scan or partial-scan logic circuit using master-slave scan test flip-flops is generated by an arbitrary algorithm, In a test using a test pattern, it is possible to prevent oscillation phenomena and signal collisions that may occur with conventional techniques, and it is possible to perform an efficient test.

[Brief explanation of drawings]

FIG. 4 is a block diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention.
For slave method scan test) 1.2, 15.1.6
...Inverter, 3,4゜5.6.9.10,
11.12...2-manpower NAND circuit, 7, 8...
...Three-person NAND circuit, 13.14...
・Combinational logic circuit block, 17.18°19...
...2-person AND circuit, 20...Scan method logic circuit block. Name of agent: Patent attorney Shigetaka Awano and one other person Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] A semiconductor integrated circuit device that can be tested by a scan test method using a level-responsive master-slave flip-flop, comprising means for controlling the combination of signal values of a slave clock, a scan clock, and a master clock of the flip-flop. A semiconductor integrated circuit device comprising: