JPH0455276B2 - - Google Patents

Description

[Detailed description of the invention] A. ``Objective of the invention'' [Industrial application field] The present invention changes a voltage according to a start fractional time and a stop fractional time, and a processor calculates a digital signal based on this voltage. This invention relates to a device that measures measured time by adding .

[Conventional technology]

Generally, the following principle is adopted to measure time with high precision. A clock signal with a period t ₀ is passed through a gate that is open during the period of time to be measured Tx, and the number N of the clocks passing through is counted. And, Nt ₀ is the time width.

Strictly speaking, this method does not hold Tx=Nt ₀ , but rather TxNt ₀ . This is because Tx is usually not divisible by t ₀ and there are small fractional times. This is shown in FIG. In FIG. 7, ΔT ₁ in c is the starting fractional time from the rising edge of Tx to the clock C ₀ occurring immediately thereafter, and ΔT ₂ in d is the starting fraction time from the falling edge of Tx to the clock C 0 occurring immediately thereafter. This is the stop fractional time to Cn. Then, the gate is opened during the period between the clock signals _C0 and _C0 (see f in FIG. 7), and the number of clocks passing through is counted. Letting the number of clocks in that period be N, the time width Tx [g in FIG. 7] is expressed by equation (1).

Tx=Nt ₀ +ΔT ₁ −ΔT ₂ (1) Therefore, if we measure the fractional times ΔT ₁ and ΔT ₂ , we get
It can be seen from equation (1) that the time width Tx can be measured with a resolution greater than the clock period _t0 .

Therefore, the present applicant filed an application on June 6, 1985 for a "time measuring device" that can accurately and rapidly measure the fractional time (ΔT ₁ , ΔT ₂ ). This application is hereinafter referred to as the "prior application."

To briefly explain the invention of this "prior application", a constant voltage is applied to the capacitor 3 via the voltage switch SW.
Add V ₀ in advance and keep the voltage of capacitor 3 at V ₀ . In this state, fractional time (ΔT ₁ ,
A constant current I ₁ is applied to the capacitor 3 via the current switch 7 which operates for a period of ΔT ₂ ), thereby discharging the charge stored in the capacitor 3.

Since the voltage of the capacitor 3 changes according to this discharge period, fractional hours are measured by measuring the voltage before and after this change.

[Problem that the invention seeks to solve]

The invention of this "prior application" has the advantage that even if the start fractional pulse and the stop fractional pulse occur close to each other, they can be accurately measured.

However, the "first application" has a constant voltage to capacitor 3.
A voltage switch SW was used as a means to apply V ₀ . Voltage switches generally differ from current switches in the following points:

A current switch can be implemented with a simpler configuration than a voltage switch. That is, the current switch can be easily constructed with, for example, two transistors. On the other hand, voltage switches are, for example, MOS/FET (metal oxide
The structure becomes complicated because it consists of semiconductors, field effect transistors, etc.

Current switches have faster switching speed than voltage switches. The reason for this is that in the case of a voltage switch, in order to completely turn on the MOS/FET, it is necessary to switch and apply a high voltage signal to its gate terminal, but it is difficult to switch a high voltage signal at high speed. It is. On the other hand, this does not happen with current switches.

The purpose of the present application is to provide a time measuring device that uses a current switch as a switching means to apply an initial value voltage to a capacitor, can measure time at a higher speed than the "prior application", and has a simple configuration. be.

B "Structure of the Invention" [Means for Solving the Problems] In order to solve the above problems, the present invention applies a constant current _i2 to the integrating capacitor 17 for a fractional time period, and the initial value voltage Vd A device that measures a measured time by adding arithmetic operations to a digital signal based on the voltage of a capacitor 17 that changes starting from A current switch 14 operates during a period other than this period, and a current i ₁ is applied to the parallel circuit of the capacitor 17 and diode 18 through this current switch 14, and the capacitor 17 is initialized by the saturation voltage of the diode that is turned on at this time. It is equipped with a constant current source 13 that provides a value voltage Vd, and the following means.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a diagram showing an example of the main part configuration of the present invention, and FIG.
The figure is a diagram for explaining the operation of the switch section in FIG. 1, FIG. 3 is a diagram showing a specific configuration example of the switch section in FIG. 1, and FIGS. 4 and 5 are for time measurement according to the present invention. FIG. 2 is a block diagram showing the overall configuration of the device.

First, the entire apparatus according to the present invention will be explained using FIG. 4. In the figure, 1 and 2 are input circuits, which shape the waveforms of introduced signals s1 and s2 to be measured. Since the signals to be measured s1 and s2 are superimposed by a nozzle, etc., the signals to be measured can be easily handled in subsequent circuits by shaping the waveforms. FIG. 4 shows a configuration for measuring the time difference between two signals s1 and s2.

3 is a clock generator, which has a constant pulse width t ₀
The signal [see FIG. 7b] is output.

Reference numeral 4 denotes a gate circuit, which includes a fractional pulse generator 4a therein. This gate circuit 4
introduces signals from the input circuits 1 and 2 and the clock generator 3, and generates the start fractional pulse s3 [see FIG. 7c] and the stop fractional pulse s4 explained in FIG.
[See Figure 7d] and the gating clock signal sg
[See Figure 7g] is output. Further, this gate circuit 4 internally generates a measured time width signal sx as shown in FIG. 7a, and applies it to the fractional pulse generator 4a. The configuration of the gate circuit 4 and the fractional pulse generator 4a can be a common circuit. In this application, since this gate circuit 4 is not a characteristic part, a specific circuit thereof will not be described.

5 is a counter and a gating clock signal
This is used to count sg.

Reference numerals 6 and 7 denote time/voltage converters, which change the voltage according to the pulse width (ie, fractional time) of the introduced pulse signals s3 and s4, and convert this voltage into a digital signal for output. The structure of the time/voltage converters 6 and 7 is a feature of the present invention, and a specific example of the structure of this portion is shown in FIG. 1 and will be explained in detail later.

8 is a processor which inputs signals from the counter 5 and time/voltage converters 6 and 7, performs the calculation shown in equation (1), and calculates the time width Tx to be measured. In addition, calculations for correcting errors based on bias currents and offset voltages in the time/voltage converters 6 and 7 are also performed. However, since this correction calculation is not directly related to the technology to be solved by the present invention, in this specification,
This correction calculation will not be explained.

In addition, in Fig. 4, there are two input circuits and a time circuit.
Although an example of a configuration including two voltage converters has been given, it is also possible to have one each. An example of the configuration in this case is shown in FIG. When there is only one input circuit 1 as shown in Fig. 5, the signal to be measured is a signal that has a time width Tx to be measured from the beginning as shown in Fig. 7a, and this time width Tx is measured. This is the case. At this time,
The gate circuit 4 can immediately obtain the time width signal sx to be measured and introduce this signal sx into the fractional pulse generator 4a.

Further, the fractional pulse generator 4a can also synthesize the start fractional pulse s3 and the stop fractional pulse s4 and output two fractional pulses as a serial signal as shown in e of FIG. In such a case, only one time/voltage converter is sufficient.

Describing the advantages and disadvantages of the configurations of FIGS. 4 and 5 as described above, the configuration of FIG.
3 and stop fractional pulse s4, respectively.
Since a dedicated voltage converter is provided, accurate measurements can be made even when the time width Tx to be measured is very short (i.e. measurements where a start fractional pulse s3 and a stop fractional pulse s4 occur close to each other). I can do it. The half configuration becomes complicated.

On the other hand, the structure shown in FIG. 5 is simple. However, processing time is always required to convert the pulse width to voltage and then to digital, so if the start fractional pulse and stop fractional pulse occur very close to each other, only one time/voltage converter is needed. This makes measurement difficult.

The time/voltage converter shown in FIG. 1, which is the main part of the present invention, can be used in both the time measuring devices shown in FIG. 4 and FIG. 5 explained above, and can exhibit its effects. can.

In Figure 1, p1 and p2 are input terminals, and p1 receives a wait (WAIT) signal from the processor 8.
A signal is added. A start fractional pulse and a stop fractional pulse are applied to p2.

11 is an RS flip-flop (hereinafter simply FF11)
), a standby signal is applied to the S terminal, and a fractional pulse is applied to the R terminal. Also Q
The output s11 of the terminal is used as a signal for controlling a current switch which will be described later.

A delay line 12 introduces a fractional pulse and delays it by a time τ. The output s12 of this delay line 12 is used as a signal s12 for controlling a current switch, which will be described later. This delay line 1
As for 2, a commercially available product can be used. Or, even if this delay line 12 is not provided, the first
By lengthening the wiring through which the signal s12 in the figure passes, the signal s12 can be delayed. That is, the delay line 12 is not specially provided, but is equivalent to the delay line 1.
It can be configured so that it can perform the same function as 2.

Reference numerals 13 and 16 are constant current sources, and the constant current source 13 causes a constant current i ₁ to flow, and the constant current source 16 causes a constant current i ₂ to flow in the directions shown in FIG. The constant current sources 13 and 16 can be easily constructed from transistors or high resistances, for example.

14 and 15 are current switches, for example, the third
As shown in the figure, it can be constructed using transistors. The current switch 14 is controlled on/off by the output signal s11 of the FF 11, and the current switch 15 is controlled by the output signal s12 of the delay line 12.
Controlled on/off. Constant current source 13, current switch 14, current switch 15, and constant current source 16 are connected in series as shown in FIG.

Reference numeral 17 denotes an integrating capacitor, which is placed between the connection point between current switches 14 and 15 and the circuit ground. The terminal voltage of this capacitor 17 changes according to the pulse width of the fractional pulse.

A clamp diode 18 is provided in parallel to the capacitor 17.

Reference numeral 19 denotes a buffer amplifier, which is composed of an amplifier with high input resistance. This buffer amplifier 19 amplifies the terminal voltage of the capacitor 17, converts the impedance, and transmits it to the next stage. Note that the amplifier with high input resistance can be easily constructed using, for example, a non-inverting operational amplifier.

20 is an AD converter, buffer amplifier 19
The analog signal introduced from the processor 8 is converted into a digital signal and transmitted to the processor 8. In addition,
In the field to which the present invention pertains, high speed is required, so a flash type (fully parallel type) AD converter is usually used.

Note that FIG. 2 is a diagram for explaining the operation of the peripheral parts of the current switches 14 and 15 and the capacitor 17.
FIG. 3 is a diagram showing a specific example of the configuration of the current switches 14 and 15, and FIG. 6 is a time chart of the device shown in FIG. 1. The operation of the device shown in FIG. 1 will be explained with reference to these figures. .

(1) After the standby signal [see Fig. 6 e] is input to the terminal p1, the FF 11 is set, the current switch 14 is on, and the current switch 15 is off [Fig. 6 b and c]. reference]. Therefore, the current _i1 of the constant current source 13 charges the capacitor 17, and when the potential reaches the forward voltage Vd of the diode, the diode 18 is charged as shown in FIG.
, the voltage of the capacitor 17 is held at the forward voltage Vd of the diode 18 [6th
See Figure d].

(2) As soon as the fractional pulse is applied to terminal p2
FF 11 is reset and current switch 14 is turned off at the rising edge of the fractional pulse (see Figure 6b). On the other hand, since the fractional pulse is delayed by the delay line 12, the current switch 15 turns on with a delay of time .tau. from the rising edge of the fractional pulse (see FIG. 6c). This time τ guarantees the time until the current switch 14 is reliably turned off. In other words, the switching means using semiconductors does not turn off immediately, but usually
As shown in FIG. 6b, the signal turns off with a dull waveform.

If the current switch 15 is turned on while the current switch 14 is still on, equation (2) explained below will not hold.
The delay time τ is necessary because accurate time/voltage conversion cannot be performed.

(3) When the current switch 15 is turned off after the current switch 14 is turned off [see Fig. 6c],
The capacitor 17 is charged or discharged via the switch 15 with a constant current _i2 . This charging or discharging operation continues while the current switch 15 is on, that is, during the fractional pulse.
Voltage Vc of capacitor 17 after fractional time ΔT
is expressed by equation (2).

Vc=Vd-1/C∫ ^T ₀ i ₂・dt =Vd-i ₂・ΔT/C (2) Where, Vd: Forward voltage of diode 18 C: Capacity of capacitor 17 In this way, the voltage of capacitor 17 is , the voltage changes according to the pulse width of the fractional pulse, that is, the fractional time.

If the current switches 14 and 15 are configured as shown in FIG. 3, high-speed switching operations can be performed. In Figure 3, current switch 1
4 is composed of differential transistors Q ₁ and Q ₂ , and current switch 15 is composed of differential transistors Q ₃ and Q ₄ . And the Q of FF11 is connected to the terminal p3.
The output of the FF11 is applied to the terminal p4. On the other hand, a signal s12 is applied to the terminal p6, and a signal 12 is applied to the terminal p5. Note that this signal 12 is a pulse signal with a polarity opposite to that of the signal s12, and is easily generated through an inverting circuit. It is generally known that differential transistor circuits can perform high-speed switching operations.

(4) The current switch 15 is turned off after the pulse width ΔT of the fractional pulse. On the other hand, current switch 1
Since capacitor 4 is also off, the voltage of capacitor 17 is in a hold state. This voltage is received by the buffer amplifier 19 with high input resistance, and after reading this output by the AD converter 20, the FF
11, and return the current switch 14 to the initial state of on and current switch 15 to off. Then prepare for the next measurement. That is, diode 18
is turned on, and the voltage of the capacitor 17 becomes the forward voltage Vd of the diode.

In FIG. 6, if the difference in voltage before and after the capacitor 17 is charged or discharged is ΔV, then
Equation (3) holds true.

ΔV=Vd−(Vd−i ₂・ΔT/C) =Vd−i ₂・ΔT/C (3) In this way, the amount of change in the voltage of the capacitor 17 ΔV
is proportional to the fractional time ΔT. Therefore, by sending the digital output signal of the AD converter 20 to the processor 8, this fractional time ΔT can be calculated.

FIG. 8 is a diagram showing a modification of the present invention. Note that the FF 11 that drives the current switches 14 and 15
etc. are the same as those shown in FIG. 1, so their description is omitted. The difference from FIG. 1 is that a voltage switch using an FET 30 is provided in place of the diode 18 and current switch 14. This FET 30 attempts to discharge the charge stored in the capacitor 17. In this case capacitor 17
Since the potential of is the potential of the source s of the FET 30, the diode 18 shown in FIG. 1 becomes unnecessary. However, the gate signal s that switches FET30
11 typically requires high voltage.

FIG. 9 is a diagram showing another configuration example of the present invention. Note that the current switches 15 and 41 are driven
Since the configuration of FF11 etc. is the same as that shown in FIG. 1, its description is omitted. Moreover, FIG. 10 is a time chart of FIG. 9. The configuration in FIG. 9 differs from the configuration in FIG. 1 as follows: (1) Constant current source 13 always supplies current _i1 .

(2) A constant current source 42 having the same value as the current i ₁ of the constant current source 13 (i ₃ =i ₁ ) and a current switch 41 are newly provided.

The operation of FIG. 9 is as follows. Before the fractional pulse is applied, current switches 15, 41 are off [see Figures 10c and d]. capacitor 17
is the voltage Vd due to the action of the constant current source 13.

When the fractional pulse rises, the current switch 41 is turned on in synchronization with this rising edge. In this case, since the currents of the constant current sources 13 and 41 are i ₁ =i ₃ , the current i ₁ flowing toward the diode 18 is canceled.

In this state, the current switch 15 is turned on with a delay of time τ from the rising edge of the fractional pulse. Therefore, the capacitor 17 is discharged or charged with the current i ₂ and changes as shown in FIG. 10b. This operation is the same as that explained in FIG.

Even though current switch 15 is turned off after a fractional hour, current switch 41 still continues to be on. Therefore, the voltage of capacitor 17 is held.

Hereinafter, since the operation is the same as that explained in FIGS. 1 and 6, the explanation of the operation will be omitted.

When configured as shown in Fig. 9, current switch 1
Since 5 and 41 can be configured with npn transistors, it is possible to achieve even higher speeds and
This has the effect of making IC implementation easier.

Note that the operation of the current switch 41 in FIG. 10 has a completely opposite relationship to the on/off operation of the current switch 14 in FIG. 1 [see FIGS. 6b and 10c].
Therefore, for example, the signal s11 shown in FIG. 1 may be extracted from the terminal of the FF 11 and the current switch 41 may be controlled using this signal.

C. Effects of the Present Invention According to the present invention, since the time/voltage converter is configured with a current switch and a constant current source, high-speed operation is possible. In addition, the initial value voltage is set using a constant current source and a clamping diode, and the current switch is turned off depending on the fractional pulse.
In addition to being capable of high-speed operation, fluctuations in initial value voltage due to leakage current, etc. are eliminated, and stable measurements can be made regardless of the input timing of fractional pulses.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the main part configuration of the present invention, FIG. 2 is a diagram for explaining the operation of the switch section in FIG. 1, and FIG. 3 is a diagram showing a specific configuration example of the switch section in FIG. 1. 4 and 5 are block diagrams showing the overall configuration of the time measuring device according to the present invention, FIG. 6 is a time chart showing the operation of the device shown in FIG. 1, and FIG.
The figure is a time chart showing the overall measurement principle of the present application, Figure 8 is a diagram showing a modification of the present invention, and Figure 9 is a diagram showing a modification of the present invention.
This figure shows another embodiment of the present invention, and FIG. 10 is a time chart showing the operation of FIG. 9. 11...RS flip-flop (FF), 12...
...Delay line, 13, 16, 42... Constant current source, 1
4, 15, 41... Current switch, 17... Capacitor, 18... Diode, 20... AD converter.

Claims (1)

[Claims] 1. Applying a constant current i ₂ to the integrating capacitor 17 for a fractional time period, and using the processor 8 to perform calculations on a digital signal based on the voltage of the capacitor 17 that changes starting from the initial value voltage Vd. A device for measuring the time to be measured, which includes: a clamping diode 18 connected in parallel to the capacitor 17; a current switch 14 that operates during periods other than the fractional time period; A constant current source 13 that applies a current i ₁ to a parallel circuit of a diode 17 and a diode 18 and gives an initial value voltage Vd to a capacitor 17 by the saturation voltage of the diode that is turned on at this time. Device. 2. During the fractional time period, a constant current _i2 is applied to the integrating capacitor 17, and the processor 8 calculates the measured time by adding a calculation to the digital signal based on the voltage of the capacitor 17 that changes from the initial value voltage Vd. In this device, a current _i1 is applied to a clamping diode 18 connected in parallel to the capacitor 17 and a parallel circuit of the capacitor 17 and the diode 18, and the capacitor 17 is initialized by the saturation voltage of the diode that is turned on at this time. A constant current source 13 that provides a value voltage Vd, a constant current source 42 that flows a current _i3 in a direction that cancels the current _i1 that this constant current source 13 flows through the parallel circuit of the capacitor 17 and the diode 18, and this constant current source 42. a current switch 41 that applies a current i ₃ of 1 to the parallel circuit;