JPH0454780A - Picture signal recording and reproducing system - Google Patents

Abstract

PURPOSE:To record information representing a kind of a picture signal without recording of a new information signal by varying a phase of a reference pilot signal recorded on a recording medium together with the picture signal for part of a period in response to the kind of the picture signal to be recorded. CONSTITUTION:A pilot signal fp generated from a synchronizing signal generator 5 and a horizontal synchronizing signal H-SYNC are fed to a pi/2 phase shifter 11, and each of pilot signals whose phase is shifted by pi/2 each in response to the kind of the picture signal outputted from the phase shifter 11 is fed to a switch S. Then the pilot signal outputted from the switch S is fed to a gate circuit 12, the gate circuit 12 passes its input signal for a horizontal and a vertical blanking period according to a composite blanking signal C-BLK fed from the generator 5 and applies each pilot signal to an adder 9 for the period, in which frequency multiplex is implemented for the horizontal and vertical blanking periods of an FM modulation picture element information signal fed from a recording signal processing circuit 10 and the result is fed to a recording amplifier 13. Then the signal outputted from the adder 9 is amplified by the recording amplifier 13 and recorded on a video floppy 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image signal recording and reproducing system that records an image signal on a recording medium and reproduces the image signal recorded on the recording medium.

[Conventional technology]

Conventionally, CCD (Charge Coupled
An electronic still video camera (hereinafter referred to as a floppy camera) has already been commercialized as a system for recording image signals obtained from an image sensor such as a device as a still image signal on a disc-shaped magnetic recording medium (video floppy). .

Images recorded with this floppy camera do not require a developing process like silver halide photography, so they can be viewed immediately by displaying them on a television monitor or making hard copies using a video printer.

By the way, the image quality of images taken with such a floppy camera is compliant with the current television system such as NTSC or PAL, so the vertical resolution is about 500 lines, and the horizontal resolution is about 500 lines. Since it is limited by the number of pixels, even if it is made into a hard copy, the image quality (especially resolution) is insufficient compared to silver halide photography.

Therefore, a still image for one screen is composed of four field images, and the field image signal corresponding to each field image is recorded in a conventional recording format, such as the FM carrier frequency, recording track pattern, etc. when FM modulating the luminance signal. is recorded using the four tracks on the video floppy without changing it, and the four field image signals reproduced from the four tracks on the video floppy are reconstructed using the image memory. A system is being considered in which the still image signal is converted into a still image signal having almost twice the vertical and vertical resolution, and the signal is displayed on a monitor or the like or hard-copied using a video printer.

In other words, as shown in Figure 7, the total number of pixels is 1300x1.
Using an image sensor with 000 pixels, out of the pixels formed on the image sensing surface, only the information stored in the pixels indicated by circles in the figure is read out, and the line Ai shown in FIG. 7 is read out.
The pixel information signals read from Bj, Cj, I] (i is 1, 2, etc.) are sequentially made to correspond to the four tracks (A-D) on the video floppy as shown in Figure 8. During recording and playback, the four tracks on the video floppy shown in FIG. Interpolate the pixel information indicated by the X mark (i.e., the pixel information not recorded on the video floppy) using the pixel information indicated by (i.e., the pixel information recorded and played back on the video floppy). By doing so, a high-definition image with a total number of pixels of 1300 x 1000 pixels is reconstructed on the memory.

FIG. 9 is a diagram showing a schematic configuration of a recording device in an image signal recording and reproducing system that performs recording and reproducing as described above.

In Figure 9, 1300x10 as shown in Figure 7 above.
During recording, an image sensor drive clock is supplied from a synchronization signal generator 52 to an image sensor 51 having an image sensor with a pixel count of 00 pixels. Pixel information corresponding to pixels indicated by circles in the figure is sequentially read out, and after being digitized by an analog-to-digital (A/D) converter 53 operated by a clock signal supplied from a synchronization signal generator 52, A memory 54 is provided.

Note that the writing and reading operations of pixel information in the memory 54 are controlled by a memory controller 55 operated by a clock signal supplied from a synchronizing signal generator 52, and the memory 54 is controlled by a digital clock signal supplied from an A/D converter 53. The converted pixel information signals are sequentially stored, and 1
After the storage of the pixel information signals for the screen is completed, the memory controller 55 first reads out the pixel information data corresponding to the field A formed by the line Ai in FIG. 7 from among the pixel data stored in the memory 54, and A digital-to-analog (D/A) converter 56 is provided.

The D/A converter 56 converts the image information data read from the memory 54 into analog data and supplies it to the adder 57 .

Note that the phase reference signal generator 58 provides a phase reference for the resampling operation performed during reproduction during a period corresponding to the vertical blanking portion of the pixel signal output from the D/A converter 56 according to instructions from the memory controller 55. A phase reference signal is generated, and in said adder 57 a D/A converter 56
The pixel information signal is added to the pixel information signal supplied from the pixel information signal.

The pixel information signal output from the adder 57 is subjected to emphasis processing in the recording signal processing circuit 59, then FM modulated and supplied to the adder 60.

Further, a pilot signal f, which serves as a reference for time axis fluctuation correction processing performed during reproduction, is generated from the pilot signal generator 61 according to instructions from the memory controller 55, and is supplied to the adder 60 from the recording signal processing circuit 59. Frequency multiplexing is performed on the FM modulated pixel information signal.

Note that the pilot signal f is composed of an FM modulated luminance signal and an FM
Approximately 2.5 to 3, which is the valley of the frequency band with the modulated color signal
, 5 MHz, and is frequency multiplexed during the blanking period of the pixel information signal so as not to affect the image quality.

Then, the pilot signal fp output from the adder 60
The FM modulated pixel information signal to which It is recorded on a video floppy 64 that is currently being used.

When the recording of the pixel information signal corresponding to the field A on one track on the video floppy 64 is completed by the above-described recording operation, the magnetic head 63 is moved onto another track by the head moving mechanism, and the magnetic head 63 is moved to the next track. Then, the recording operation of the pixel information signal corresponding to field B constituted by line B1 in FIG. A track pattern as shown in FIG. 8 and FIG. 1θ is formed.

[Problem that the invention is trying to solve]

Incidentally, the above-mentioned recording device is configured to temporarily store the pixel information signal obtained from the imaging section in a memory, read out the pixel information signal stored in the memory, and record it on a video floppy. Therefore, there is no need to worry about the dark current of the image sensor, a single magnetic head is sufficient, and there is no need to move the head at high speed.

Moreover, as mentioned above, the track pattern shown in FIG.
It is possible to record pixel information signals of any field on four tracks on a video floppy, such as the track pattern shown in Figure 0. However, with the above-mentioned device, what kind of track pattern is used to record pixels during recording? Because no identifying information is recorded indicating whether the information signal was recorded,
On the playback device side, it is not possible to determine what kind of track pattern is recorded on the loaded video floppy, and there is a risk that the original high-definition image signal cannot be restored. There was an inconvenience that the pattern could not be selected arbitrarily, but a predetermined track pattern had to be specified.

In addition, in order to record a pixel information signal using an arbitrary track pattern during recording, and to accurately restore the original high-definition image signal on the playback device side, an identification signal is required to identify the track pattern used during recording. It must be added to the pixel information signal, but when a new signal is added in this way, there is a risk that the added signal will adversely affect the image quality.

The present invention was made to solve the above-mentioned problems, and it records an image signal on a recording medium in an arbitrary track pattern without recording a new information signal, and ensures that the original image signal is preserved during playback. The purpose of the present invention is to provide an image signal recording and reproducing system that can restore images.

[Means to solve the problem]

The image signal recording and reproducing system of the present invention records both a reference pilot signal and an image signal on a recording medium during recording, forms a sampling clock that is phase-synchronized with the reference pilot signal reproduced from the recording medium during reproduction, and A system for sampling a reproduced image signal in synchronization with a sampling clock, wherein during recording, the phase of at least a part of a period of a reference pilot signal recorded on a recording medium together with the image signal is determined according to the type of image signal to be recorded. It is changed and recorded accordingly.

[Effect]

With the above configuration, without recording new information signals,
Information indicating the type of image signal can be recorded on the recording medium.

〔Example〕

Hereinafter, the present invention will be explained using examples of the present invention.

FIG. 1 is a diagram showing a schematic configuration of a recording device in an image signal recording and reproducing system as an embodiment of the present invention.

In order to simplify the explanation, a system for recording and reproducing black and white image signals will be described here, but the present invention can also be applied to a system for recording and reproducing color image signals, and the same effects can be obtained. It is.

In FIG. 1, the imaging unit 1 includes a 130 as shown in FIG.
It has an image sensor with a pixel count of 0x1000 pixels, and during recording, a synchronization signal generator transmits only the information stored in the pixels marked with ○ in the figure among the pixels formed on the imaging surface of the image sensor. The data is read out in synchronization with the image sensor driving clock supplied from the synchronization signal generator 5, digitized in the A/D converter 2 in synchronization with the clock signal supplied from the synchronization signal generator 5, and then supplied to the memory 3.

Note that the writing and reading operations of pixel information in the memory 3 are controlled by a memory controller 6 operated by a clock signal supplied from a synchronizing signal generator 5, and the memory 3 is controlled by a digital clock signal supplied from an A/D converter 2. After storing the converted pixel information signals sequentially and completing storage of the pixel information signals for one screen, the memory controller 6 first stores the pixel information signals configured by the lines Ai in FIG. 7 out of the pixel data stored in the memory 3. The pixel information data corresponding to field A is read out and supplied to the D/A converter 4.

The D/A converter 4 converts the image information data read from the memory 3 into analog data and supplies it to the adder 8 .

Note that the phase reference signal generator 7 is connected to the memory controller 6.
During a period corresponding to the vertical blanking portion of the pixel signal output from the D/A converter 4, a phase reference signal is generated which serves as a phase reference for the resampling operation performed during reproduction, and the adder 8 It is added to the pixel information signal supplied from the D/A converter 4.

Then, the pixel information signal output from the adder 8 is added with a composite synchronization signal (C-3YNC) supplied from the synchronization signal generator 5 in the recording signal processing circuit 10, and subjected to emphasis processing. FM modulated, adder 9
is supplied to

Here, the pilot signal f frequency-multiplexed onto the FM-modulated pixel information signal in the adder 9 will be explained.

The pilot signal f and the horizontal synchronization signal H-3YNC generated from the synchronization signal generator 5 are input to the π/2 phase shifter 11, and the horizontal synchronization signal H-3Y is output from the π/2 phase shifter 11.
The pilot signal f, □ (see Fig. 2(b)) synchronized with the falling edge of the NC (see Fig. 2(a)) is output from the output terminal a.
is output from the pilot signal fPa, and the phase is π from the pilot signal fPa.
The pilot signal fPb (see FIG. 2(c)) that is shifted by /2 is output from the output terminal, and the pilot signal f
A pilot signal fPc (see FIG. 2(d)) whose phase is shifted by π from Pa is output from the output terminal C, and a pilot signal fpac whose phase is shifted by 3π/2 from the pilot signals f and □ is outputted from the output terminal C. (see (e)) is the output terminal d
and each pilot signal 'PiL+rpbl fPe output from the π/2 phase shifter 11
t fPd is supplied to switch S.

The switching operation of the switch S is controlled by the memory controller 6, and during the period when pixel information data corresponding to field A is being read from the memory 3 according to instructions from the memory controller 6, the switch S is connected to the a terminal. , a pilot signal fPa is outputted from the switch S, and a pilot signal fPb is outputted from the switch S when reading out a field B corresponding to a readout field of pixel information data read out from the memory 3 according to an instruction from the memory controller 6 as described later. When reading field C, a pilot signal fPc is output, and when reading field D, a pilot signal fPd is output.

The pilot signals fPa, fPゎ+fPet'Pd outputted from the switch S in the manner described above are supplied to the gate circuit 12, and the gate circuit 12 receives the composite blanking signal C- supplied from the synchronization signal generator 5. BLK
The gate is opened during the horizontal and vertical blanking periods according to the pilot signal fP&+ 'Pb+ during this period.
fPet rpa is supplied to an adder 9, frequency-multiplexed during the horizontal and vertical blanking periods of the FM modulated pixel information signal supplied from the recording signal processing circuit 10, and supplied to the recording amplifier 13.

The FM modulated pixel information signal to which the pilot signal is added outputted from the adder 9 is amplified by the recording amplifier 13 and then moved to an arbitrary track on the video floppy 15 by a head moving mechanism (not shown). The data is supplied to a magnetic head 14 and recorded on a video floppy 15 which is rotated by a motor 16.

When the recording of the pixel information signal corresponding to the field A on one track on the video floppy 15 is completed by the above-described recording operation, the magnetic head 14 is moved onto another track by the head moving mechanism, and then the magnetic head 14 is moved onto another track. The pixel information data corresponding to the field B constituted by the line Bi in FIG. 9, the pilot signal fPb is frequency-multiplexed and recorded on the video floppy 15, and similarly, the pilot signal fPe+'Pd is frequency-multiplexed and recorded on the pixel information signals corresponding to fields C and D.

As described above, the pixel information signals corresponding to each field are stored in the four tracks on the video floppy 15 as four types of pilot signals 'Par fP with different phases.
It is recorded with b+'Per fPd added.

FIG. 3 is a diagram showing a schematic configuration of a reproducing device in an image signal recording and reproducing system compatible with the recording device shown in FIG. 1.
The reproduction operation of a video floppy on which a high-definition image signal is recorded in the track pattern shown in the θ diagram will be described.

In FIG. 3, first, the magnetic head 21 is moved by a head moving mechanism (not shown) onto track A (see FIG. 1O) on the video floppy 15 which is being rotated by the motor 16 at a predetermined number of rotations. A reproduction signal reproduced from track A by the magnetic head 21 is supplied to a reproduction amplifier 22.

The playback signal amplified by the playback amplifier 22 is sent to a playback signal processing circuit 23, a PLL (Phase Lock)
dLoop) circuit 27, and is subjected to FM demodulation, de-emphasis processing, amplitude and phase characteristic correction processing, etc. in the reproduced signal processing circuit 23, and then supplied to the A/D converter 24.

On the other hand, P to which the reproduction signal is supplied from the reproduction amplifier 22
The LL circuit 27 separates the pilot signal fP' from the supplied reproduced signal using a band pass filter (BPF), outputs the separated pilot signal fP to the field discrimination circuit 30, and synchronizes the phase with the pilot signal fP'. A sampling clock fs is generated and supplied to the phase shifter 28.

Note that the frequency of the sampling clock fs is the frequency of the pilot signal (, /), which is 195fH (=3.07MHz).

fH is the horizontal synchronization frequency), then 136, which is 7 times that
It is set to 5fH (=21.47MHz).

The field discrimination circuit 30 also receives a horizontal synchronization signal H-SYNC (
4(a)), and the field discrimination circuit 30 receives the horizontal synchronization signal supplied from the synchronization signal separation circuit 29, the pilot signal 1, / supplied from the PLL1 circuit 27, and Based on the phase comparison result, the field type of the image signal recorded on the track on the video floppy 15 that is currently being reproduced by the magnetic head 21 is determined.

That is, as shown in FIG. 4, the horizontal synchronizing signal H-3YNC
(See Figure 4(a)) If the phase difference of the pilot signal fP' with respect to the falling edge is "0", it is determined that the pilot signal recorded on the track currently being played is fP&. Therefore, it is determined that the image signal corresponding to the aforementioned field A is recorded in the track currently being reproduced, and a field discrimination signal F representing field A is sent to the memory controller 31, which will be described later. Output.

By the way, as described above, when the BPF is used to separate the pilot signal in the PLL circuit 27, there is a possibility that a phase difference will occur between the separated pilot signal and the reproduced image signal, but in this embodiment, the reproduced signal In the processing circuit 23, the reproduced image signal is delayed by the time by which the pilot signal is delayed by the BPF, so that no phase difference occurs between the pilot signal and the reproduced image signal.

The sampling clock fs formed by the PLL circuit 27 is phase-synchronized with the reproduced pilot signal (J), so the phase differs for each reproduced track, and the phase shifter 28 adjusts the different phases for each reproduced track. Correct to.

That is, the sampling clock f5' output from the phase shifter 28 is supplied to the A/D converter 24, and the A/D converter 24 converts the reproduced image signal supplied from the reproduced signal processing circuit 23 to the phase shifter 28. The signal is digitized in synchronization with the sampling clock f5' supplied from 28, and is supplied to the memory 25 and phase shifter 28.

The phase shifter 28 extracts and stores the data of the phase reference signal added during recording from the digital image signal supplied from the A/D converter 24, and then extracts the data of the phase reference signal portion added at the time of recording. The A/D converter 24 again digitizes the reproduced image signal using the sampling clock f5' whose phase has been shifted and supplies it to the phase shifter 28.

Then, the phase shifter 28 extracts and stores the data of the phase reference signal part from the digital image signal as described above, and the data of the phase reference signal part extracted from the newly supplied digital image signal. The phase shift amount of the sampling clock f5 is increased or decreased until the level of the newly extracted data becomes the highest, and the data of the phase reference signal portion is extracted. By repeating this operation, the data with the highest level is Once obtained, the memory controller 31 is permitted to write the image data in the memory 25, and the A/D converter 24 sets the phase using the shift amount when the highest level phase reference data was obtained, as described above. The memory controller 31 digitizes the reproduced image signal supplied from the reproduced signal processing circuit 23 in synchronization with the shifted sampling clock fs', and the memory controller 31 converts the digital image signal supplied from the A/D converter 24 into the field. A field discrimination signal F is supplied from the discrimination circuit 30. The information is stored at an address on the memory 25 according to the address.

As described above, the field type of the image signal recorded on track A on the video floppy 15 shown in FIG. 10 is determined by detecting the phase of the pilot signal.
By specifying the write address of the memory 25 according to the field type determined when storing the reproduced image signal in the memory 25, the reproduced image signal can be stored at the correct address on the memory 25 according to the field type. I can remember it.

After the reproduction operation of track A is completed as described above, the magnetic head 21 is moved one track by a head moving mechanism (not shown) so as to come into contact with track C shown in FIG.
The signal stored in track C is reproduced.

Then, by comparing the phase of the pilot signal fP' separated from the reproduced signal in the PLL circuit 27 with the horizontal synchronizing signal in the field discrimination circuit 30 in the same way as described above, the image signal recorded on the track C is Determine the type of field that is present.

At this time, as shown in Figure 4, the horizontal synchronizing signal H-5YNC
(see FIG. 4(a)), the pilot signal f.

Assuming that the phase difference of It is determined that the image signal corresponding to the above-mentioned field C is recorded in the track C currently being played,
Memory 2 of reproduced image signals by memory controller 31
5, the memory 25 corresponding to field C
, and the reproduced image signal is stored.

Hereinafter, track B shown in FIG. 10 is similar to the above.

D, and the recorded pilot signal is fPb(
As shown in Fig. 4(d), the phase difference is π/2 (90°) with respect to the horizontal synchronizing signal H-5YNC shown in Fig. 4(a), or fpa (as shown in Fig. 4(e)). As shown in Fig. 4(a), the phase difference is 3π/2 with respect to the horizontal synchronizing signal H-5YNC.
(=270°)), it is determined whether the image signal recorded on the track corresponds to field B or field D, and the memory controller 31 stores the reproduced image signal. 25, the write address to the memory 25 corresponding to field B or D is specified, and the reproduced image signal is stored.

As mentioned above, the reproduced image signals reproduced from the four tracks on the video floppy 15 are stored at an address on the memory 25 corresponding to the pixel arrangement of the image sensor in the image pickup section l of the recording apparatus shown in FIG. After being stored, the memory controller 31 gives an instruction to the interpolation processing circuit 33, and the interpolation processing circuit 33 records the data of the pixels (marked with an x in FIG. 7) that are not recorded on the video camera 25. Perform interpolation processing using the data of the pixels (marked with ○ in Figure 7),
High-definition image data of 1300x1000 pixels is formed on the memory 25.

After the interpolation processing operation is completed as described above, the memory controller 31 reads out the image data stored in the memory 25 in accordance with the accurate tarok signal supplied from the read clock generator 32, and reads out the image data stored in the memory 25. By converting to analog in the A converter 26, the output terminal 3
4 outputs a high-definition image signal.

As explained above, in this embodiment, the pilot signal, which is recorded together with the image signal during recording and serves as the reference for the time axis correction processing performed during playback, is changed in phase for each recorded track to create a video floppy disk. By recording on the video floppy, the playback side can determine the type of field to which the image signal recorded with the pilot signal corresponds by determining the phase of the pilot signal reproduced from the video floppy. It is possible to detect the recording pattern of tracks recorded on a video floppy without recording information signals, and it becomes possible to reliably record and reproduce high-definition image signals.

Furthermore, in the embodiment shown in FIG. 1, the phase of the pilot signal recorded on the video floppy together with the image signal is changed for every period of each track, but it is changed only during a predetermined part of each track. You may also do so.

For example, as shown in FIG. 5, a signal obtained by inverting the phase of a pilot signal f generated by the synchronizing signal generator 5 by an inverter 72 and a signal without inverting the phase are supplied to the switch S1, and the memory controller 71 The image shows a pilot signal obtained by performing a different control operation for each track when controlling the switching operation of the switch S1 in synchronization with the horizontal synchronization signal H-5YNC generated by the synchronization signal generator 5. The recording pattern of the track recorded on the video floppy may be detected by recording the signal together with the pilot signal and detecting the state of change in the phase of the pilot signal on the reproduction side.

As an example of controlling the switch SI in the above embodiment,
For example, if the phase is inverted with respect to the original pilot signal, it is "1", and if it is not inverted, it is "0", and during the horizontal blanking period of 2H in total immediately before and after the recording start position of each track. If the phase of the pilot signal multiplexed to the field is changed for each track, the image signal corresponding to field A will be "0" and "0" (see Fig. 6).
a)), “0” and “1” for the image signal corresponding to field B (see Fig. 6 (b)), and “]” and “0” for the image signal corresponding to field C (see Fig. 6 (b)). (
(see Figure 6(d)) for the image signal corresponding to field D, and by monitoring the phase of the pilot signal in this part during playback, the field of the image signal is You will be able to distinguish between the types.

〔Effect of the invention〕

As explained above, according to the present invention, an image signal can be recorded on a recording medium in an arbitrary track pattern without recording a new information signal, and the original image signal can be reliably restored during playback. It is possible to provide an image signal recording and reproducing system that can perform

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a schematic configuration of a recording device in an image signal recording and reproducing system as an embodiment of the present invention. FIG. 2 is a diagram showing the phase relationship between each pilot signal added to an image signal and a horizontal synchronization signal in the apparatus shown in FIG. 1. FIG. 3 is a diagram showing a schematic configuration of a reproducing device in an image signal recording and reproducing system compatible with the recording device shown in FIG. 1. FIG. 4 is a diagram showing the phase relationship between each pilot signal separated from the reproduced signal and the horizontal synchronization signal in the apparatus shown in FIG. 3. FIG. 5 is a diagram showing a schematic configuration of a recording device in an image signal recording/reproducing system as another embodiment of the present invention. FIG. 6 is a diagram showing the phase relationship between a partial period of each pilot signal added to an image signal and a horizontal synchronization signal in the apparatus shown in FIG. 5. FIG. 7 is a diagram showing the arrangement of pixels sampled in the image sensor and recorded on the recording medium. FIGS. 8 and 10 are diagrams showing track patterns formed on a video floppy. FIG. 9 is a diagram showing a schematic configuration of a recording device in a conventional image signal recording and reproducing system. 1... Imaging unit 2... A/D converter 3... Memory 4... D/A converter 5... Synchronization signal generator 6... Memory controller 11... π/2 Phase shifter 12...Gate circuit S...Switch Fig. 2 (b) (c) (d) (e) pa pb pc pd] “Downstream” “Ge”0′ “1” “1” “Ge”1” “0” “1”

Claims (1)

[Claims] A reference pilot signal and an image signal are both recorded on a recording medium during recording, and a sampling clock that is phase-synchronized with the reference pilot signal reproduced from the recording medium during reproduction is formed and synchronized with the sampling clock. A system for sampling a reproduced image signal, the system comprising: changing the phase of at least a part of a period of a reference pilot signal recorded on a recording medium together with the image signal at the time of recording according to the type of image signal to be recorded; An image signal recording and reproducing system characterized by recording.