JPH0454552A - Access system for dual port memory - Google Patents

Abstract

PURPOSE:To eliminate the change of the data stored in a dual port memory when these data are read out by always enabling the memory to have an access to a single CPU only. CONSTITUTION:A main CPU 1 and a sub-CPU 2 are connected to an arbitration circuit 3 via an address bus and a data bus respectively. The circuit 3 is connected to a common RAM 4 serving as a dual port memory via the address and data buses, and the RAM 4 is provided with an access flag which decides the access right to the RAM 4 between the CPU 1 or the CPU 2. Thus only the CPU 1 or 2 to which the access right is granted by the access flag can have an access to the dual port memory 4 and the other CPU is unable to have any access to the memory 4. As a result, the read-out data are never changed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a dual port memory access method [Prior Art] Conventionally, when a common dual port memory is used between two CPUs, the dual port Each CPU's access to memory is performed without any coordination with each other.

[Problem to be solved by the invention]

Therefore, conventionally, when two CPLIs access a common dual port RAM, one CPLI
When U is writing to the dual-port RAM, a situation arises in which the other CPLI tries to read the same location that the one CPU is writing to, and there is a risk that the read data may change in this case. There was an inconvenience.

An object of the present invention is to provide a dual-port memory access method that eliminates such inconveniences.

[Means to solve the problem]

In order to achieve this object, the present invention provides an access flag in the dual port memory, and allows a CPU to which access rights are set to this access flag among a plurality of CPUs to access the memory. The CPU is configured to update the access flag after the access is completed so that other CPUs have access rights. In addition to this configuration, an arbitration circuit is provided, and when multiple CPUs access the same location of the memory at the same time, the arbitration circuit determines the The CPU may be configured to select a bus on the side of a CPU that has a priority right, and give access rights to the CPU that has a priority right and is connected via this bus.

[For production]

One CPU granted access rights by access flag
Only one CPU can access the dual-port memory, and during this access, no other CPU can access the memory. Furthermore, in the case where an arbitration circuit is provided, when multiple CPUs simultaneously access the same location in the memory, the arbitration circuit selects the bus on the CPU side that has predetermined priority. Accordingly, the CPU with the priority right is given the access right regardless of the setting state of the access right in the access flag. In this way, only one CPLI will have access to memory at any given time. and,
After the CPU completes the access, the CPU updates the access flag to set access rights to other CPUs.

〔Example〕

Hereinafter, a preferred embodiment of the present invention will be described in detail based on the accompanying drawings. Here, FIG. 1 is a schematic block diagram showing the overall configuration, FIG. 2 is a flowchart showing the access operation of the main CPU, and FIG. 3 is a flowchart showing the access operation of the sub CPU.

As shown in Figure 1, the main CPU1 and sub CPLI2
are connected to the arbitration circuit 3 via an address bus and a data bus, respectively. The arbitration circuit 3 is connected to a common RAM 4, which is a dual port memory, via an address bus and a data bus, and also includes:
The common RAM 4 is provided with an access flag. The access flag is used to set which of the main CPUI and the sub CPL 12 has the right to access the common RAM 4.

Furthermore, when the main CPU 2 and the sub CPU 2 access the same location of the common RAM 4 at the same time, the arbitration circuit 3 determines the setting state of the access right in the access flag, that is, which CPU Regardless of whether the access right of the sub CPU 2 is set or not, by selecting the bus of the sub CPU 2 and making it valid, the request of the sub CPU 2 is accepted and the request of the main CPU 2 is canceled. has been done. In this way, in this embodiment, sub-C
PU2 has priority.

Next, based on Figure 2, the common RAM of the main CPU
The access operation for 4 will be explained.

First, read the access right setting status in the access flag of the common RAM 4 (step 1), the main C
It is determined whether the PUI has the access right to the common RAM 4 (steps 1 and 2). If it is determined that the PUI does not have the access right, the process returns to step 101, and step 10
In step 2, the device is in a standby state until it is determined that it has access rights.

On the other hand, if it is determined in step 102 that there is an access right, the main CPL 11 proceeds to step 103 to access the common RAM 4 and read or write predetermined data. When the access is completed, the main CPU 2 sets the access right of the sub CPU 2 in the access flag (Step 104), and then reads out the setting state of the access right of the access flag (Step 105), and the sub CPU 2 sets the access right of the sub CPU 2 in the access flag (Step 105). It is checked whether access is possible (step 106).

Here, if it is determined that the CPU 2 does not have the access right, the process returns to step 104 and the above-described operation is repeated again, while if it is determined in the step 106 that the sub CPU 2 has the access right, the operation ends.

Next, the access operation of the sub CPU 2 to the common RAM 4 will be explained based on FIG.

First, the access right setting state in the access flag of the common RAM 4 is read out (step 201), and the sub C
It is determined whether the PU 2 has the access right to the common RAM 4 (step 202). If it is determined that the PU 2 does not have the access right, the process returns to step 201, and step 20
In step 2, the device is in a standby state until it is determined that it has access rights.

On the other hand, if it is determined in step 202 that there is an access right, the process proceeds to step 203, where the sub CPL 12 accesses the common RAM 4, reads predetermined data,
Alternatively, when the sub CPU 2 finishes accessing the common RAM 4 for writing, the sub CPU 2
U2 sets the access right of the main CPUI in the access flag (step 204), and ends the operation.

Here, if the same location of the common RAM 4 is accessed from the main CPL II and the sub CPU 2 at the same time,
Regardless of the setting state of the access right in the access flag, the sub-CPU that has priority rights according to the arbitration circuit 3
Two buses are selected and made valid, and the sub CPU2
The request from the main CPUI is accepted, and the request from the main CPUI is canceled. Then, the main CPUI enters a standby state until the access by the sub CPU 2 is completed and the access right of the main CPUI is set in the access flag of the common RAM 4.

In this way, only either the main CPU I or the sub CPU 2 can access the common RAM 4 at any time.

Note that the present invention is not limited to the above-mentioned embodiments, and for example,
Main CPU1 and sub CPU at the same location of common RAM4
When accesses are made from two CPUs at the same time, priority may be given to the main CPU, and the number of CPUs is not limited to two, but may be three or more.

〔effect〕

As is clear from the above explanation, according to the present invention, the dual port memory is configured so that only one CPU can access it at any time.
When a CPU is writing to memory, other CPUs will not read the same location that is being written to.
This has the effect that there is no fear that the data stored in the memory will change when read.

[Brief explanation of drawings]

The figures show a preferred embodiment of the present invention, in which Fig. 1 is a schematic block diagram showing the overall configuration, Fig. 2 is a flowchart showing the access operation of the main CPU, and the third leap is a sub-CPU.
3 is a flowchart showing the access operation of FIG. l...Main CPU 2...Sub CPU
3...Arbitration circuit 4...Common RM

Claims (2)

[Claims] (1) An access flag is provided in the dual port memory, so that one of the plurality of CPUs for which access rights are set in the access flag can access the memory, and the CPU that has accessed the memory can access the memory after the access is completed. A dual port memory access method characterized in that a flag is updated so that other CPUs have access rights. (2) An access flag is provided in the dual port memory, so that a CPU among the plurality of CPUs for which access rights are set in the access flag can access the memory, and the CPU that has accessed the memory can access the memory after the access is completed. While the flag is updated so that other CPUs have access rights, an arbitration circuit is provided to set the access rights in the access flag when multiple CPUs access the same location of the memory at the same time. A dual port memory access system characterized in that the arbitration circuit is configured to give access rights to a CPU with predetermined priority regardless of the state.