JPH0454052A - Clock fault evading method - Google Patents

Abstract

PURPOSE:To minimize speech interruption as small as possible by selecting automatically an internal clock when a clock from a clock distributer is interrupted. CONSTITUTION:An output of an output clock interruption detection circuit 15 is inputted to a selection circuit 21 selecting a clock and the changeover between an external clock from a PLO and an internal clock from an oscillator 23 is implemented automatically. The output of the output clock interruption detection circuit 15 is inputted to a state display register SR, in which a relevant bit is set and enters the selection circuit 21 via a buffer 31 to make clock changeover. Thus, the clock is switched automatically by using the output from the output clock interruption detection circuit 15 in this way, only momentary interruption is caused in the clock and much remarkable fault is not caused to talking or the like.

Description

[Detailed Description of the Invention] [Summary of the Invention] Regarding a method for avoiding clock failure in a telephone exchange, the present invention relates to a method for avoiding clock failure in a telephone exchange, which automates switching to shorten the clock interruption period as much as possible.
In order to avoid failures, it takes in a clock from the outside and generates a clock synchronized with it, also generates a clock internally, and uses a selection circuit to take in the external clock to the main body network when the external clock is normal. In a method for avoiding a clock failure in a telephone exchange that imports the internal clock into the main network when the external clock is disconnected, the output of the external clock disconnection detection circuit is input to the selection circuit, and when the external clock is disconnected, the clock is automatically switched to the internal clock. Configure it like this.

[Industrial application field]

The present invention relates to a method for avoiding clock failures in telephone exchanges.

Telephone exchanges use clocks in their networks, and there are two types of clocks: one is supplied externally, and the other is generated by each exchange. In the former case, the clock may not be supplied from the outside (clock cutoff) and the exchange may not operate normally, but the present invention relates to a method for avoiding this failure.

[Conventional technology]

There are asynchronous systems and synchronous systems in telephone exchanges.
The former uses free-running oscillation to distribute and supply clocks to the network, while the latter receives clocks from a clock distribution device, performs network synchronization, and distributes and supplies clocks to the network. The latter method is shown in FIGS. 4 and 5.

Figure 4 shows a duplex system, with digital trunk trunks (DTK) A and B currently in use.

This is a DTK for backup (0 series, 1 series) lines. A receiving circuit RFC and a transmitting (distribution) circuit DRV are connected to this, and a selection circuit SEL selects the O-system and 1-system receiving circuits and extracts the clock component. Phase synchronized oscillation circuit PL
O generates an internal clock that is phase-synchronized with the external clock output by the selection circuit SEL, and this is supplied to the network as a frame clock and a clock via a counter 14 and an output clock disconnection detection circuit 15.

This clock device has a status display register SR and a control register CR, and the former includes a bit that is sent at the output of the output clock disconnection detection circuit 15, a bit that is sent at the output of the PLO asynchronous detection circuit 13, and a bit that is sent at the output of the PLO asynchronous detection circuit 13, as shown in the figure. Bits set by the output of the 0-system human connection/disconnection detection circuit, bits sent by the output of the 1-system human connection/disconnection detection circuit, bits indicating whether the 0-system and 1-system cables are installed/uninstalled, and switches It has a total of 7 bits of pinpoint (turns on when manually switching the input clock) at the output of IN.

The processor reads the contents of the status display register SR and sets the required control bits in the control register CR. The control focus of this control register CR becomes alarm 8LM via OR gate G, and select circuit SE
It is used for switching L, status INO, i lamp lighting, and asynchronous reset.

On the network side, as shown in Figure 5, the crystal oscillator 2
3. The clock from the clock device shown in FIG. 4, which has a counter 24 and a timing generation circuit 25 and is received via the reception circuit 22, and the frame clock;
The selection circuit 21 selects either the clock from the timing generation circuit 25 or the frame clock. The output of the selection circuit 21 is directly connected to the counter 2 in the network.
6 and further via a timing generation circuit 27 for use as various timing pulses.

[Problem to be solved by the invention]

In this conventional device, when the external clock (from the clock distribution device) is cut off, the supervisor who notices this operates a switch to change over the selection circuit 21, and when the clock is normal, the clock is taken in from the clock device shown in FIG. 4. The current clock is switched to the clock from its own crystal oscillator 23. At this time, a bit to that effect (bit due to IN) is set in the status display register SR in Fig. 4, and the processor sees this and sets the corresponding bit (■■ focus) in the control register CR, and the selection circuit SEL is set. Switching between O system and 1 system is performed. If the external clock becomes normal now, the supervisor operates the selection circuit 2I again to take in the external clock to the network.

If the system is not a duplex system, of course the switching between the 0 system and the l system is not performed, but only the selection circuit 21 is operated to switch the external clock to the internal clock.

In such a clock switching by a supervisor, it takes time (there is a delay of several minutes) from clock disconnection to switching, and during that time, calls, etc. are interrupted.

The present invention aims to improve these points, automate the switching, shorten the clock interruption period as much as possible, and avoid failures.

[Means to solve the problem]

As shown in FIG.
The internal clock from the oscillator 23 is automatically switched from the external clock from the PLO to the internal clock from the oscillator 23.

As in all figures, the same parts as in other figures are given the same reference numerals. The output of the output clock disconnection detection circuit 15 is input to the status display register SR to set the corresponding bit, and is also input to the selection circuit 21 via the buffer 31 to perform clock switching.

[For production]

In this way, if the clock switching is automatically performed using the output of the output clock disconnection detection circuit 15, a disconnection of 0.7 will be a momentary interruption, and will not cause any significant trouble to telephone calls or the like.

When the clock is switched internally, it is no longer phase-synchronized with the external clock, but digital communication becomes impossible unless the clock is switched. However, analog communication within the premises is possible, and failures can be limited to as few conditions as possible.

If a redundant system is used, system switching is also performed, so it is possible to take in the external clock from a healthy system. In this case, after a momentary interruption due to system switching, both analog and digital systems can communicate. can return to normal state.

〔Example〕

Embodiments of the present invention are shown in FIGS. 2 and 3. Selection circuit 21
performs clock switching in response to a signal TGSEL (timing/generation selection signal) from the clock device shown in FIG. 2, and the signal TGSEL is enabled by the output of the output clock cutoff detection circuit 15. outputs.

As is known, the phase synchronized oscillation circuit PLO consists of a VCO1 frequency divider and a phase comparator, and oscillates a clock synchronized with the master clock. Also, if the mask clock is disconnected, it will self-oscillate.

The PLO asynchronous detection circuit 13 is a phase synchronization oscillation circuit PLO
Detects the phase difference between the input/output clocks of the input clock, and detects the out-of-synchronization of the output clock with respect to the input clock, and sets the corresponding bit in the status display register SR. It is also reset by the asynchronous reset bit of the control register CR, and restores the asynchronous detection bit of the status display register SR.

The status display register SR collects various fault information, key information, and cable connection information and notifies the microprocessor.

〔Effect of the invention〕

As described above, according to the present invention, when the clock from the clock distribution device is cut off, the clock is automatically switched to the internal clock, so that the call cut-off can be kept to the user's time as much as possible. In addition, if it is a duplex system, it is possible to immediately switch to the standby system, eliminate the clock interruption, and restore normality to both the digital system and the analog system.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIGS. 2 and 3 are diagrams showing an embodiment of the invention, and FIGS. 4 and 5 are diagrams showing a conventional example. In FIG. 1, 21 is an internal/external clock selection circuit, and 15 is an external clock disconnection detection circuit.

Claims (1)

[Claims] 1. Takes in a clock from the outside and generates a clock synchronized with it, also generates a clock internally, and selects a selection circuit (
21), when the external clock is normal, the external clock is taken into the main body network, and when the external clock is disconnected, the internal clock is taken into the main body network. A method for avoiding clock failures, characterized in that input is input to the selection circuit to automatically switch to an internal clock when the external clock is cut off. 2. Take in a clock from the outside, generate a clock synchronized with it, generate a clock internally, and select the selection circuit (
21), when the external clock is normal, the external clock is taken into the main body network, and when the external clock is disconnected, the internal clock is taken into the main body network, and the 0 system/1 system is switched. In the fault avoidance method, the output of the external clock disconnection detection circuit (15) is input to the selection circuit and the 0 system/1 system selection circuit, and when the external clock is disconnected, the output is automatically switched to the internal clock and the 0 system/1 system is switched off. A clock failure avoidance method characterized by automatically switching one system.