KR19990056020A - Network Synchronous Clock Control Method in Private Switching System - Google Patents

Abstract

end. The technical field to which the invention described in the claims belongs

How to Control the Synchronous Clock in Private Switching Systems

I. The technical problem that the invention is trying to solve

In order to provide smooth service between nodes in private switching system, if the designated synchronization clock fails, the system reference clock is changed to another normal synchronization clock immediately.

All. Summary of the Solution of the Invention

In the private switching system, the clock is automatically changed by using the holdover mode of the clock controller without resetting the digital link unit in the case of clock failure, and the process of storing the presence or absence of selection of a synchronization source to change the network synchronizer is performed.

la. Important uses of the invention

Even if the designated synchronous clock fails in a private switching system, it is quickly changed to another synchronous clock, which is convenient for network management and maintenance.

Description

How to Control the Synchronous Clock in Private Switching Systems

The present invention relates to a method for controlling a network synchronizer clock of a private exchange which is connected and operated with a large power system, and more particularly, to a method for quickly changing a reference clock in case of failure of a reference clock for smooth service of a system.

In general, a private switching system composed of multiple nodes has a number of synchronous clock sources for inter-node synchronizers, and selects a normal clock among synchronous clock sources supplied to the system and uses it as a reference clock for the inter-node synchronizers. . The synchronous clock source that can be used as a reference clock can be a digital trunk (E1, T1, PRI) connected to the public network.In case of a slave node in a private switching network composed of multiple nodes, an internal node used for inter-node connection Inter Node Interface It can be a digital card.

A method of changing a network synchronizer clock when a current reference clock fails in a conventional private switching system will be described with reference to FIG. The conventional private switching system is supplied with four synchronization clock sources CK1 to CK4, and one of the normal clocks is selected as a reference clock to synchronize the system. In the case of a failure of the current synchronous clock source in the conventional private switching system, the synchronous clock of the system is immediately changed to the next normal synchronous clock to prevent a fatal effect of the system due to the clock failure. For example, when the system (master node) currently connected to the large station selects the first synchronous clock source CK1 as the reference clock, the synchronization of the entire system through the digital link unit 115, 121 connecting the master node and the slave node to the synchronous clock source CK1. To match. At this time, if a failure occurs in the first synchronous clock source CK1 selected as the reference clock, if the second synchronous clock source CK2 is normal, the reference clock is immediately changed to the second synchronous clock source CK2. If a failure occurs in the second synchronous clock source CK2, the reference clock is sequentially changed to a normal synchronous clock source by the third and fourth synchronous clock sources CK3 and CK4. The slave node 120 receives a reference clock from the digital link unit 115 of the master node 110 through the digital link unit 121 and synchronizes with the reference clock. However, in the slave node 120, which receives the reference clock from the master node 110 and synchronizes with the reference clock from the master node, when the currently selected synchronization fails, the clock is immediately changed to the next synchronization source like the master node 110. Instead, the digital link unit 121 of the corresponding node is reset to select the synchronous clock again. This is because the slave node 120 resets the digital link unit 121, which supplies the inter-node link and the clock, to re-select the synchronous clock of the changed master node 110 to prevent the clock from shaking due to the clock failure.

As such, the method of resetting the digital link unit 121 in the case of a clock failure in the slave node 120 is unnecessary due to the holdover function of providing the system clock to the stable clock immediately before the clock controller 122 when a clock change occurs. However, when talking with a subscriber of the master node 110, the call is disconnected momentarily due to the reset by the above method, and data may be lost between nodes, causing many problems. In addition, there is a problem in that a link failure occurs between nodes during the time when the slave node 120 resets the digital link unit 121 and selects a reference clock again. In addition, when the digital link unit 121 is reset at the slave node 120, since the configured synchronous clock is always selected, the next normal clock cannot be sequentially selected in the event of a clock failure.

Accordingly, an object of the present invention is to provide a method for quickly changing a synchronous clock when a failure of a selected reference clock occurs in a private switching system.

Another object of the present invention is to provide a method for immediately switching to a normal synchronous clock source by using a holdover function when a reference clock fails in a private switching system.

It is still another object of the present invention to provide a method of changing a reference clock without resetting a digital link unit of a slave node in a private exchange system.

It is still another object of the present invention to provide a method of immediately switching to a normal synchronous clock source without resetting a digital link unit of a slave node when a reference clock is changed in a private switching system.

Still another object of the present invention is to provide a method of changing a reference clock such that a call and data loss between nodes does not occur even if a failure of the reference clock occurs in the private exchange system.

Another object of the present invention is to provide a method for stably changing a plurality of synchronous clock sources in a private switching system.

It is still another object of the present invention to provide a method of accurately storing a state of a plurality of synchronous clock sources in a private switching system to select an accurate reference clock even when a clock is changed.

The present invention for achieving the above object is a method for changing the network clock of the private exchanger operating in connection with the power system, which provides a continuous smooth service without affecting the system even if the reference clock of the current system fails. It is characterized by.

1 is a block diagram for changing a network synchronizer clock in a conventional private switching system.

Figure 2 is a block diagram for selecting and distributing a network synchronizer clock in a private switching system according to the present invention.

3 is a register for storing states of four manipulator sources in a private exchange system in accordance with an embodiment of the present invention.

4 is a diagram illustrating a method of changing a schematic reference clock of a private exchange system according to an embodiment of the present invention.

5A and 5B illustrate a process of changing a network synchronizer reference clock in a private exchange system according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are used as much as possible even if displayed on different drawings. In addition, in the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The private exchange system according to the present invention is configured as shown in FIG.

Referring to FIG. 2, the private switching system according to the present invention includes a digital trunk 210, a clock controller 220, a diagnostic processor 230, a digital link unit 240, a signal processor module 250, and a line processor module 260. The digital trunk 210 receives a clock from a power station or a master node, and the clock controller 220 controls the state of the input synchronization clock and the reference clock. The diagnostic processor 230 receives a state of the input synchronization clock from the digital trunk 210 to select a system reference clock, and the digital link unit 240 distributes the selected reference clock to other nodes.

First, a method of extracting 8 KHz for use as a reference clock in a private exchange system according to an embodiment of the present invention will be described. A private switching system according to a specific embodiment of the present invention may configure up to four synchronization clocks for a network synchronizer, using a normal one of the synchronization clocks as a reference clock for the network synchronizer, and using the reference clock. By distributing to slave nodes, it is controlled to be used for the synchronizer of the connected private switching network. In addition, the digital f-link unit 240 that can be used as a synchronous clock source may use E1, T1, PRI, INI, etc., and only up to four may be used as the system synchronous clock. For example, if there are eight E1 trunks in the system, only four of these trunks can be used as synchronous clocks, and the configuration of the digital trunk you select can be changed to a database for network synchronization.

First, the digital trunk 210 monitors a clock state provided from a power station or a master node supplying a reference clock, and transmits the clock signal to the clock controller 220. In addition, the digital trunk 210 transmits the input clock state information to the diagnostic processor 230 through the line processor module 260. Accordingly, when the digital trunk 210 is configured with four digital trunks, which can be selected by the system, the digital trunk 210 transmits four clock signals and information on status to the clock controller 220 and the diagnostic processor 230, respectively. The diagnostic processor 230 analyzes the clock state information transmitted from each synchronization source and selects a clock of the synchronization source at a normal and high hardware priority as a reference clock. In addition, the diagnostic processor 230 writes the information about the selected clock into a reference clock selection register as shown in FIG. 3 in the clock controller 220. Referring to FIG. 3, the reference clock selection register is configured to indicate whether or not up to four synchronization clocks are selected, bit by bit, and is set (1) or reset (0) to a bit corresponding to a selected clock position. It is supposed to record. Accordingly, the clock control unit 220 selects only the corresponding clock by referring to the information of the register and controls it to be supplied to the reference clock of the whole system, and continuously monitors and controls the state of the clock. In this way, the selected synchronous clock is distributed to the slave system and the selected synchronous clock to the slave node, so that the entire system matches the network with the synchronous clock extracted from the power, so that smooth service is achieved.

On the other hand, when a failure occurs in the currently selected synchronous clock, the diagnostic processor 230 may have a fatal effect on the system, and immediately change the reference clock to another clock. In the private switching system according to the embodiment of the present invention, the method for changing the network synchronizer clock changes the reference clock according to hardware priorities as shown in FIG. Referring to FIG. 4, when a reference clock of a current system is referred to as a first reference clock in a private switching system according to an exemplary embodiment of the present disclosure, if a failure occurs in the reference clock during system operation, information about the failure may be stored in the digital trunk unit. From the 210 to the diagnostic processor 230 through the line processor module 260. Therefore, the diagnostic processor 230 resets the state of the failed synchronization clock. That is, the diagnostic processor 230 resets the synchronous clock select bit recorded in the reference clock register of the clock controller 220. In addition, the diagnostic processor 230 transmits information to block the clock supplied from the failed digital trunk to the line processor module 260 so as to prevent the failed clock from being used as the system reference clock. In addition, the diagnostic processor 230 checks the states of the second to fourth reference clocks and selects the clock having the highest priority in hardware as the reference clock among the normal clocks as shown in FIG. 4. The diagnostic processor 230 sets a selection bit of the selected reference clock on the reference clock selection register of the clock controller 220 and transmits information to the line processor module 260 to supply a clock from the corresponding digital trunk. For example, when the second to fourth clocks are all normal, the second clock is selected as the reference clock because the hardware priority of the second clock is high. In addition, when the current reference clock is the second clock, the diagnostic processor 230 selects the first clock as the reference clock of the system when all other clocks are normal. As such, the private switching system according to the embodiment of the present invention automatically changes the network synchronizer clock according to the hardware priority even if the current reference clock fails.

Meanwhile, when the reference clock is changed, the clock controller 220 may control the holdover mode function to prevent the clock phase from shaking. The holdover mode function is to provide a stable clock immediately before a failure by storing a normal clock immediately before a failure occurs in the currently selected clock. The clock controller 220 resets all of the reference clock selection registers as shown in FIG. 3 to perform the holdover mode. Therefore, the slave node does not need to use the conventional change method of resetting the digital link unit to select the manipulator again due to the shaking of the clock which may occur when changing the clock. In other words, the stability of the system can be increased by providing a function of selecting the next normal clock immediately after the register is reset using the holdover function.

The method of changing the network synchronizer reference clock of the private switching system according to the embodiment of the present invention is performed by the steps as shown in FIG.

2 to 5, a method of changing the network reference clock of the private switching system according to the embodiment of the present invention will be described. If a failure occurs in the currently selected reference clock, the digital link unit 210 transmits the status information message to the diagnostic processor 230. Accordingly, when receiving the message transmitted from the digital link unit 210 in step 511, the diagnostic processor 230 analyzes the received message in step 512. In operation 513, the diagnosis processor 230 determines whether the received message is a message for notifying occurrence of a failure of the reference clock. If the received message is not a message for notifying that a clock failure has occurred, the diagnostic processor 230 performs an operation corresponding to the received message in step 514. For example, when the received message is a clock recovery message, the diagnostic processor 230 performs a control operation for clock recovery. In contrast, when the received message is a message for notifying the occurrence of a clock failure, the diagnostic processor 230 determines whether the message is for notifying the occurrence of a failure for the current reference clock in step 515. If the received message is a message for notifying occurrence of a failure with respect to the current reference clock, the diagnostic processor 230 transmits a clock block message to the clock source (digital trunk) where the failure occurs in step 516. In operation 517, the diagnostic processor 230 resets a bit corresponding to the failed clock to the reference clock select register in the clock controller 220. In operation 518, the diagnosis processor 230 determines whether a normal clock source exists. If it is not a failure message for the current reference clock or if there is no other normal clock source when the failure of the current reference clock in step 519, the diagnostic processor 230 sends a clock block message to the blocked clock source (digital trunk). Send. In operation 520, the diagnostic processor 230 resets a bit corresponding to a clock source having a failure in the reference clock select register in the clock controller 220, and performs a holdover mode in operation 521.

In contrast, if there is a normal synchronization clock source, the diagnostic processor 230 performs a control operation from operation 522 to operation 529 to select a reference clock according to hardware priority. According to the above steps, the synchronization clock with the highest hardware rank can be selected as the changed new reference clock. If there is a normal synchronization clock source, the diagnostic processor 230 determines whether the fourth clock is normal in operation 522. If the fourth clock is normal, the diagnostic processor 230 changes the fourth clock to the reference clock in step 523.

In contrast, when the fourth clock is not normal, in operation 524, the diagnostic processor 230 determines whether the third clock is normal. If the third clock is normal, the diagnostic processor 230 changes the third clock to a reference clock in step 525.

In contrast, when the third clock is not normal, the diagnostic processor 230 determines whether the second clock is normal in step 526. If the second clock is normal, the diagnostic processor 230 changes the second clock to a reference clock in step 527.

In contrast, when the second clock is not normal, the diagnostic processor 230 determines whether the first clock is normal in step 528. If the first clock is normal, the diagnostic processor 230 changes the first clock to a reference clock in step 529.

In operation 530, the diagnostic processor 230 transmits a clock recovery message to the changed clock source, and sets the bit of the changed clock in the reference clock selection register of the clock controller 220 in operation 531.

For example, if the first clock, which is the current reference clock, fails to change the reference clock, it is determined whether another synchronization source is normal, and the clock having the highest hardware priority is selected as the reference clock. Therefore, the diagnostic processor 230 transmits a clock recovery message to the digital trunk 210 supplying the changed reference clock and receives the clock from the digital trunk. In addition, the diagnostic processor 230 sets a bit of the clock in the reference clock select register of the clock controller 220 and sets the clock controller 220 to a normal mode. As such, the diagnostic processor 230 controls the network of the system with the changed reference clock so as to stably change the clock without affecting the system due to the clock failure.

As described above, the present invention can provide a continuous smooth service even when a clock failure occurs in a private switching system by preventing a fatal effect of the system. In addition, the present invention does not reset the digital link unit when the clock is changed by using the holdover mode in the private switching system, and instantaneous call disconnection and message loss that may occur by immediately changing the reference clock to the next normal clock. It can improve the stability of the system by solving the problem. In addition, the present invention accurately manages the state information of the maximum synchronous clock that can be used in the private switching system and reflects the register in the register to compensate for the instability of the clock due to the mismatch of the synchronization control between the hardware and the software, thereby improving system reliability. There is an effect to increase.

Claims (6)

In the network synchronization clock control method of a private switching system that is connected and operated with a power station, Receiving a message corresponding to a state of a plurality of clocks supplied from the connected station, and setting one of the plurality of clocks as a reference clock; Determining whether a failure occurs in the clock set as the reference clock; And receiving a message corresponding to a state of a clock other than the failed clock to change a reference clock to a normal clock. The method of claim 1, And a holdover mode in the process of changing the reference clock. The method of claim 1, And controlling the selection of the clock in a register during the change of the reference clock. In the network synchronization clock control method of a private switching system that is connected and operated with a power station, A first process of receiving a message corresponding to a state of a plurality of clocks supplied from the connected power station; A second step of determining whether a failure occurs in the clock set as the current reference clock by the message transmitted in the first step; A third step of determining whether a clock other than the clock determined to have a failure in the second step is normal; And a fourth process of changing a clock determined as a normal clock in the third process to a reference clock. The method of claim 4, wherein And a reference clock is changed according to the hardware priority of the plurality of clocks in the fourth process. The method of claim 4, wherein And a hold over function when the reference clock is changed in the fourth process.