JPH04531A - Orthogonal transformation arithmetic unit - Google Patents

Abstract

PURPOSE:To simplify the constitution of a comuting element and to reduce the capaity of a ROM by specifying the address to a memory device and replacing row and column addresses while matching with the execution of operation of an one-dimensional orthogonal transformer. CONSTITUTION:At the time of writing, an address is applied so as to be advanced in a row direction and the calculated result of an one-dimensional discrete cosine transformation (DCT) computing element 4 is written in accor dance with a row direction address in a memory device 2. At the time of read ing, the switching circuit 18 in an address generator is switched to switch a row address to a column address. Thereby, address specification in the memory device 2 is changed to the order of the column direction and the data of the device 2 are read out to the computing element 6. At the end of the address reading, the reading mode is changed to the writing mode again and the circuit 18 is switched so that addresses are advanced in the row direction again. Thus, DCT operation is repeated.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention is used in digital still video cameras, facsimile machines, color copies, video telephones, etc., and is used to perform discrete cosine transform ( The present invention relates to an arithmetic unit that performs orthogonal transformation such as DCT (hereinafter referred to as DCT or DCT transformation) and discrete sine transformation (hereinafter referred to as DST or DST transformation).

(Conventional technique $1) DCT is one of the transform encoding methods for information compression.
Orthogonal transform operations such as , and DST are known.

FIG. 14 shows an example in which data compression is performed through DCT processing.

The image information read by the CCD reading element 150 is
The D converter 152 converts the signal into a digital signal, and one screen's worth is temporarily stored in the frame memory 154. The data in the frame memory 154 is subjected to DCT processing by the DCT processing circuit 156.
converted, quantized in a quantization circuit 158, Huffman transformed in a Huffman encoding circuit 8160, and stored in a memory device 162.
is memorized. When the data stored in the memory device 162 is reproduced as an image, the Huffman decoding circuit 16
4, and after passing through the dequantization circuit 166, I
The data is returned to image data by the DCT circuit 168, converted to an analog signal by the D/A converter 170, and output.

To explain the case where an image is divided into blocks consisting of (N
)Vπ/2N)-=-(1) When Ll=0 C(U)
=17f2 When U≠0 C(υ)=1 When v=o C(V) = 1/fi ■ When ≠O
C(V)=1 f(x+j) is pixel data.

In the two-dimensional DCT calculation, after performing the one-dimensional DCT calculation on j, the one-dimensional DCT calculation may be performed on i as well. When the one-dimensional DCT calculation formula is converted into a vector calculation formula for the case of N=8, the following formula (2) is obtained.

here, α=cos(2/8)π β = cos (1/8n π δ=sin(1/8)π λ=eos (1/16)π μ=sin (3/16)π γ=cos(3/16) π ν=sin (1/16)π It is.

When image compression processing is performed after DCT operation, the decompression operation that returns the compressed image to its original data requires IDCT operation (Inverse DC), which is the inverse operation of DCT operation.
T operation) is performed. The IDCT operation can be expressed as the following formula.

・cos((2j+1)Vπ/2N) ・−・(3)U
When =O C(U) = 1/, /"iU≠0 When C(U)=1 ■=0 When C(■)=1/J'''2■≠0
To perform the dimensional IDCT operation on C(V)=, after performing the one-dimensional IDCT operation on ■, it is sufficient to perform the one-dimensional IDCT operation on U as well, and the -dimensional IDCT operation can be expressed as a vector calculation formula as shown in equation (4) below. It is expressed as

When attempting to calculate the vector calculation formulas of equations (2) and (4), it is necessary to multiply the conversion coefficient by data X or 2.

As shown in FIG. 15, a two-dimensional DCT calculator that executes equation (1) applies a transformation matrix 132 of transformation coefficients W(1,j) to an original image 130 composed of (NXN) pixels.
Perform the convolution operation by multiplying by the coefficient 4 C(
By multiplying U)C(V)/N2, the converted pixel F(
U, V) are obtained.

When this operation is executed using multipliers and adders, as shown in FIG. 16, N2 multipliers 36-1 to 36-N2,
N2-bit adder 138 and coefficient 4 C(U)C(V
)/N'' is required.

There is a ROM lookup table method that uses a ROM table instead of a multiplier to perform the multiplication. For example, if you want to perform vector calculation using equation (2), as shown in FIG. 17, prepare a ROM 102 that holds data corresponding to the product of each conversion coefficient and input data, ROM 1 with input data as address
All you have to do is read out 02. 104 is an address generator. Conversion coefficient data and input data are each input to address generator 104 in multiple bits.

(Problem to be Solved by the Invention) A one-dimensional DCT operation for image compression and a one-dimensional IDCT operation for expansion thereof, for example,
If it is divided into blocks each consisting of pixels, it is necessary to perform 64 multiplications and 56 additions. Therefore,
Since the DCT processing time and IDCT processing time become longer and the circuit scale becomes larger, it becomes difficult to integrate the method into an integrated circuit.

Even when a DST operation is performed instead of a DCT operation as an orthogonal transformation, the same problem arises in that the processing time is long and the scale of one circuit is large.

In the ROM lookup table method, when the input data is n bits and the number of types of conversion coefficients is m, the ROM
The address space of IO2 is mX2''.
Applying this to the case of DCT transformation of
Assume that the conversion coefficients are fixed at 8 types, and the input data consists of 8 8-bit pixels, so n = 64 and the address space is 8 x 2''.Achieving such a large capacity That is difficult.

SUMMARY OF THE INVENTION An object of the present invention is to simplify the configuration of a DCT computing unit or a DST computing unit so that it can be integrated into an integrated circuit.

An object of the present invention is to reduce the capacity of the ROM when implementing orthogonal transform operations such as DCT using the ROM lookup table method.

(Means for solving problems) The present invention will be explained with reference to FIG. 1 showing an embodiment.

The present invention includes a one-dimensional orthogonal transform computing unit 4 such as a first one-dimensional DCT computing unit, and a memory device 2 for temporarily storing the output thereof.
and a second one-dimensional DC whose input is the output of the memory device 2.
A one-dimensional orthogonal transformation arithmetic unit 6 such as a T arithmetic unit, and an address generator 8 that specifies addresses of the memory device 2 and exchanges row addresses and column addresses in accordance with switching between write and read operations of the memory device 2. We are prepared.

10 is an address decoder, and 12 is a read/write control section.

In order to operate at high speed, as shown in FIG.
The one-dimensional orthogonal transform calculator 4 and the second one-dimensional orthogonal transform calculator 6 are connected to both memory devices i2 a via switch circuits 20 and 22, respectively.

2b, and when the first one-dimensional orthogonal transformation computing unit 4 is connected to one memory device 2a (or 2b), the second one-dimensional orthogonal transformation computing unit 6 connects to the other memory device 2b (or 2a). ) to be connected to the changeover switch circuit 20.2
2.

In the present invention, the address generator 8 in FIG. The read/write control unit 12 performs an operation of exchanging the row address and column address, and after reading one piece of data in the memory device 2, writes the first data at the same address.
It is also possible to perform an operation of writing a new calculation result of the one-dimensional orthogonal transformation calculation unit 4.

The present invention also provides a preprocessing circuit that performs addition and subtraction between input data so that some of the coefficients become O during orthogonal transformation processing that performs discrete cosine transformation or discrete sine transformation, and the orthogonal transformation processing circuit The data added or subtracted by the preprocessing circuit may be multiplied by a non-zero coefficient and the multiplication results may be added.

The present invention further performs orthogonal transformation using a ROM lookup table method using a ROM table, using each bit of input data and multiple bits of conversion coefficient data as addresses, and data read from the ROM table at the address. It is also possible to add all bits of the input image data by shifting in the upper or lower direction depending on the bit position in the input data.

In addition, in the present invention, in the ROM lookup table method, a preprocessing circuit is provided before the orthogonal transformation circuit to perform addition and subtraction between input data so that a part of the transformation coefficient becomes O during orthogonal transformation processing. You may prepare.

(Operation) In the present invention, two-dimensional orthogonal transformation calculations are realized by a set of one-dimensional orthogonal transformation calculation units. Divide the image into blocks consisting of (NxN) pixels and apply two-dimensional DCT to each block.
The case of conversion will be explained.

I have already mentioned that the two-dimensional DCT operation is expressed by a formula (1)
It becomes a ceremony.

Transforming equation (1), ・cos((2i+1)Uπ/2N) = (2C(U)/N)ΣF(i,V) ・cos((
2i+1)Uπ/2N) (5) Prize F(i, V) = (2C(V)/N)Σf (i, j
)cos((2j+1)V π/2N) ・−・
(6) J=0. Here, equation (5) is -dimension D of F (i, V)
Expression (6) represents a -dimensional DCT operation of f (IIj). Therefore, a two-dimensional DCT operation with N taps (N By doing so, the result of the two-dimensional DCT operation can be obtained.

In FIG. 1, the first one-dimensional DCT calculator 4 writes data in the row or column direction of the memory device 2, and the second one-dimensional DCT calculator 6 reads the data in the column or row direction.
Perform CT calculation.

The above is an explanation of compression, but decompression, which is the reverse operation, can be processed in a similar manner by simply changing the conversion formula.

Two-dimensional ID CT (Inverse DCT)
) operation can be expressed as an equation (3) already mentioned.

・cos((2i+1)lx/2N). Here, equation (7) is the -dimension ■D of f(V,i)
Expression (8) represents the CT calculation, and the - of F (U, V)
Represents a dimensional IDCT operation. Therefore, the N tap (N By doing so, the result of the two-dimensional IDCT operation can be obtained.

The same applies when DST transformation is used as the orthogonal transformation calculation.

When performing an (8x8) DCT operation according to the present invention, there are 8 types of conversion coefficients, and 1 bit of each pixel is operated on 8-pixel input data, so n = 8,
The required address space is 8×28. With this scale, it becomes possible to implement a semiconductor integrated circuit.

Furthermore, if we perform preprocessing using the symmetry of the transformation coefficient matrix so that some of the transformation coefficients become O, we can obtain 4
Since it is only necessary to calculate one bit of each pixel with respect to the input data of the pixels, n=4, and the required address space is reduced to 8×24, which further facilitates implementation.

The preprocessing circuit performs the following calculations.

A case will be described in which an image is divided into blocks composed of (8×8) pixels and each block is subjected to one-dimensional DCT transformation. The preprocessing circuit receives input data Xo, X0 . ”””X
7 to CX2+X5)t CX2+X5)t(X10Xl
, )+ (X3+X4)+ (XOX7L(X2-
x, ), (xl-x6), (xa-x4). In order to use the data converted by the preprocessing circuit as a variable (
2) Expressing the DCT conversion formula of Eq.

The following equation (9) is obtained.

In the decompression process, the calculation formula for the IDCT operation is the following formula (10).

here a = cos(1/4)π b=cos(1/8)x d = sin (1/8) 7C e = cos(1/16)π f = cos (3/16) x g”5in (1/16)π h = sin (3/16) yt It is.

According to equation (9), half of the conversion coefficients are O.

There is no need to perform multiplication for the portion where the coefficient is O.

After IDCT operation according to formula (10), (xo +
7L (X2+XS) l (xx” xs) +
(X3+X4) * (Xo Xv') t (
Xz Xs) +(x, -xG), (x3x4
) as X,, xl, ”'x.

Perform post-processing to return to normal.

(Example) FIG. 1 represents one embodiment.

2 is a transport memory device, which is an N×N word RAM. If N is 8, it has a capacity of 64 words. 4 and 6 are one-dimensional DCT computing units,
N pieces of each are provided. If the unit block in which the DCT operation is performed is (8×8) pixels, then N is 8. - To specify the address for writing the calculation result of the dimensional DCT calculation unit 4 to the memory device 2, and to specify the address for reading the data written to the memory device 2 to the one-dimensional DC, T calculation unit 6, An address generator 8 is provided. If the memory device 2 has 64 words, a 6-bit address is generated from the address generator 8 as the address. 1o inputs the address and memory device 2
This is an address decoder that specifies addresses. 12
is a read/write control unit for controlling writing and reading in the memory device 2;

An example of the address generator 8 is shown in FIG.

Two 3-pint counters 14 and 16 are provided to generate a 6-bit address, and the 6-bit address is constructed by combining the 3-bit outputs of each. From the counter 14, 3 of (AO, Al, A2)
The address of the bit is output, and the counter 16 outputs (A
3. A4. It is assumed that the 3-bit address of A5) is output. These 3-bit addresses are combined to form a 6-bit address. Reference numeral 18 is a switch circuit that switches the address combination of 3 bits at a time. When this switch circuit 18 is switched to one side, the address becomes (AO, Al, A2.A3°A4.A5), and when switched to the other side, the address becomes (A3°A4). .A5.AO, Al, A
2). The relationship between these switched addresses corresponds to the row address and column address in the memory device 2 being switched. The switch circuit 18 is switched in conjunction with read/write operations. When writing, the address is switched so that it advances in the row direction, and when reading, it is switched so that it advances in the column direction. Or, conversely, when writing, the address is switched so that it advances in the column direction, and when reading, it is switched so that it advances in the row direction.

Next, the operation of this embodiment will be explained with reference to FIGS. 3 and 4.

FIG. 3 represents addresses in the memory device 2. When writing, the addresses advance in the row direction, i.e. (0, O), (1, O), (2°0), (3, O),
It is assumed that addresses are given so as to proceed in the order of (N-1, N-1).

As a result, the calculation results of the one-dimensional DCT calculation unit 4 are written into the memory device 2 according to the addresses in the row direction. This is what is written as shown by the dashed arrow in FIG.

Next, the operating mode changes to read and the switch circuit 18 of the address generator is switched to switch between row and column addresses. As a result, addressing in the memory device N2 is performed in the column direction (0, O), (0°1), (0,2), (0,3), as shown by the solid line in FIG.
, , -(N-1°N-1), and the data in the memory device 2 is read out to the one-dimensional DCT calculator 6.

When reading to (N-1, N-1) address is completed,
The write mode is changed again, and the address is switched to advance in the row direction again. In this way, the DCT calculation is repeated.

Writing in the memory device 2 may be performed in the column direction, and reading may be performed in the row direction.

In another embodiment, the read/write control unit 12 transfers data at a specified address to the one-dimensional DCT calculator 6 at a low level of one cycle of the clock CK at a specified address, as shown in FIG. Control is performed so that the calculation result of the one-dimensional DCT calculation unit 4 is read and written to the same address during the high level period of the cycle.

Next, the operation of this embodiment will be explained with reference to FIGS. 3 and 6.

First, for example, the addresses advance in the row direction, that is, (0, O), (L O), (2゜○), (3
,○), . . . (N-1, N-1). This allows one-dimensional DCT
The calculation results of the calculation unit 4 are written into the memory device 2 according to the addresses in the row direction.

This is what is written as shown by the dashed arrow in FIG.

Next, the switch circuit 18 of the address generator is switched to switch between row and column addresses. As a result, the address specification in the memory device 2 is (0,
O), (0,1), (0°2), (0,3),...
...The order changes to (N-1, N-1). First, (0,
The data at address 0) is read to the one-dimensional DCT calculator 6, and then the calculation result of the one-dimensional DCT calculator 4 is written as data to the same address (0, O).

Next, the memory address changes to (0, 1), and -dimensional DC
The T calculation unit 6 reads the data at that address, and then the calculation result of the one-dimensional DCT calculation unit 4 is written as data to the (0, 1) address. The column direction arrow shown as a solid line in FIG. 6 represents the direction of the first read operation, and the column direction arrow at 1 point m and W+ represents the direction of the second write operation. When this operation is repeated and executed up to memory address (N-1, N-1), the row address and column address of the memory address are switched again, and this time the data is processed by the one-dimensional DCT operator 6 along the row direction. One-dimensional DCT operator 4 to the same address following reading
The writing of the operation results from (N-1, N-1) is executed.

FIG. 7 shows yet another embodiment.

In this embodiment, a pair of transport memory devices 2a and 2b made of RAM are provided. 20 is a switch circuit that switches and connects the one-dimensional DCT calculator 4 to the memory devices 2a and 2b, and 22 is a switch circuit that switches and connects the one-dimensional DCT calculator 6 to the memory devices 2a and 2b.

Although not shown, an address generator, an address decoder, and a read/write control section are connected to the memory devices f2a and f2b as in FIG. 1.

The operation of the embodiment shown in FIG. 7 will be explained.

When the switch circuits 20 and 22 are in the state shown.

In the memory device 2a, the calculation results of the one-dimensional DCT calculator 4 are written in the row direction, and the -dimensional DCT calculator 6 reads out the data written in the memory device 2b in the column direction. Writing to memory device 2a, memory device 2b
When reading is completed, the switch circuits 20 and 22 are switched. This time, the calculation results of the one-dimensional DCT calculator 4 are written to the memory device 2b in the row direction, and the -dimensional DC
The T calculator 6 reads data written in the memory device 2a in the column direction. In this way, one memory device is writing while the other memory device is simultaneously reading. This is repeated while switching the switch circuits 20 and 22.

In FIG. 7, two-dimensional DCT calculation can be performed at twice the speed compared to FIG. 1.

An apparatus for sequentially performing the first one-dimensional DCT operation and the second one-dimensional DCT operation will be explained with reference to FIGS. 8 and 9.

FIG. 8 explains the principle.

First, as shown in (A), the row direction transformation coefficient wi(
j ) (=cos((2j+1)Vπ/2N)), add them in the row direction, and perform a row-dimensional DCT operation by multiplying them by a coefficient 2C(V)/N to convert the row-direction transformed pixel F(i, V), and in the (i+1)th cycle, F(i+1.V) is similarly computed.

When the row direction-dimensional DCT operation of N cycles is completed, the column direction-dimensional DCT operation is started, and as shown in (B), the pixel (U, V )
column direction transformation coefficient wv(i)(=cos((2i+1
) Uπ/2N)) and add them in the column direction, and multiplying by the coefficient 2C(U)/N to calculate the converted pixel F(U, V).

FIG. 9 represents an apparatus for carrying out this embodiment.

Pixels in one row of the original image f(i, O), f(i, 1)...
pixel (U) for each f(i, N-1).

■) In order to multiply by the row direction transformation coefficient wi(j), N
Multipliers 54-1 to 54-N are provided. 56
is an adder that adds the calculation results of those multipliers 54-1 to 54-N, and 58 adds a coefficient 2 to the added result.
This is a multiplier that multiplies C(V)/N. As a result, a one-dimensional DCT operation in the row direction is performed.

Next, N multipliers 62-1 to 62-N are provided to perform one-dimensional DCT calculation in the column direction. Selector switches 60-1 to 60-N are provided between the multiplier 58 and the multipliers 62-1 to 62-N, respectively, and the corresponding selector switches are selectively turned on depending on the row position i. Conversion coefficient w in each multiplier 62-1 to 62-N
v(0) to wv(N-1) are multiplied. 64 is an adder that adds the multiplication results by the multipliers 62-1 to 62-N, and 66 is a multiplier that multiplies the addition result by a coefficient 2C(U)/N. U,
V) is calculated.

FIG. 10 shows an embodiment equipped with a preprocessing circuit, and shows, as an example, a case where an image is divided into blocks of (8×8) pixels and a DCT operation is performed.

32-O to 32-7 are input data X, respectively.

This is a shift register and latch circuit that increments and holds x7 at the timing of clock CLOCK1. 34-
1 to 34-4 are shift register and latch circuits 32-0
This is an addition/subtraction circuit that takes in two predetermined data held in 32-7 and performs addition or subtraction according to a select signal. 36-1~36-4.38-1~38-
Reference numeral 4 denotes a shift register and a latch circuit that increments and holds the data calculated by the addition/subtraction circuits 34-1 to 34-4 at the timing of clock CLOCK2.

40 is a DCT processing circuit, in which coefficients a and b are used to perform multiplication and addition expressed by equation (9).

It holds dr 8'+ fy gv h and is equipped with a multiplier for performing 32 multiplications and an adder for performing 31 additions.

The arithmetic device that performs the IDCT calculation also has a similar circuit configuration.

The arithmetic device that performs the DST calculation and the ID5T calculation also has a similar configuration.

FIG. 11 shows a one-dimensional DCT operation in the DCT conversion device of the embodiment using the ROM look-up table method, and shows a ROM look-up table circuit corresponding to one multiplication.

Reference numeral 76 denotes an address generator, into which multi-bit conversion coefficient data and 1-bit input data are input as addresses. If there are, for example, eight types of conversion coefficients, the conversion coefficient data is 3-bit data. The input data is the largest bit (LSB) or the smallest bit (MSB).
) are input one bit at a time. 78 is a ROM that holds data. When the input data is 411 I+, the conversion coefficient data is used as the address of the ROM 78, and when the input data is "0", 0 is used as the address of the ROM 78. 80 is an adder, 82 is a register that temporarily holds data from the adder 80, and 84 is a register that stores data from the register 82 in the upper direction when input data is input from the largest bit. This is a 1-bit shifter that shifts the bit position of the data held in the register 82 in the lower direction when input data is input from the smallest bit.

The data shifted by 1 bit in the upper or lower direction by the 1-bit shifter 84 and the data from the ROM 78 are added to the adder 8o.

Assuming that the input data is input bit by bit starting from the largest bit, first, the ROM 78 is accessed using the 1-bit input data of the largest bit n and the conversion coefficient data as the address of the ROM 78 to obtain data Dn. Data Dn is held in register 82 via adder 80.

What is held in the register 82 is output. next,
The 1st bit data of the (n-1)th bit of the input data and the conversion coefficient data are stored in the ROM 7 as the address of the ROM 78.
8 is accessed, and data Dn-□ is output from the ROM 78. The adder 80 adds this data Dn-0 to the data shifted by 1 bit in the upper direction by the 1-bit shifter 84 in order to double the data D in the register 82, and the added value is held in the register 82. and the output is updated.

The final output is obtained by repeating this operation until the input data has the minimum bits.

In this case, the capacity of the ROM 78 is the number of types of conversion coefficients m(
In this example, it is 8).

FIG. 12 shows an example of a DCT processing circuit when performing one-dimensional DCT calculation expressed by equation (2).

86 is a shift register to which one line of data including 8 pixels expressed in 8 bits is sent; 88 is a shift register for each pixel X of 8 bits. - This is a latch that holds Xt. 90 is a DCT processing circuit using the ROM lookup table method, and each DCT processing circuit 90 includes eight circuits shown in FIG. 1 and an adder for adding the outputs of these eight circuits. It is. Each DCT processing circuit 90 receives input data X. -x7 is input one bit at a time starting from the largest bit (or starting from the smallest bit), and although not shown in the figure, conversion coefficient data is also input to perform the calculation shown in FIG. 11. The output of each DCT processing circuit 90 is 8-bit output data 2°-77.

92 is a shift register, which sequentially arranges and outputs 2o-27.

In FIG. 12, the ROM capacity required to obtain output data of 2°-77 is 8×28.

FIG. 13 shows an embodiment for performing the calculation expressed by equation (9) using the symmetry of DCT conversion coefficients in order to further reduce the capacity of the ROM table.

Shift register 88 and DCT processing circuit 90a.

A preprocessing circuit 94 is provided between 90b.

The preprocessing circuit 94 rearranges the transformation coefficient matrix as shown in equation (9), half of which becomes 0, and outputs z,, z2
．． In the four DcT processing circuits 90a that obtain z, , zG, the latter four transform coefficients are 0, so input data for multiplying by these 0 is no longer necessary, and the four DCT processing circuits 90a
The processing circuit 90a has input data (XO+Xt) r
(Xt + X6) t (xz + Xs) r(
Four bits, one bit each, are input from (X3+X4). Output Z-work, Z3. Get ZS, Z, 4
In the four DCT processing circuits 90b, the first four transform coefficients are 0, so the input data for multiplying by these 0s is no longer required, and the four DCT processing circuits 90b receive the input data (xO- X 7 ) r (X 1xt,) +
Four bits, one bit each, from (X2 Xi) l (X3 X4) are input. Each DCT processing circuit 90a, 90b includes four circuits shown in FIG.
and an adder that adds the outputs of those four circuits.

In FIG. 13, the ROM capacity required to obtain the output data of zI, to z7 is reduced to 8×24.

(Effects of the Invention) According to the present invention, if the two-dimensional orthogonal transform operation is realized by one set of one-dimensional orthogonal transform operators, the number of required multipliers is 1. For example, if the unit of the orthogonal transform operation is a block of (8×8) pixels, Therefore, while the conventional method requires 64 multipliers, the present invention requires only 8+8=16 multipliers, which simplifies the device and allows it to be integrated into an integrated circuit. Become.

In addition, in a memory device that temporarily stores the calculation results of the first one-dimensional DCT calculation unit, data written in the row direction is read out in the column direction, new data is written in the column direction, and data written in the column direction is read out in the column direction. If addressing and read/write control is performed to read data in the row direction and write new data in the row direction, the required capacity of the memory device is (N One word block will be enough. As a result, the memory capacity can be reduced and high-speed operation can be performed.

By forming a pair of memory devices and writing to one memory device and reading from the other memory device at the same time, high-speed operation becomes possible.

If a pre-processing circuit for input data is provided to set some coefficients to 0 in two-dimensional DCT calculations or two-dimensional DST calculations, the number of multipliers and adders in the DCT processing circuit or DST processing circuit will be reduced. Processing speed becomes faster.

In addition, the circuit size becomes smaller and it becomes easier to integrate the circuit.

By using input data bit by bit as an address when implementing the orthogonal transformation process using the ROM lookup table method, the orthogonal transformation process can be realized with a small ROM capacity.

By providing a preprocessing circuit that utilizes the symmetry of the transform coefficients and setting some of the transform coefficients to 0, the ROM capacity can be further reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment, FIG. 2 is a block diagram showing an example of an address generator in the same embodiment, and FIG.
The figure shows the address of the memory device in the same embodiment,
FIG. 4 is a timing diagram showing the addressing method of a memory device showing the operation of the same embodiment; FIG. 5 is a timing diagram showing the operation of the read/write control section of another embodiment; and FIG. 6 is the same embodiment. a diagram illustrating the addressing method of a memory device showing the operation of the
FIG. 7 is a block diagram showing still another embodiment, FIG. 8 is a diagram showing the concept of calculation in still another embodiment, FIG. 9 is a circuit diagram of the same embodiment, and FIG. 10 is a block diagram showing still another embodiment. FIG. 11 is a block diagram showing a portion corresponding to one multiplier of the ROM lookup table method in another embodiment, and FIGS. 12 and 13 are respectively in the embodiment. FIG. 2 is a block diagram showing a DCT calculation device. Fig. 14 is a block diagram showing a data compression/decompression system, Fig. 15 is a conceptual diagram showing a conventional two-dimensional DCT operation, Fig. 16 is a circuit diagram of the conventional example, and Fig. 17 is a ROM look using the conventional method. FIG. 3 is a block diagram showing a portion corresponding to one multiplier in the up-table method. 2.2a, 2b... Memory device, 4, 6...
. . .-dimensional DCT computing unit, 8 . . . address generator, 12 . . . read/write control unit, 14.
16...3-bit counter, 18, 20.22...
...changeover switch circuit, 32-O~32-7...
...Shift register and latch circuit, 34-1 to 3
4-4... Addition/subtraction circuit, 36-1 to 36-4
, 38-1 to 38-4...shift register and latch circuit, 40...-dimensional DCT processing circuit,
76...address generator, 78...
...ROM, 80... Adder, 82...
Register, 84...1 bit shifter, 86...
...Shift register, 88...Latch, 90
, 90a, 90b...DC, T processing circuit using ROM lookup table method.

Claims (6)

[Claims] (1) A first one-dimensional orthogonal transformation computing unit, a memory device that temporarily stores the output thereof, a second one-dimensional orthogonal transformation computing unit that receives the output of the memory device as input, and address specification of the memory device. An orthogonal transformation arithmetic device comprising: an address generator that performs the above operations and interchanges row addresses and column addresses in accordance with switching between write and read operations of the memory device. (2) a first one-dimensional orthogonal transformation computing unit, a memory device that temporarily stores the output thereof, a second one-dimensional orthogonal transformation computing unit that receives the output of the memory device as input, and address specification of the memory device and an address generator that exchanges the row address and column address in accordance with the execution of the calculations of the first and second one-dimensional orthogonal transform calculation units; An orthogonal transformation calculation device, comprising: a read/write control unit that writes a new calculation result of the first one-dimensional orthogonal transformation calculation unit. (3) A pair of the memory devices are provided, and a first one-dimensional orthogonal transform arithmetic unit and a second one-dimensional orthogonal transform arithmetic unit are respectively connected to the two memory devices via changeover switch circuits. The orthogonal transformation according to claim 1, wherein the changeover switch circuit is switched so that when the original orthogonal transformation computing unit is connected to one memory device, the second one-dimensional orthogonal transformation computing unit is connected to the other memory device. Computing device. (4) In an orthogonal transform calculation device equipped with an orthogonal transform processing circuit that performs discrete cosine transform or discrete sine transform, addition and subtraction are performed between input data so that some of the coefficients become 0 during orthogonal transform processing. An orthogonal transform calculation device comprising a preprocessing circuit, wherein the orthogonal transform processing circuit multiplies the data added or subtracted by the preprocessing circuit by a non-zero coefficient and adds the multiplication results. (5) In an orthogonal transform calculation device equipped with an orthogonal transform circuit that divides one image into blocks each including a plurality of pixels and performs orthogonal transform processing for each block, the orthogonal transform circuit performs a ROM lookup process using a ROM table. It performs calculations using the up-table method, where each bit of input data and multiple bits of conversion coefficient data are used as addresses, and the data read from the ROM table is sorted according to the bit position in the input data at that address. Alternatively, an orthogonal transform arithmetic device comprising an adder circuit that shifts in the lower direction and adds all bits of input data. (6) A preprocessing circuit according to claim 6, further comprising a preprocessing circuit that performs addition and subtraction between input data so that some of the transform coefficients become 0 during the orthogonal transform process, at a stage before the orthogonal transform circuit. Orthogonal transformation calculation device.