JPH0453150B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a teletext multiplex signal receiving device that receives a teletext multiplex signal sent using a television signal.

[Technical Background of the Invention and Problems thereof] A system has been developed that utilizes the vertical blanking period of a television signal to transmit so-called character multiplex signals such as pattern signals and code signals. The character multiplex signal in this system is superimposed on the vertical blanking period of the video signal as a binary digital signal with a clock frequency f(ck)=5.727272 MHz. Therefore, a receiving device that receives this character multiplexed signal must reproduce a sampling clock that is synchronized with the transmission clock and sample the transmitted data using this sampling clock.

Here, the sampling clock regeneration circuit is important for accurately sampling the transmitted data, and conventionally a circuit as shown in FIG. 1 has been used. A video signal containing a video-detected text multiplex signal is applied to input terminal 11. The video signal is input to a color signal subcarrier regeneration circuit 12 and also to a clock run-in signal extraction circuit 14. In the color signal subcarrier regeneration circuit 12,
Color signal subcarrier [f
sc=3.57945MHz] and converts it into a phase-locked loop circuit (hereinafter referred to as PLL circuit) 13.
Enter. In the PLL circuit 13, the transmission clock frequency [f(ck)
=(8/5)f sc]. The output is then input to the variable phase shifter 16.

On the other hand, the clock line signal extracted by the clock line signal extraction circuit 14 is sent to the phase determination circuit 15.
is input. This phase determination circuit 15 determines the phase difference between the output of the variable phase shifter 16 and the clock run-in signal. Then, based on the determination output of the phase determination circuit 15, the variable phase shifter 16
The amount of phase shift is controlled. As a result, a sampling clock synchronized with the transmission clock can be obtained from the variable phase shifter 16.

In the field of television technology, digital television receivers have been developed that quantize and process the video signals they handle. In this type of digital circuit, a frequency of 4×f sc is used as the quantization sampling frequency. Here, the quantization sampling frequency 4×f sc in the digital television receiver and the sampling clock frequency [f(ck)
=(8/5)f sc], the two do not have a simple integer relationship. Therefore, when a digital television receiver is intended to receive a character multiplex signal, it is necessary to separately provide a dedicated sampling clock reproducing circuit as shown in FIG.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and provides a sampling clock for receiving a character multiplex signal with a simple configuration in a circuit that processes a quantized digital television signal. It is an object of the present invention to provide a receiving device for a teletext signal that can be obtained.

[Summary of the Invention] In the present invention, as shown in FIG.
sc) From the digital data series sampled every second {f sc = 3.579545MHz}, by interpolation method,
Create a pseudo data series with an interval of T×1/2. Next, the data series at intervals of T×1/2 are sampled every five times by latch circuits 281 to 285. As a result, data sequences sampled at 5/(8f sc) intervals of five types of phases are obtained. And judgment circuit 3
0, the data with the closest phase to the clock run-in signal is selected.

[Embodiments of the Invention] Examples of the present invention will be described below with reference to the drawings.

FIG. 4 shows an embodiment of the present invention, in which an analog video signal including a character multiplex signal is input to the input terminal 21. This video signal is an analog
In addition to being added to the digital conversion circuit 24,
The signal is input to an oscillator 22 that generates an oscillation signal of xf sc [f sc = subcarrier frequency]. This oscillator 22 is a synchronous oscillator that oscillates in phase synchronization with the burst signal. The output of this oscillator 22 is 1/2
The frequency divider 23 converts the signal into a frequency of 4×f sc and it is applied to the analog-to-digital conversion circuit 24 as a quantized sampling signal. As a result, a quantized digital video signal is obtained from the analog-to-digital conversion circuit 24.

This digital video signal is input to an interpolation data generation circuit 25, a gate switch 26, and a timing setting circuit 27.

The interpolation data generation circuit 25 includes a plurality of delay elements.
DL1, DL2, DL3...DLn are connected in series,
The input terminal of the delay element DL1 and the output terminal of each delay element are respectively connected to coefficient setting circuits K1, K2, K3...
It is connected to the adder circuit 251 via Kn+1. Here, the output of the oscillator 22 is used as the drive clock for the interpolation data generation circuit 25. Further, this interpolation data generation circuit 25 is an acyclic filter having a tap interval of period T=1/(8f sc) [sec]. Assume now that the input signal at the terminal 21 is 4A, and its quantization is performed at timings t1, t2, t3, . . . in FIG. It is also assumed that the output terminal of the delay element DL2 is an intermediate tap. Furthermore, coefficient setting circuit K
2, K4 is set to 1/2, and the other coefficient setting circuits are set to zero. If the output of the adder circuit 251 and the output of the delay element DL2 are switched at a frequency of 8f sc by the changeover switch 252, the data of the sampling points indicated by white circles and black circles are alternately obtained as shown in Fig. 2. can get. Now, assuming that the data at the position of the black circle is obtained from the delay element DL2, the data shown at the position of the white circle is interpolated data. When the sampling points of this data are arranged and shown, it becomes as shown in FIG. 3a. This data is stored in the latch circuits 281, 28
2,283,284,285 in parallel.

On the other hand, for the latch circuits 281 to 285,
A latch pulse from a 1/5 frequency divider 29 is applied.
This 1/5 frequency divider 29 divides the output of the previous oscillator 22 into 1/5.
This is a frequency dividing circuit. Therefore, from this divider 5
If the divided outputs with different phases are extracted and used as the latch pulses of the latch circuits 281 to 285, each latch circuit 281 to 285 will latch the data at the points indicated by the multiplication marks b to f in FIG. 3, respectively. That will happen. This means that data sampled at a frequency of 8×f sc is latched once every five times.

Therefore, the output data from each latch circuit 182-185 is equivalent to being sampled at a frequency of (8/5) fsc.

Due to the above operation, there are 5 types of different phases.
Moreover, a digital video signal sampled at (8/5) f sc is obtained. Here, one of the five types of phases is selected, which is determined by the determination circuit 3.
Determined by 0.

That is, the determination circuit 30 receives the clock run-in signal transmitted for synchronization at the beginning of the character multiplex signal. The clock run-in signal is
A timing setting circuit 27 that is preset with a vertical synchronizing signal and detects the position of the clock run-in signal by counting the horizontal synchronizing signal is introduced into the determination circuit 30 by controlling the gate switch circuit 26. The determination circuit 30 detects a digital video signal whose phase is synchronized with the clock run-in signal or whose sampling timing has the smallest phase difference, and controls the selection switch 31 to extract the video signal. Further, the determination circuit 30 also controls the selection switch 32 so as to extract the latch pulse that latches the extracted video signal. Since the clock run-in signal is a repetition of 101010..., the data series with the largest difference between the maximum value and the minimum value of each data series obtained at the timings b to f in Figure 3 within this period is the clock run-in signal. This will be close to the phase of the in signal. In other words, the difference between the data in the 1 period and the data in the 0 period of the clock run-in signal may be calculated for each series.

As a result, the output from the selection switch 31 is
This is a digital character signal sampled at a frequency of (8/5)fsc, and the output of the selection switch 32 is a clock signal synchronized with this.

Although various embodiments are possible as a means for generating interpolated data, a simple method is to use the average data of adjacent sampling data as interpolated data. Furthermore, various methods can be implemented to determine the time position of interpolated data. In addition to the above embodiment, the edges of a 4f sc sampling clock with a duty ratio of 50% may be used, and the rising and falling edges thereof may be used.

[Effects of the Invention] As explained above, the present invention makes it possible to obtain a sampling clock for receiving a character multiplex signal with a simple configuration in a circuit that processes a quantized digital television signal. A receiving device for a teletext signal can be provided.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a conventional sampling clock regeneration circuit, Fig. 2 is an explanatory diagram of signals to explain the present invention, and Fig. 3 is an explanatory diagram of sampling timing to explain the operation of the present invention. , FIG. 4 is a circuit diagram showing an embodiment of the present invention. 25...Interpolation data generation circuit, 281-285...
Latch circuit, 30...determination circuit, 31, 32...switch circuit.

Claims (1)

[Claims] 1. Period T = 1/(4f sc), where f sc; an analog-to-digital conversion circuit that generates a digital video signal sampled at an interval of a color subcarrier frequency; and a circuit to which the digital video signal is input. It consists of a plurality of delay elements connected in series, and an interpolated signal obtained by adding a signal obtained by multiplying the tap signal of each delay element by a coefficient, and a direct signal of an intermediate tap serving as a reference are alternately transmitted. By deriving the selection,
an interpolation data generation circuit that pseudo-converts into a data series with an interval of 1/(8f sc) period; and a period T output from the interpolation data generation circuit.
=1/(8f sc) data series is cyclically latched in five latch circuits at a frequency of (8f sc)/(5f sc), and the period of output data of each latch circuit is T.
=5/(8f sc), and comparing the phase of a clock run-in signal that is intermittently inserted into the digital video signal and the phase of each output data of the five latch circuits. and means for deriving the output data having a phase closest to the clock run-in signal.