JPH0452939A - Lock control system - Google Patents

Abstract

PURPOSE:To select an effective processing request from a priority circuit in each cycle to send it to a storage device by comparing the processing request from a processing unit by first and second comparing means and suppressing the preference control in the priority circuit with respect to the processing request in the case of equal output to perform the lock control. CONSTITUTION:A first comparing means 22 is used at the timing when processing requests from processing units PU0 to PU7 are set to ports PORT0 to PORT7, and a second comparing means 23 is used at the timing after setting of processing requests to ports PORT0 to PORT7. When the equal comparison is obtained, the preference control in a priority circuit 24 is suppressed with respect to processing requests to perform the lock control. Thus, the effective processing request is selected from the priority circuit 24 in each cycle and is sent to the storage device.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art and Problems Solved by the Invention 7 Means for Solving the Problems Action Examples Effects of the Invention [Summary] Plural Processing Devices Regarding the lock-based control method in the storage control device (MC[]) connected to the storage device shared by A port (POR) that holds processing requests from the processing device to the storage device for the purpose of facilitating processing.
TO~), a lock control register (LCRO-) that holds the own control information from each processing device, and when a processing request from each processing device is set to the port (PORTO~). is the address set in the port (PO)
)70~) to each baud, l, (PORTI),
) First comparison method, J-9 After the processing request is sent to the boat (PORTO), the processing request is sent to the boat (PORTO). 7:, J, set the address ('l and s) of the write control register (LC [NO=)
20th Hiken F compared for each I My River (PORT1~・)
Based on the comparison results between stage 1' and stage 1', the priority order of line processing requests is 4Y>:. The processing request from the processing device is
In the evening/timing set to RTO~・), the -1 exhaust L1 first comparison means compares and determines whether the processing request is
．． ．． At the timing after it is set to (F10RTO~), the second comparing means compares and a matching output is obtained.

When the processing request is received, the processing request will be sent on 11. ζ, 2. ] Notes・1
``Priority selection control in the priority circuit is configured to perform lock control by inhibiting the control circuit.''

[Industrial application field]

In the present invention, when a plurality of processing devices share a memory and send a processing request to the device, the processing device 1.y refers to a certain area of the storage device and updates the storage device. The present invention relates to a lock control device for preventing other processing devices from issuing processing requests to this area while the processing is in progress.

In recent years, information processing devices often take the form of multiple processing devices sharing a storage device.1. In such a configuration, each processing device may attempt to issue a processing request to the same area of the storage device. Therefore, one processing device references it.

It is necessary to perform lock control to prevent other processing devices from issuing processing requests to the area being updated.

In particular, as the number of processing units that share a storage device increases as in recent years, the opportunities for the above-mentioned lock control also increase, so priority selection of valid processing requests in each cycle is performed using a priority circuit. A lock control scheme that can be sent to a storage device is required.

[Prior art and problems to be solved by the invention] FIG. 3 is a diagram explaining a conventional lock control system, in which the lock control register (LCRO
7 shows an example of 21 and its peripheral circuit.

In this figure, a processing request coming from a processing device (PIIO''-yen+7) 1 is set in a baud 1-(Pi哩TO-~) 20 in a storage control device t(MCI+) 2.

The processing request that was made, the priority circuit (
PRIORITY) 24aM come and choose,
'h1. -':'Shift register (R1) 2 of the instruction vibe line 213 consisting of star groups R1 to □Rn
1 included in PiO, in principle, this vibe sea (,
' / 25 requires processing] Before inputting i
PORTO-) Hold 20&im, and as soon as the lock is released, the super-block 2 image will be inhibited from restricting the priority selection in circuit 24a! If you say J, it will be valid every cycle It is efficient because it allows you to select the desired processing request, but if you configure it in this way, the number of logic stages in the steps from the port (PORTO) 20 to the vibe line 25...\ will increase (i.e., Briority m24a → lock control circuit)
However, the engine speed increases, and the performance of the information processing device deteriorates.

Therefore, in the conventional system, lock control is performed at the first stage of the pipeline 25, as shown in the figure.

That is, the processing request set in the shift register (R1) 250 is sent to the next shift register (R2) 251, and if the processing request has a lock request, the lock control register (LCRO~) 21 Among them, the lock control information (address of the shared storage area, etc.) is stored in the one corresponding to the processing device (PUO-PUT) 1 that is the processing request source.

At the next timing, the shift register (R1) 25
The addresses of another processing request set to 0 and the lock control information stored in the lock control register (LCRO~) 21 are compared in the comparator (COMPO~7) 26, and if they match, the lock state is established. , a lock nutify circuit (LNG) 27 sends a processing request (MS[I) issued at that stage to a storage device (not shown), a signal S1 for invalidating (cancelling) the The address set in (R1) 250 is the next shift register (R2) 2
A signal S2 is sent to prevent the signal from being set to 51.

Furthermore, this signal S2 prohibits participation in the priority circuit (PRIORITY) 24a of the port (FORTO~) 20 to which the locked processing request is set, and the locked processing request is ~) 20, and when the lock control information in the lock control register (LCflO~) 21 is reset by a specific command etc. from the corresponding processing unit (PUO-PO2) 1 and the lock is released, It operates so that participation in the priority circuit (PRIORITY) 24a is permitted.

However, with this conventional method, the address of the processing request is
The processing request is compared with the address in the lock control register (LCRO~) 21 in the priority circuit (P
RIORITY) 24a.

Therefore, after a processing request with an address matching the address of the lock control register (LCRO~) 21 is sent from one of the processing units (PUO-PO2) 1,
Furthermore, the priority circuit (PRIORITY) 2
4a, the processing request is sent out from the shift register (RL) 250 and then invalidated, so that the processing request is sent to the next shift register (RL) for one cycle.
R2) Nothing is set in 251. Furthermore, if the processing requests have to be processed in priority order, it is necessary to wait one more cycle, resulting in wasted cycles. Furthermore, the lock-nullify circuit (
LNG) 27, the signals such as Sl and S2 mentioned above had to be sent out, creating a problem of complicated control.

SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks of the conventional art, it is an object of the present invention to provide a lock control system that can select valid processing requests from a priority circuit (PRIORITY) every cycle and send them to a storage device.

[Means to solve the problem]

FIG. 1 is a diagram showing the basic configuration of the present invention.

The above problems are solved by a lock control system configured as follows.

A lock control method in a storage control unit (MCU) 2 connected to a storage device shared by a plurality of processing units (PUO~) 1, wherein a processing request from the processing bag f (PUO~) 1 to the storage device is Hold the board 1- (FORTO~)20
and.

and a lock control register (LCRO~) 21 that holds lock control information from each processing unit (PUO~) l.

Processing requests from each processing unit (PUO~) 1 are submitted to the boat (
When set to PORTQ~)20, the corresponding boat (F
a first comparison means 22 for comparing the address set in the ORTO~) 20 and the address of the lock control register (LCRO~) 21 for each port (PORTI~) 20;

After the processing request is set to the port (FORTO~>20), the address of the boat (FORTO~) 20 and the address of the lock control register (LCRO~) 21 are compared for each port (PORTI~) 20. and a second comparison means 23.

Based on the respective comparison results, a priority circuit 24 is provided to suppress and control the priority selection of the processing request, so that the processing request from the processing device ll (P[IO~)1 is routed to the above board (FORTO~). At the timing when the processing request is set to 20, the first comparing means 22 compares the process request, and at the timing after the processing request is set to the port (PORTO~) 20, the second comparing means 23 compares, When a matching output is obtained, the processing request is configured to suppress priority selection control in the priority circuit 24 and perform lock control for the processing request.

(Function) That is, according to the present invention, a plurality of processing bags W (PUO to P
Lock control for processing requests from IJ7) is performed before a priority circuit for performing priority selection control for the plurality of processing requests.

With this configuration, a certain processing request is immediately selected by the priority circuit and sent to the storage device, and other times it is selected due to low priority, bank busy, etc.
There are cases where it is necessary to wait for several cycles, but when performing lock control on processing requests immediately sent to the storage device, the following problems arise.

That is, if there is a logical delay for comparison control with lock control information, and if lock control is required for the processing request, the priority circuit (PRIORITY
) requires a logical mechanism to suppress input to
Considering that it would be too late to perform the comparison process with the lock control information after it is set on the boat (FORTO~), we decided to perform the comparison process with the lock control information before it is set on the boat (FORTO~). 1 comparison circuit (COMP
OOI~).

However, as mentioned above, some processing requests are
Since it may be necessary to wait several cycles after the boat is set to
Processing requests set in RTO~) also require comparison processing with lock control information. This comparison process is configured to be performed by a second comparison circuit (GOMPOII~).

Then, a comparison process is performed with the lock control information for the processing request before being set in this boat (FORTO~), or a comparison process is performed with the lock control information for the processing request set in the boat (PORTO~). For example, a valid signal (PO
RTO VALII)~).

Hereinafter, the operation of configuration 1 of the lock control system of the present invention will be specifically explained.

First, processing requests from processing units cpuo to PU7) are
If the lock is set on a boat (FORTO~・7) and has a lock request at the same time (this means
(which can be recognized by looking at the operation part of the instruction set in TO~7) is set in the lock control register (LCRO~7) that corresponds to the processing unit (PUO-PUT) that is the source of the processing request. Lock control information (address of shared storage area, etc.) is stored.

And this lock control register (LCRO~7),
The address of a processing request from another processing device (PUO to P[]7) sent to a boat (FORTO to 7) is stored in the first address provided corresponding to each boat (PORTO to 7). The processing request is compared in the comparator (GOMPOOI~706) of the port (FORTO
~7), and in the next cycle, the address of the lock control register (LC1?0 to 7) and the address of the processing request set to each port (to FORTO, 7) are set to each port (POI?7). Comparisons are made in second comparators (COMP011-716) provided corresponding to TO-7).

Furthermore, these comparison results are sent to the selection circuit (SBLOI~76
) is sent. At this time, the boat (PORTO~7)
If the processing request is not set, the selection signal (
SIGO~7), the selection circuit (SELO1~7)
0), the first comparator (CMPOOI~706)
In the cycle after the side is selected and the processing request from each processing device t (PUO-Pt17) is set in the port (PORTO~7), the L selection signal (SIGO
The second comparator (CMPO1l~716
) side is selected.

If the comparison result signal selected in the comparison process indicates address matching, the priority circuit (PRIO
The matching signal (2), which prohibits the selection of the processing request, is sent to the processing request (RITY).

The above selection signal (SIGO~7) is the boat (FORTO~
7), the polarity changes depending on whether or not the processing request data is being held, and as described above, the selection circuit (S
ELOI) selects the signal from the first comparator (COMPOOI) when the port (PORTI) is not in the data holding state, and selects the signal from the second comparator (COMPOOI) when it is in the data holding state.
This selects the signal from COMPOII).

Since it operates in this way, in the present invention, addresses are compared using lock control registers (LCRO~7),
Matching processing requests are sent to the priority circuit (PRIORI).
By prohibiting participation in TY), lock control is performed on the processing request that generated the matching signal (), and a valid lock is stored in the storage device every cycle for processing requests that are not subject to the lock control. It is configured to be sent as a processing request.

Also, when the boat (FORTO~7) is not in the data holding state, the address set at the next timing and the lock control register (
Select the signal resulting from comparing the addresses of LCRO~7), and when in the data retention state, select the address of the retained boat (FORTO~7) and the address of the lock control register (LCRO~7) above. By selecting the comparison result signal and sending it to the priority circuit (PRIORITY), the priority circuit (PRIO
RITY), a processing request with the same timing as this comparison result signal is always selected.

For example, although the port (PORTI) is not in the data holding state, the address of the processing request set to the port (PORTI) next will be in the lock control register (LC).
Even if the address matches the address of a lock control register (LCR2 to 7) other than RI), the address of the corresponding port (POR
TI) processing request is sent to the lock control register (LCRI) in the cycle set in the port (PORTI).
The coincidence signal (2) from the selection circuits (SELO1-76) other than the selection circuits (SELIO-17) corresponding to the corresponding port (FORTI) simultaneously prohibits selection in the priority circuit (PRIORITY).

This is because the selection circuit (SELO) has a latch mechanism.
It operates so that the timing at which the match signal from the first comparison circuit (CMPOOI to 706) is latched by the selection circuit (SELO1 to 76) coincides with the timing at which the processing request is set to the port CPORTO. It is for this purpose.

If the processing request is not immediately selected by the priority circuit (PRIORITY) and is made to wait for the next cycle or later depending on its priority, the port
The processing request set and held in (FORTO) and the address of the lock control register (LCRO) are always compared in the second comparison circuit (CMPOII to 716) from the next cycle onward. As a result of the operation, if the matching signal ■ is output from the selection circuit (SELO1 to SELO76), the processing request is
From the next cycle after the cycle set to O),
Selection by the priority circuit (PRIORITY) is prohibited. This prohibited operation continues in each cycle until the lock request of the processing request that has the lock request that matches the address of the processing request is released, and in the cycle in which the lock request is released, the priority is If it is in first place, it is immediately put into the vibe line and sent to a storage device (not shown).

Of course, normal processing requests that are not subject to selection prohibition are always
It is set in each port (PO1?TO~) every cycle, and the priority selection is controlled by the priority circuit (PRIORITY), and processing requests are sequentially processed starting from the highest priority.
The data is sent to the storage device.

Because it operates in this way, in the present invention, in each cycle, a certain processing request is not canceled in the pipeline as in the conventional method, and the priority circuit (PRIORITY) constantly processes the object of lock control. This has the effect that only valid processing requests are selected and sent to the storage device every cycle, and processing requests from the processing device can be executed without any hitches, improving the performance of the storage control unit (MCU). The effect is that there are many areas that contribute to improvement.

〔Example〕

Embodiments of the present invention will be described in detail with reference to the drawings.

The above-mentioned FIG. 1 is a diagram showing the principle configuration of the present invention, and FIG. 2 is a diagram showing an embodiment of the present invention, in which (a) shows an example of the configuration, and (b) shows an operation time chart.・It shows.

In this embodiment, °C is a storage control device connected to a storage device shared by a plurality of processing devices (1) [to 10], for example, two processing devices (1'U0.1) 1.
MCtl) 2, the two processing units (PUo, 1
) Boat processing request from 1 (PORTo, 1) 2
0 and the priority circuit (PRIORITY
) 24 performs priority selection and performs lock control when sequentially selecting items starting from the highest priority.
Provided before PRIO[TY)24. At this time, the boat (FORTo.

1) When no processing request is held in 20, the address of the processing request and the lock control register (LC) are set in 20 at the next timing.
A first comparison circuit (CMPloo, 001) 22 that compares the address of Rl, O) 21 with the address of G, when a processing request is held in the port (FORTo, 1) 20, Boat (PORTo, 1
) 20 7 dos U/S and r tonk control register (LCR
A second comparator circuit ((JPilO, 011) 23 is provided to compare the address of the processing request from each processing unit cpuo, i) with the °7 address of 21.
Corresponding port (FORTo, 1) Sera (・
7 from the previous cycle. The boat (PORTo, 1
) is set to 20 in subsequent cycles as well, and the port (PORTo.

1) Before the cycle set to 20, 1-2 first
The second comparison circuit (CMPIOo, 001) selects the matching output of
Pllo, 011) 23 is selected and when a matching output is obtained, the priority circuit (PRIORITY)
A means for suppressing the selection of the boat (FORTO, 1) 20 at 24 is a necessary means for implementing the present invention. Here, the first comparison circuit.

In the second comparison circuit (CO liver xyz), =x1 corresponds to lock control register (LCRx) 21 L211
, lyl indicates the first comparison circuit when it is 0゛, 1゛ indicates the second comparison circuit, and zI corresponds to the port (FORTz) 20 where the processing request to be compared is set. .

Note that the same reference numerals indicate the same objects throughout the figures.

Hereinafter, the lock control system of the present invention will be explained with reference to FIG. 2 while referring to FIG.

In this example, for convenience of explanation, two processing devices (
Hereinafter, the case of pt+o, i) will be taken as an example.

In this figure (a), the PORTO, lν^LID signal is 5NG0.1 among the 5XGO~7 signals in Figure 1.
and two boats (PORTo, 1)
This is a signal indicating that data is held in 20.

First, time 1. A lock processing request (PL
IOREQUEST) is set to port CPORTO) 20, and at the same time the lock control register (LCRO)
It is also set to 21. As a result, as shown in Figure (b), at the time t, the above PORTOVALI
The D signal turns “on”.

Further, at time t2, a processing request from PUI 1 is set in port (PORTI) 20. As a result, at time t2, the PORTI VALID signal becomes
It turns on.

Here, at the time t, the port (PORTI
)20 is not in the data retention state yet, so the above PO
RTI VALID (item based on No. 3, selection circuit (SE
LO) 28 is the first comparison circuit (COMPO) of the present invention.
OI) 22 is selected, and the comparison result is sent to a priority circuit (PRIORITY) 24.

Therefore, the address to be set in the port (POI?TI) 20 is the lock control register (L(
If the address matches the address of JO) 21, the value of the first comparison circuit (COMPOI) 22 is °1'', so the output ■ of the selection circuit (SELOI) 28 becomes °l', and the above priority circuit (PRIORITY) 2
4, the processing request set to the port (PORTI) 20 is set, and at the same time, selection is inhibited by the signal 1° from the first comparison circuit (COMPOOI) 22.

Furthermore, at time t2, the boat (PORTI) 2
Since 0 is the data retention state, the above POIIITI
Based on the VALID signal, the selection circuit (SELOI)
28 is the second comparison circuit (COMPOII) of the present invention
23 and the comparison result is the priority circuit (PRI).
ORITY) 24.

Therefore, the address set in the port (FORTI) 20 is the address set in the lock control register (LCRO).
21, the second comparison circuit (
Since the value of COMPOII) 22 is 1, the output of the selection circuit (SELol) 2B is 1, and the processing request set to the port (PORTI) 20 by the priority circuit (PRIORITY) 24 is as follows: Selection is inhibited by the signal °1' from the second comparator circuit (COMPOII) 22.

The selection prohibition condition is the lock control register (LCRO) 2
The lock control information set to 1 is set to 1 by the processing device f(
PUO) is released by being reset by a specific command from 1.

In the cycle in which the selection prohibition condition is canceled and in subsequent cycles, when the priority of the processing request set in the port (PORTI) becomes first, at that point, the pipeline (not shown) This is also sent to a storage device (not shown) via .

In this way, the present invention provides a method for using a plurality of processing units (PUO~).
A boat (FORTO~) that holds processing requests from
A lock control register (LCRO~) that sets a lock processing request from the processing unit (PUO~).

In the cycle before the above processing request from each processing device (puo~) is set to the above boat (FORTO~),
A first comparison circuit (COMPOOI~) that compares with the address indicating the shared storage area set in the lock control register (LCI?0~), and a
In each cycle after it is set to (FORTO~),
A second comparison circuit (COMOII~) that compares with the address indicating the shared storage area set in the lock control register (LCRO~) is connected to each boat (FORTO~
), and a cycle before a processing request from the processing device is set in the corresponding port (PORTQ~);
Each subsequent cycle, each lock control register (LCRO
~) address and the above 1st address corresponding to each port (FORTO~). When the second comparison circuit compares and a matching output is obtained, the priority circuit (
The feature is that the priority selection control on PRIORITTV is suppressed.

In this embodiment, the number of processing devices is two, but the same effect can be obtained even if the number of processing devices is further increased.

〔Effect of the invention〕

As explained above, according to the present invention, only valid processing requests that are not subject to locking are constantly selected in each cycle in the priority circuit (PRIORITY) and sent to the storage device. The processing requests from the storage controller can be executed without any delay, and the effect is that it greatly contributes to improving the performance of the storage control device.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration of the present invention. FIG. 2 is a diagram showing an embodiment of the present invention. FIG. 3 is a diagram explaining a conventional lock control method. It is. In the drawings, 1 is a processing device (PUO-PUT). 2 is a storage control unit (ACU). 20 is a boat (PORTQ~). 21 is a lock control register (LCRO~); 22 is the first comparison circuit (COMP001 to 007, 10
1-107. ~) 23 is the second comparison circuit (COMPOI
→~017.111~117. ~). 24 is a priority circuit (PRIORITY). 25 is a pipeline. 250.251. ~ is each shift register. 26 is a comparison circuit (COMPO~7). 27 is a lock nullify circuit (LNG). 28 is a selection circuit (SEL01-07.-, 70-76)
. are shown respectively. CO? [POll SELOI Diagram (Part 2)

Claims (1)

[Claims] A storage control unit (MCU) (2) connected to a storage device shared by a plurality of processing units (PU0~) (1)
A lock control method in which a port (PORT0~) (20
), and lock control registers (LCR0~) (that hold lock control information from each processing unit (PU0~) (1)).
21), and when a processing request from each processing device (PU0~) (1) is set to the port (PORT0~) (20), the address set to the port (PORT0~) (20) and , the above lock control register (LCR0~)
(21) address for each port (PORT1~) (20
), and after the processing request is set in the port (PORT0~) (20), the address of the port (PORT0~) (20) and the lock control described above are used. Register (LCR0~) (21
) for each port (PORT1~) (20), and a priority circuit (23) that performs suppression control of priority selection of the processing request based on the respective comparison results. 24), and at the timing when a processing request from the processing device (PU0~) (1) is set to the port (PORT0~) (20), the first comparing means (22) compares the request. , at the timing after the processing request is set to the ports (PORT0~) (20), the second comparing means (23)
A lock control method characterized in that when a matching output is obtained by comparing the above, lock control is performed by suppressing priority selection control in the priority circuit (24) for the processing request.