JPS5821736B2 - Memory control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory control method in an information processing system, and more specifically, to a memory control method in an information processing system in which a plurality of memory devices with different speeds are connected on the same bus. It is.

2. Description of the Related Art In recent years, there has been remarkable development of various types of memory elements, and along with this, memory devices used in information processing systems have also become more diverse.

In general, the cost ratio of the main memory device in an information texture system is very high. Therefore, in order to design an information alpha ring system with good cost performance, it is necessary to select a memory device that matches the required texture ability. ing.

However, as mentioned above, advances in memory devices are remarkable;
A memory device that is not thought to be economically practical at the time of system design may be put into practical use by the time the system is commercialized. A method that can flexibly respond to progress and development is desirable.

On the other hand, in information processing systems where the access frequency of programs and data is known in advance, such as the central processing system in electronic exchanges, frequently accessed programs and data are processed at high speeds even though they are costly. A system with good cost performance can be realized by accommodating programs and data that are accessed infrequently in a cheap and low-speed memory device.

Furthermore, in information texture systems such as electronic exchanges, memory devices that match the texture capabilities required by station conditions can be freely connected without requiring changes in the design of the central control unit in response to changes in station conditions. If you have a configuration that allows you to do this, you can design a system with better cost performance.

For the reasons mentioned above, a memory access control method, that is, a different speed memory control method, which allows a plurality of memory devices having different access times to be connected on the same memory bus, has recently been adopted.

Conventionally, in information texture systems employing such different speed memory control methods, instruction texture patterns have been designed based on the access times of the fastest memory devices connected on the same memory bus.

In other words, the texture device that is currently accessing the memory device
When a subsequent access request to another memory device on the same memory bus occurs, there is a method for permitting subsequent memory access before a certain time when response information is returned from the memory device currently being accessed to the central controller. This "
The "fixed time" was fixedly determined within the access time of the fastest memory device connected on the same memory bus.

This will be explained in more detail using FIGS. 1 to 9.

In these FIGS. 1 to 9, each symbol is used with the following meaning.

(1) I; CC memory access cycle (instruction fetch) (2) P; CC memory access cycle (operand fetch) (3) CH; data channel device memory access cycle (Jx; = instruction decoding, operand address total x cycles ( 5) A; Instruction execution cycle (6) n, n+1, n+2; Instruction is nth
It shows that it is the 1st (n+1)th and the (n+2)th.

(7) ----; Waiting cycle (8) e: Machine cycle time (= bus cycle time) Now, Figure 1 shows a representative command during three-stage advance control when a memory with an access time of 2e is connected. JE! Show a pattern.

Here, CC memory access cycle (instruction fetch)
■ and CC memory access cycle (operand fetch) P are accessing different memory devices on the same bus.
It is possible to improve the texture ability.

As mentioned above, during a memory access cycle (for example, n+
Subsequent memory access requests (e.g. n
P) is the previous memory access cycle (e.g. n
However, in the case of a memory device with an access time of 2e, subsequent memory accesses (e.g. By allowing P) of n, efficient memory control without waiting cycles can be achieved.

Figure 1 shows the case of memory devices with the same memory speed.
In the case of different speed memories, problems of answer bus collision and answer data overtaking occur.

FIG. 2 is an example of an answer bus collision.

For example, as in this example, the access time of low-speed memory is 3
In a different speed memory system where the access time of the high speed memory is 2e, the nth When high-speed memory is accessed in the operand fetch of the th instruction (P in n in Figure 2), the response information from two memory devices overlaps on the memory answer deck bus MWB as shown in Figure 2. This is called an answer bus collision, but since it causes malfunction of the central texture device, it is necessary to control it to avoid it.

FIG. 3 is an example of overtaking answer data.

As shown here, for example, in a different speed memory system where the access time of low-speed memory is 4e and the access time of high-speed memory is 2e, the instruction fetch of the n+1th instruction (n+1 in Figure 3) is performed. If the high-speed memory is accessed by the operand fetch of the n-th instruction (P of n in Figure 3) while the low-speed memory is being accessed in I), the response information from the low-speed memory that was accessed first will be accessed later. The response information is returned later than the response information from the high-speed memory.

This is called answer data overtaking, and if it occurs between an instruction fetch and an operand fetch, it will cause a malfunction of the central control unit.

The conventional method to solve these problems in different speed memory systems is to control the start of a subsequent memory access cycle at a certain time before the end of the preceding memory access cycle, as described above. In the examples shown in Figures 2 and 3, the "fixed time" is determined so that the highest speed memory device in the different speed memory system can be controlled most efficiently when accessed continuously. Since the access time of the fastest memory device is 2e, a method is applied in which the subsequent memory access cycle is allowed to start before the preceding memory access cycle ends le, as shown in FIG. Although the above-mentioned problems have been solved by using the command ashtray pattern shown in FIGS.

In other words, in a different-speed memory system where the access time of low-speed memory is 4e and the access time of high-speed memory is 2e, when the low-speed memory is accessed consecutively, according to the conventional method, the access time shown in FIG. This results in a free texture pattern such that subsequent memory access requests that occur during the memory access cycle (in Figure 6,
P of n for 1 of , I of n+2 for P of n.

P of n + 1 for 1 of n + 2) forces unnecessary waiting cycles (each 2e in FIG. 6), leading to a decrease in texture ability.

This waiting cycle is essentially unnecessary, and there is no inconvenience if the command α is followed as shown in FIG. 7, and the processing ability is improved in this way.

For example, in a different-speed memory system similar to that shown in FIG. 6, if the central control unit accesses the high-speed memory while the data channel device is accessing the low-speed memory, the conventional method results in the instruction processing pattern shown in FIG. .

If answer data overtakes occur between the central controller's instruction fetch and operand fetch, it will cause malfunction.
Even if answer data is overtaken during the memory access cycle between the data channel device and the central control device, there is no problem, so the waiting cycle (2e) in FIG.
This is also unnecessary, and there is no problem with the instruction texture pattern shown in FIG. 9, and the texture ability is improved.

As shown in these examples, the arrow of conventional methods is that the acceptance of subsequent memory access requests that occurred during the preceding memory access cycle is controlled in a uniform manner determined by the access time of the fastest memory device. This was done in a conventional manner, resulting in unnecessary waiting cycles when slow memory is accessed continuously and when answer data is allowed to overtake (for example, memory access between data channel equipment and central control unit). This results in a decrease in processing capacity.

In order to solve these drawbacks, the present invention has been developed to calculate the access time of the memory device currently being accessed and the access time of the memory device currently being accessed when a request to access another memory device on the same bus occurs while the memory device is being accessed. Subsequently, by comparing the access time of the memory device for which the access request occurred, and allowing access to the memory device for which the access request occurred subsequently, it is possible to eliminate all speed combinations. The present invention provides a flexible memory control system that allows memory devices to be used most efficiently even in different speed memory systems.This will be described in detail below.

FIG. 10 is a block diagram of an embodiment of the present invention, in which the central control unit CC includes a memory address bus MAJ3, a memory write data bus MDB1 and a memory answer data bus MWB.
It has three types of buses, to which one or more memory devices 2MM12MM2 to MMn are connected, and these memory devices receive memory activation signals ENo and E from the central controller CC.
N1. Each of these memory devices MM is activated by EN2 to ENn and has an access time T.

, T1. T2 to Tn, at least one of these access times is different from the others.

FIG. 11 is a block diagram of the memory device control section in the central controller CC.

In FIG. 11, an access request to the memory device MM is made by a command control unit (not shown) of the central control unit CC, for example.
The memory access contention circuit is executed by a request signal RQ1 from the central controller CC, by a request signal RQ2 from the operand control unit (not shown) of the central controller CC, and by a request signal Rq from the data channel device (not shown). One of them is selected with priority in the MAP, and this information is sent to the memory address data selection circuit MASL.
and sends the memory address data of the preferentially selected device, that is, the memory address data AD from the command control section of the central control device CC, or the memory address data AD2 from the operand control section of the central control device CC, or the data channel device. Memory address data AD3 from
Select one.

The memory address data selected by the memory address data selection circuit MASI is divided into two parts: a logical memory device name part LEN and a memory device internal address part m.
It consists of ab.

The memory device internal address section mab is sent to the drive gate DG.

The logical memory device name portion LEN is sent to a memory device name conversion circuit MNC and converted into a physical memory device name PEN.

The physical memory device name PEN is decoded by the decoder DEC and sent to the drive game 1-DG as a memory device designation signal eno''enn.

Furthermore, the physical memory device name PEN is sent to the memory device speed indicator circuit MSI.

The memory device speed display circuit MSI stores the access time of the memory device MM corresponding to the memory device MM, and outputs the access time display signal ms of the corresponding memory device MM according to the designation of the physical memory device name PEN.

The physical memory device name PEN and the memory device internal address mab are also input to the access condition check circuit ACK.

The access condition check circuit ACK performs a memory device busy check, a memory protection check, etc., and when access is possible, sets the access signal ACK to "1" and sends it to the memory access control circuit MC19MC22MC3.

Each memory access control circuit MC12MC22MC3 receives a memory access request RQ1 from an instruction control unit (not shown) of the central control unit CC and a memory access from an operand control unit (not shown) of the central control circuit CC in the memory access contention circuit MAP. Request RQ2 and memory access request RQ3 from a data channel device (not shown) cause memory access circuit activation signal rTI.
Cl+rn, C2t, rn, and Ca are respectively selected and activated when the access enable signal ACK from the access condition check circuit ACK is 1''.

The memory access control circuit MC12MC22MC3 checks the memory speed to see if there is any problem in accessing the memory device MM now based on the memory access time display signal ms from the memory device speed display circuit MSI.

The present invention relates to this check, which will be explained in detail later.

Now, if the check result is that access is not possible, memory access is prohibited, but in the case of access, memory drive timing signal DT1. DT
2. By sending DT3 respectively, the memory address bus MAB is driven and the memory activation signal EN(, +EN1...
・・・・Instructs the sending of ENn, and also sends the memory access time display signal ms from the memory device speed display circuit MSI.
An answer reception timing signal RT1. for receiving response information from the memory device via the memory answer data bus MWB based on the response information RT1. RT2. RT3 to answer reception gate R
G1. RG2. Send each to RG3.

Answer reception gate RG1. RG2. RG3 is the memory device M received from the memory answer data bus MWB.
The response information from M is stored as memory answer data WD12wD2.
．． As WD3, each memory access request source, that is, the command control unit (not shown) of the central control unit CC
, an operand control section of the central controller CC (not shown)
, to a data channel device (not shown).

The above is an outline of the operation of the memory control unit to which the present invention is applied.
This relates to MC22MC3, and will be explained in more detail below using FIG. 12.

In FIG. 12, MC12MC22MC3 is the memory access control circuit MC12MC22MC3 in FIG.
is shown in detail.

In Figure 12, Cαβ (where α=1.2, 3.β=
1.2.3 and α\β.

same as below. ) is a memory speed comparison circuit in the memory access control circuit MCα2, which compares the access display signal ms sent from the memory device speed display circuit MSI with the output signal sbβ of the 11 circuit SBβ in another memory access control circuit MCβ. If the condition is satisfied, the first AND game)Gα.

1'' is applied to the access request source. This condition differs depending on the source of the access request, and will be described later.

If the access condition is satisfied in the comparison circuit Cαβ, and the access enable signal ACK, which is the output of the access condition check circuit ACK, is 1''' and the memory access circuit activation signal mcα is 1'', the first AND gate Gα .

is opened, the memory access control circuit MCα is activated, and in synchronization with the clock CLK, the fifth AND game 1-Ga4 is activated.
The 'mori drive timing signal DTα' is sent out via the.

In the memory access control circuit MCα, SRα is a register that temporarily stores the memory speed currently being accessed, and together with the -1 circuit SBα constitutes a counter.

Register SRa: 1 is set in the initial state. Therefore, the output sbd of the 11th circuit SBα is 0, and the output zdα of the zero detection circuit ZDα is N, +1.
It becomes.

The output of the first AND gate 1-Ga4 is "lu, and the output zdα of the zero detection circuit ZDα is 1".

Then, the access time display signal ms is passed through the third AND gate Gα2. It is set in register SRα via OR gate Gα3 in synchronization with clock CLK.

The output srα of the register SRα is input to the 11th circuit SBα, and the 11th circuit SBα further outputs sbα.

Ru.

The zero detection circuit ZDα is 0 when the output sbα of the 11 circuit SBα is 0.
When , the output zdα is set to “1”.

-1 when the output zdα of the zero detection circuit ZDα is “0”
The output sbα of the circuit SBα is connected to the second AND gate Gα1+
It is set in the register SRα again via OR gates 1-Ga4.

Output of zero detection circuit ZDα. When zda is "1", the above-mentioned counter function stops and a new register SRa
Tube third AND gate G (, n.

OR game) Access time display signal m via Ga4
At the same time, a fourth AND gate G
An answer reception gate signal RTα is generated by α4.

The conditions for the output of the comparison circuit Cαβ to be "1" are as follows in the example of FIG.

In the example of FIG. 12, MC1 is a first memory access control circuit that responds to a memory access request from an instruction control unit (not shown) of the central control unit CC, and MC2 is a first memory access control circuit that responds to a memory access request from an instruction control unit (not shown) of the central control unit CC. A second memory access control circuit for a memory access request of M
C3 is the third memory access control circuit for responding to memory access requests from a data channel device (not shown), but as mentioned above, it is necessary to avoid answer bus collision in any memory access, and it is necessary to avoid answer bus collisions in any memory access. Answer data passing between operand fetches must be avoided, but answer data passing between instruction fetches or operand fetches and data channel devices (not shown) is allowed.

Therefore, in the case of the example shown in FIG. 12, the output of the comparison circuit Cαβ is "
1'' occurs when the following time condition is satisfied between the access time display signal ms and the output sbα of the 11th circuit SBα.

That is, C1□ is rnS > S b2 t C13
is ms\Sb3. C23 is ms\sb3*C21 is rn
s > 5b1t C31 is ms\5b1t"32 is m
It is s\sb2.

Regarding the operation of the memory control unit, the first
A more detailed explanation will be given with reference to FIGS. 1 and 12.

In Fig. 13, co, C1...C1o indicate time, To, T1...Tlo indicate timing names, and To, T1...Tlo are all the same interval, which is equal to one machine cycle e.

Here, we will explain the case where a memory access request RQ3 from a data channel device (not shown) and a memory access request RQt from a command control unit (not shown) of the central control unit CC occur simultaneously at time C8. The premise is flexibility.

That is, (1) Memory access requests from the data channel device are given priority over memory access requests from the central controller CC.

(2) The access time of the memory device that the data channel device is currently trying to access is 5e (e is machine cycle).

(3) The access time of the memory device that the central controller CC is currently trying to access is 4e (e is machine cycle).

Now, the two memory access requests RQ1 and RQ3 that occurred simultaneously at time C6 are at timing T.

However, due to the above precondition (1), the access request R is input to the memory access contention circuit MAP in FIG.
Q3 is accepted.

The output of the memory access contention circuit MAP is at the same timing T.

In this case, the memory address data selection circuit MASL selects the address AD3 and outputs the logical memory device name section LEN and the memory device internal address section mab.

As described above, the logical memory device name section LEN is manually inputted by the memory name conversion circuit MNC to output the physical memory device name PEN, and the physical memory device name PEN is further sent to the memory device speed display circuit MSI to generate an access time display signal. ms is output, but now the above premise is 2)
Therefore, it is m s-5.

As already explained, the memory access system (m circuit M
The output z d 3 of the zero detection circuit ZD3 of C3 is "1", the comparison condition with the access time display signal ms is satisfied in the comparison circuit C31 and the comparison circuit C3□, and the output from the access condition check circuit ACK is satisfied. Assuming that the access enable signal ack is 1'', the memory access circuit activation signal mC from the memory access contention circuit MAP
3 is timing T.

Therefore, the third memory control circuit MC3
The first AND gate G, .

, the third AND gate 1-G3□, and the OR gate G33, the access time display signal ms is set in the register SR3 at time C1, and at the same time, the access time display signal ms is set in the register SR3 via the third AND gate 1-G3□ and the OR gate G33.
3. A memory drive timing signal DT3 is output from.

At timing T1, register output Sr3 indicates 5, which is input to -1 circuit SB3, and therefore -1 circuit Sr3.
The output sb3 of B3 indicates 4.

Now, the memory access request RQ1 generated from the command control unit (not shown) of the central controller CC at time C6 is received at timing T.

The priority competition at 2008 was lost and the process is suspended until timing T1.

Since there is no other memory access request at timing T1, the memory access contention circuit MAP issues a memory access request R.
I accept Q1.

Thereafter, at timing To, memory access request RQ
The access time indication signal ms is obtained in exactly the same manner as described in connection with 3.

According to the precondition (3), ms is now 24, but at timing T1, the output sb3 of the 11 circuit SB3 indicates 4, so the first memory access control circuit MC1
The comparison circuit C13 detects a match between the two and n Q jl
Therefore, the first memory access control circuit MC1
The AND clause of the first AND gate G1゜ does not stand,
At time C2, access time display signal m is sent to register SR1.
s is set, and the fifth AND gate G0
5, the sending of the memory drive timing signal DT1 is prohibited, and as a result, the timing T2 also becomes a waiting cycle.

At timing T2, the output sb3 of the -1 circuit SB3 of the third memory access control circuit MC becomes 3, and the comparison circuit C13 detects a mismatch and outputs nI.
Let it be I+.

On the other hand, assuming that the second memory access control circuit MC2 is not currently being accessed, the output sb2 of the -1 circuit SB2
is 1, therefore, the comparator circuit C12 also detects a mismatch and outputs "1".

Furthermore, if the access enable signal ack from the access condition check circuit ACK is 1'', then at timing T2, the memory access circuit activation signal mc2 is sent to the first memory through the first MΦgate G1o of the first memory access control circuit MC1. Activate the access control circuit MC1.

Timing T after all. The memory access request RQ1 generated at 03 is not accepted for the first time at time 03, and the memory drive timing signal DT1 is sent out.

Memory drive timing signal DT3. When DT1 is sent out, register SR3°SR and -1 circuit SB3. The 11 counter consisting of SB1 has the output of the 11 circuit sba l sb
Repeat the subtraction until l becomes O, -1 circuit SB3 p
The zero detection circuit ZD3. detects that the outputs sbs and sbl of SBt have become 0. ZD1 detects and its output zd3
．． Timings T5 and T when zdl becomes 1'',
The fourth AN of the third memory access control circuit MC3
D game 1-03. By outputting answer reception timing signals RT3 and RTl through the fourth AND gate G14 of the first memory access control circuit MC1, the signals on the memory answer data bus MWB are received at times C6 and C7, respectively.

In this way, when the memory access request RQ1 is accepted at the time C2, the expected answering collision at the time C6 can be controlled to be avoided with only the minimum number of waiting cycles (2e in this example).

In this case, it is clear that if the conventional method is applied, a waiting cycle of 4e is required, and the waiting cycle can be significantly shortened.

In the example shown in Figure 13, we explained about the answerbus collision.
Regarding the overtaking of answer data, the above-mentioned comparison circuit C
It can be similarly controlled by the comparison conditions for αβ.

As described above in detail, according to the present invention, the access time display signal ms output from the memory device speed display circuit MSI, that is, information regarding the access time of the memory device that is currently being accessed, and the information regarding the access time of the memory device currently being accessed. information regarding the access time of the memory device, i.e. outputs sb0 to sb of the circuits SB1 to SB3;
3 and comparison circuit C12ycts 1CZ31 C21t
By comparing C31t Cs□, if an answer bus collision is expected, the reception of subsequent memory access requests is delayed and controlled, and overtaking of answer data is allowed between the data channel device and the central controller, but the central controller Conventionally, control was implemented to prohibit overtaking of answer data between instruction fetch and operand fetch, and conventionally, memory access request reception for different speed memories was uniformly controlled in accordance with high-speed memory access time. from.

This eliminates unnecessary waiting cycles as shown in FIGS. 6 and 8, and enables efficient different speed memory access control as shown in FIGS. 7 and 9.

[Brief explanation of the drawing]

Figures 1 to 9 show representative command α during three-stage advanced control.
10 to 13 are for explaining the present invention, FIG. 10 is a block diagram of the information texture system, FIG. 11 is a block diagram of the memory control section in the texture device, and FIG. 12 is a block diagram of the information texture system. The figure is me. FIG. 13 is a detailed block diagram of the memory access control circuit in the memory control section, and is a timing chart showing an overview of the operations of the memory control section of FIG. 11 and the memory access control circuit of FIG. 12. CC...Central control unit, MMrr-...Main memory device, ENo -EN n...Memory activation signal, MAB...Memory address bus, MD
B...Memory write data bus, MWB...
...Memory answer deck bus, MAP...Memory access contention circuit, MASL...Memory address data selection circuit, MNC...Memory device name conversion circuit, MS... ...Memory device speed display circuit, MC1 to MC3...Memory access control circuit, DEC...Decoder, DG...
・Drive gate, RG1-RG3...Answer reception gate, RQ1-RQ3...Memory access request, AD1-AD3...Memory address data, LEN... Logical memory device name section, P
EN... Physical memory device name section, wD1~w
D3...Memory answer data, ACK...
...Access condition check circuit, DT1 to DT3...
...Memory drive timing signal, RT1 to RT3...
...Answer reception timing signal, mab...
・Memory device internal address section, ms... Access time display signal, rn C1 to rn C3...
Memory access circuit activation signal, eno~enn~memory device designation signal, ack...Access enable signal, C
LK・・・・・・Clock, C1□" 13 "21
p C23+C311C32""" comparison circuit, G1o~
G6. G2o~G25. G3゜~G35...Gate, S to SR3...Register, SBl~S
B3...-1 circuit, ZD1 to ZD3...
・Zero detection circuit, sr1~sr3...SR1~
Output of SR3, sbl ~Sb3"""SB1 ~SB3
output, zd1 to Zd3...output of ZD1 to ZD3.

Claims (1)

[Claims] 1. In an information processing system that includes at least one processing device and a plurality of memory devices having different access times, and in which the alpha device and the plurality of memory devices are connected via the same bus, one of the memory devices in the texture device The memory access control circuit has a memory speed display circuit correspondingly having access time information, and a plurality of memory access control circuits for each type of memory access such as instruction read access, operand data access, and access from a data channel. A counter that counts the response time of the memory currently being accessed and a memory access signal) are used to compare the access time information of the requested memory device with the counter output of other memory access control circuits. and a plurality of comparison circuits, and when a request to access another memory device occurs while the alpha processing device is accessing one of the memory devices, the output of the memory speed display circuit and the memory access A memory control method characterized in that counter outputs of control circuits are compared to control acceptance of an access request to the other memory device.