JPH0451489Y2 - - Google Patents
Info
- Publication number
- JPH0451489Y2 JPH0451489Y2 JP1987049712U JP4971287U JPH0451489Y2 JP H0451489 Y2 JPH0451489 Y2 JP H0451489Y2 JP 1987049712 U JP1987049712 U JP 1987049712U JP 4971287 U JP4971287 U JP 4971287U JP H0451489 Y2 JPH0451489 Y2 JP H0451489Y2
- Authority
- JP
- Japan
- Prior art keywords
- leads
- support plate
- external
- external lead
- unconnected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 26
- 238000007789 sealing Methods 0.000 claims description 13
- 238000009413 insulation Methods 0.000 claims description 2
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 229920005989 resin Polymers 0.000 description 11
- 239000011347 resin Substances 0.000 description 11
- 238000005452 bending Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000003139 buffering effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005219 brazing Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910020836 Sn-Ag Inorganic materials 0.000 description 1
- 229910020988 Sn—Ag Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 239000004945 silicone rubber Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
本考案は、パワートランジスタと厚膜回路とを
組み合せて樹脂封止したハイブリツドIC、これ
に類似の回路装置等の絶縁物封止型回路装置に関
し、更に詳細には、外部リード間の耐圧向上に関
する。[Detailed description of the invention] [Field of industrial application] The present invention is applicable to insulator-encapsulated circuit devices such as hybrid ICs that combine power transistors and thick film circuits and encapsulate them with resin, and similar circuit devices. More specifically, the present invention relates to improving the withstand voltage between external leads.
パワートランジスタチツプの厚膜回路とを組み
合せた従来の樹脂封止型ハイブリツドICは、第
５図に示す如く構成されている。第５図に示され
ているリードフレームから形成された金属製の放
熱支持板１には２つの孔２が設けられている。７
本の外部リード３，４，５，６，７，８，９は支
持板１の一端（下端）側近傍から第１の方向に沿
つて伸びるように導出され、かつ第１の方向に直
交する第２の方向に沿つて互いに並置されてい
る。外部リード３，４，５，７，８，９は支持板
１と一体に形成されていないので、これ等を非連
結外部リードと呼び、一方、外部リード６は支持
板１と一体に形成されているので、これを連結外
部リードと呼ぶことにする。１０は厚膜素子を含
む回路装置であつて、支持板１の一端側寄りに固
着されている。なお、この回路装置１０は保護樹
脂１１で被覆されている。パワートランジスタチ
ツプ１２は、支持板１の一端側から見て回路装置
１０よりも遠い側の部分にろう材１３（例えば
Pb−Sn−Ag半田）で固着されている。トランジ
スタチツプ１２は支持板１の第１の方向に伸びる
中心線２２上に配置されている。通常、トランジ
スタチツプ１２は保護樹脂で被覆されるが、第５
図では省略されている。内部リード１４，１５，
１８，１９は回路装置１０と外部リード３，４，
８，９とを接続し、内部リード１６，１７は回路
装置１０を経由してパワートランジスタチツプ１
２と外部リード５，７とを接続している。樹脂封
止体２０は、回路基盤１０、パワートランジスタ
チツプ１２、内部リード１４〜１９、及び外部リ
ード３〜９の支持板１の近傍部分を封止してい
る。なお、支持板１の２つの貫通孔２に対応して
２つの取付孔２１が樹脂封止体２０に生じてい
る。
A conventional resin-sealed hybrid IC that combines a power transistor chip with a thick film circuit is constructed as shown in FIG. Two holes 2 are provided in a metal heat dissipation support plate 1 formed from a lead frame shown in FIG. 7
The external leads 3, 4, 5, 6, 7, 8, and 9 of the book are led out from near one end (lower end) side of the support plate 1 so as to extend along the first direction, and are perpendicular to the first direction. juxtaposed with each other along the second direction. Since the external leads 3, 4, 5, 7, 8, and 9 are not formed integrally with the support plate 1, they are called non-coupled external leads.On the other hand, the external lead 6 is formed integrally with the support plate 1. Therefore, we will call this a connected external lead. Reference numeral 10 denotes a circuit device including a thick film element, and is fixed to one end of the support plate 1. Note that this circuit device 10 is covered with a protective resin 11. The power transistor chip 12 has a brazing material 13 (for example,
It is fixed with Pb-Sn-Ag solder). The transistor chip 12 is arranged on a center line 22 of the support plate 1 extending in a first direction. Normally, the transistor chip 12 is coated with a protective resin, but the fifth
It is omitted in the figure. Internal leads 14, 15,
18, 19 are the circuit device 10 and external leads 3, 4,
8 and 9, and the internal leads 16 and 17 are connected to the power transistor chip 1 via the circuit device 10.
2 and external leads 5 and 7 are connected. The resin sealing body 20 seals the circuit board 10, the power transistor chip 12, the internal leads 14-19, and the external leads 3-9 in the vicinity of the support plate 1. Note that two attachment holes 21 are formed in the resin sealing body 20 corresponding to the two through holes 2 of the support plate 1.
ところで、第５図に示す如きハイブリツドIC
を回路基盤に装着する場合には、一般に外部リー
ド３〜９を折り曲げる。もし、外部リード３〜９
の折り曲げ位置が樹脂封止体２０に接近すると、
外部リード３〜９と樹脂封止体２０との間に剥離
が生じたり、樹脂封止体２０にクラツクが発生す
る。この問題は外部リード３〜９の折り曲げ位置
を樹脂封止体２０から離らかすことによつて解決
される。第５図の例では、非連結外部リード３〜
５及び７〜９に幅狭部２４と幅広部２３を設け、
連結外部リード６においても幅狭部２６と幅広部
２５を設け、各幅狭部２４，２６で折り曲げる。
幅広部２３，２５はリード折り曲げ時の応力緩衝
部分として機能し、樹脂封止体２０の剥離及びク
ラツクを防止する。 By the way, a hybrid IC as shown in Figure 5
When mounting the circuit board on a circuit board, the external leads 3 to 9 are generally bent. If external leads 3 to 9
When the bending position approaches the resin sealing body 20,
Peeling may occur between the external leads 3 to 9 and the resin molding body 20, or cracks may occur in the resin molding body 20. This problem can be solved by moving the bending positions of the external leads 3 to 9 away from the resin sealing body 20. In the example of FIG. 5, unconnected external leads 3 to
A narrow part 24 and a wide part 23 are provided at 5 and 7 to 9,
The connecting external lead 6 also has a narrow portion 26 and a wide portion 25, and is bent at each of the narrow portions 24, 26.
The wide portions 23 and 25 function as stress buffering portions when bending the leads, and prevent peeling and cracking of the resin sealing body 20.
なお、連結外部リード６の幅広部２５の幅は、
支持板１を支えるために非連結外部リード３〜５
及び７〜９の幅広部２３の幅よりも大きい。外部
リード３〜９の配列ピツチは標準化された2.54mm
（インチピツチ）である。但し、外部リード３と
４との間及び７と８との間は絶縁耐圧を高めるた
めに２倍のピツチになつている。 Note that the width of the wide portion 25 of the connected external lead 6 is as follows:
Unconnected external leads 3 to 5 to support the support plate 1
and larger than the width of the wide portion 23 of Nos. 7 to 9. The array pitch of external leads 3 to 9 is standardized to 2.54mm.
(inch pitch). However, the pitch between external leads 3 and 4 and between external leads 7 and 8 is doubled in order to increase the withstand voltage.
第５図のハイブリツドICにおいて、パワート
ランジスタチツプ１２が数百ボルトの高耐圧品で
ある場合には、コレクタに接続されている連結外
部リード６とエミツタに接続されている非連結外
部リード５及びベースに接続されている非連結外
部リード７との間の絶縁耐圧を高めなければなら
ない。非連結外部リード３と４との間又は７と８
との間のように外部リードを１本除去して標準ピ
ツチの２倍のピツチとすることが考えられるが、
必然的にハイブリツドICの小型化が阻害される。
In the hybrid IC shown in FIG. 5, when the power transistor chip 12 is a high-voltage product of several hundred volts, the connected external lead 6 connected to the collector, the unconnected external lead 5 connected to the emitter, and the base It is necessary to increase the dielectric strength voltage between the external lead 7 and the unconnected external lead 7 connected to the external lead 7. Between unconnected external leads 3 and 4 or 7 and 8
It is conceivable to remove one external lead and make the pitch twice the standard pitch, as shown between
This inevitably hinders the miniaturization of hybrid ICs.
上述の如き問題を解決するために、例えば、実
開昭58−6789号公報に開示されているように、非
連結外部リード５の幅広部２３の右側突出部を除
去して左側突出部を大きくし、また非連結外部リ
ード７の幅広部２３の左側突出部を除去して右側
突出部を大きくすることが考えられる。しかし、
連結外部リード６の幅広部２５の幅は外の非連結
外部リードの幅広部２３よりも幅が広いので、十
分な間隔を得ることができない。また、非連結外
部リード４と５との間隔が狭くなるという問題が
生じる。 In order to solve the above-mentioned problems, for example, as disclosed in Japanese Utility Model Application No. 58-6789, the right side protrusion of the wide part 23 of the uncoupled external lead 5 is removed and the left side protrusion is enlarged. However, it is also conceivable to remove the left side protrusion of the wide portion 23 of the uncoupled external lead 7 and make the right side protrusion larger. but,
Since the width of the wide portion 25 of the connected external lead 6 is wider than the wide portion 23 of the outer unconnected external lead, a sufficient distance cannot be obtained. Further, a problem arises in that the distance between the unconnected external leads 4 and 5 becomes narrow.
また、トランジスタチツプ１２と回路装置１０
とを含む装置において、これ等と外部リードとの
電気的接続が容易且つ確実に達成できれば好都合
である。 Also, the transistor chip 12 and the circuit device 10
It would be advantageous if electrical connection between these and external leads could be easily and reliably achieved in a device including the above.
そこで、本考案の目的は、耐圧を低下させるこ
となしに連結外部リードによる支持板の支持強度
を高め、且つ内部リードによる接続を容易に達成
することができる絶縁物封止型回路装置を提供す
ることにある。 SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an insulator-sealed circuit device that can increase the support strength of a support plate by connecting external leads without reducing the withstand voltage, and can easily achieve connection using internal leads. There is a particular thing.
［問題点を解決するための手段］
上記目的を達成するための本考案は、実施例を
示す図面の符号を参照して説明すると、連結外部
リード３３を有する支持板３１と、前記支持板３
１の一端側近傍から第１の方向に沿つて伸び、か
つ前記第１の方向に直交する第２の方向に沿つて
互いに並置され、かつ前記連結外部リード３３に
対しても並置されている複数の非連結外部リード
３４〜３９と、前記支持板３１に固着された半導
体チツプ４２及び回路装置４０と、前記半導体チ
ツプ４２の上面側の電極を前記複数の非連結外部
リード３４〜３９から選択されたものに接続する
ための第１の内部リード４４，４５と、前記回路
装置４０を前記複数の非連結外部リード３４〜３
９から選択されたものに接続するための第２の内
部リード４６〜４９と、前記支持板３１、前記連
結外部リード３３及び前記非連結外部リード３４
〜３９の一部、前記半導体チツプ４２、前記回路
装置４０、及び前記第１及び第２の内部リード４
４，４５，４６〜４９を封止する絶縁封止体５０
とから成り、前記連結外部リード３３及び前記非
連結外部リード３４〜３９が幅広部５４，５６と
幅狭部５５，５７とをそれぞれ有し、前記幅広部
５４，５６は前記支持板３１に近い方に配設さ
れ、前記絶縁封止体５０が前記幅広部５４，５６
の一部を覆うが、前記幅広部５４，５６の残部と
前記幅狭部５５，５７とを覆わないように形成さ
れている絶縁物封止型回路装置において、前記連
結外部リード３３と前記非連結外部リード３４〜
３９とから成る外部リード配列の一方の端に前記
連結外部リード３３が配置されており、前記連結
外部リード３３の前記幅広部５４の前記非連結外
部リード３４〜３９側の端が、前記連結外部リー
ド３３の幅狭部５５の前記非連結外部リード３４
〜３９側の端の延長線５８から突出しないよう
に、又は前記連結外部リード３３の前記幅広部５
４の前記非連結外部リード３４〜３９側の端が前
記幅狭部５５の端の前記延長線５８から突出する
幅ａを、前記連結外部リード３３の前記幅広部５
４の反対側の端が前記連結外部リード３３の前記
幅狭部５５の反対側の端の延長線５９から突出す
る幅ｂよりも小さくなるように前記連結外部リー
ド３３の幅広部５４が形成されており、前記半導
体チツプ４２は前記支持板３１の前記第１の方向
に延びる中心線５２と前記支持板３１の前記連結
外部リード５５が設けられている側の側面との間
に配置されており、前記回路装置４０は前記支持
板３１の前記半導体チツプ４２が配置されている
領域と前記支持板３１の前記一端側との間の領域
及び前記中心線５２を横切る領域を含む部分に配
置されており、前記半導体チツプ４２の下面の電
極は前記支持板３１に電気的に接続されており、
前記半導体チツプ４２の上面の電極４２ａ，４２
ｂは前記回路装置４０を経由して前記連結外部リ
ード３３の隣りの前記非連結外部リード３４，３
５に前記第１の内部リード４４，４５によつて接
続されていることを特徴とする絶縁物封止型回路
装置に係わるものである。なお、半導体チツプ４
２の上面の電極を１つとすること又は複数とする
ことが可能であり、更に第１の内部リードを１本
とすること又は複数本とすることが可能である。[Means for Solving the Problems] To achieve the above object, the present invention will be described with reference to the reference numerals in the drawings showing the embodiments.
1 extending along a first direction from near one end side, and arranged in parallel with each other along a second direction orthogonal to the first direction, and also arranged in parallel with the connecting external lead 33. unconnected external leads 34 to 39, semiconductor chip 42 and circuit device 40 fixed to support plate 31, and electrodes on the upper surface side of semiconductor chip 42 selected from among the plurality of unconnected external leads 34 to 39. first internal leads 44, 45 for connecting the circuit device 40 to the plurality of unconnected external leads 34-3.
9, the support plate 31, the connected external lead 33, and the unconnected external lead 34.
39, the semiconductor chip 42, the circuit device 40, and the first and second internal leads 4.
Insulating sealing body 50 that seals 4, 45, 46 to 49
The connected external lead 33 and the unconnected external leads 34 to 39 have wide parts 54, 56 and narrow parts 55, 57, respectively, and the wide parts 54, 56 are close to the support plate 31. The insulating sealing body 50 is disposed on the wide portions 54, 56.
In the insulator-sealed circuit device, which is formed so as to cover a part of the wide portions 54, 56 and not cover the narrow portions 55, 57, the connection external lead 33 and the non-width portion Connected external lead 34~
The connected external lead 33 is disposed at one end of an external lead array consisting of The unconnected external lead 34 of the narrow portion 55 of the lead 33
-39 side end extension line 58, or the wide part 5 of the connecting external lead 33.
The wide portion 5 of the connected external lead 33 has a width a in which the end of the non-connected external leads 34 to 39 side projects from the extension line 58 of the end of the narrow width portion 55.
The wide portion 54 of the connecting external lead 33 is formed such that the end opposite to the narrow portion 55 of the connecting external lead 33 is smaller than the width b protruding from the extension line 59 of the opposite end of the narrow portion 55 of the connecting external lead 33. The semiconductor chip 42 is disposed between a center line 52 of the support plate 31 extending in the first direction and a side surface of the support plate 31 on the side where the connecting external leads 55 are provided. , the circuit device 40 is disposed in a portion of the support plate 31 including a region between the region where the semiconductor chip 42 is disposed and the one end side of the support plate 31 and a region crossing the center line 52. an electrode on the lower surface of the semiconductor chip 42 is electrically connected to the support plate 31;
Electrodes 42a, 42 on the upper surface of the semiconductor chip 42
b is connected to the unconnected external leads 34 and 3 adjacent to the connected external lead 33 via the circuit device 40;
The present invention relates to an insulator-sealed circuit device characterized in that the circuit device is connected to the first internal leads 44 and 45 by the first internal leads 44 and 45. Note that the semiconductor chip 4
It is possible to have one or more electrodes on the top surface of 2, and it is also possible to have one or more first internal leads.
上記考案における連結外部リード３３は、外部
リード配列の最も端に配置され、幅広部５４が非
対称に形成され、非連結外部リード３４〜３９が
配置されない側に幅広部５４の突出部が十分に大
きく設けられている。従つて、支持板３１を支え
るために要求される幅を十分に得ることができ
る。連結外部リード３３とこれに隣接する非連結
外部リード３４との間は連結外部リード３３の幅
広部５４を非対称にすることによつて十分に離
れ、所望の耐圧を得ることができる。
The connected external lead 33 in the above device is arranged at the end of the external lead array, the wide part 54 is formed asymmetrically, and the protruding part of the wide part 54 is sufficiently large on the side where the unconnected external leads 34 to 39 are not arranged. It is provided. Therefore, a sufficient width required to support the support plate 31 can be obtained. By making the wide portion 54 of the connected external lead 33 asymmetrical, the connected external lead 33 and the adjacent unconnected external lead 34 are sufficiently separated, and a desired withstand voltage can be obtained.
次に、第１図及び第２図に基づいて本考案の実
施例に係わるスイツチングレギユレータ用の樹脂
封止型ハイブリツドICを説明する。第１図に示
すハイブリツドICは、リードフレームに基づい
て形成されたNi被覆Cu材から成る支持板３１を
含む。この支持板３１の平面サイズは、横22×縦
19mmである。支持板３１の第１の方向に伸びる中
心線５２の一方の側に貫通孔３２が設けられてい
る。
Next, a resin-sealed hybrid IC for a switching regulator according to an embodiment of the present invention will be explained based on FIGS. 1 and 2. The hybrid IC shown in FIG. 1 includes a support plate 31 made of Ni-coated Cu material and formed based on a lead frame. The planar size of this support plate 31 is 22 in width x 22 in height.
It is 19mm. A through hole 32 is provided on one side of a center line 52 extending in the first direction of the support plate 31 .
支持板３１の一端側近傍から第１の方向に沿つ
て伸びる連結外部リード３３と６本の非連結外部
リード３４，３５，３６，３７，３８，３９が設
けられている。合計７本の外部リード３３〜３９
は第１の方向（ｙ軸方向）に直交する第２の方向
（ｘ軸方向）に互いに並置され、インチピツチで
９ピン基準にリード列から２本抜いた配列とさ
れ、中心線52の一方の側に第１の群の外部リード
３７，３８，３９が配置され、他方の側に残りの
４本の第２の群の外部リード３３，３４，３５，
３６が配置され、第１の群と第２の群は個々のリ
ード間隔よりも広い間隔Ｌで区画されている。各
外部リード３３〜３９は支持板３１と同一材料か
ら成る。 A connected external lead 33 and six unconnected external leads 34, 35, 36, 37, 38, and 39 are provided extending along the first direction from near one end of the support plate 31. Total of 7 external leads 33-39
are arranged in parallel with each other in the second direction (x-axis direction) perpendicular to the first direction (y-axis direction), and are arranged in inch pitch with two leads removed from the lead row based on 9 pins. The first group of external leads 37, 38, 39 are arranged on one side, and the remaining four second group external leads 33, 34, 35,
36 are arranged, and the first group and the second group are separated by a distance L that is wider than the distance between the individual leads. Each of the external leads 33 to 39 is made of the same material as the support plate 31.
支持板３１の一端側寄りに平面形状長方形の厚
膜素子を含む回路装置４０がエポキシ樹脂系接着
剤によつて固着されている。この回路装置４０
は、セラミツク基板上に厚膜導体、厚膜抵抗等を
形成し、更にトランジスタ、ホトカプラー等を装
着したスイツチングレギユレータの制御回路のハ
イブリツドICである。回路装置４０を覆うシリ
コンラバーから成る保護樹脂４１は、内部リード
４４〜４９のワイヤボンデイングが終了した後に
設けられる。 A circuit device 40 including a thick film element having a rectangular planar shape is fixed to one end of the support plate 31 with an epoxy resin adhesive. This circuit device 40
This is a hybrid IC for a control circuit of a switching regulator, which has thick film conductors, thick film resistors, etc. formed on a ceramic substrate, and is further equipped with transistors, photocouplers, etc. A protective resin 41 made of silicone rubber that covers the circuit device 40 is provided after wire bonding of the internal leads 44 to 49 is completed.
支持板３１の一端側から見て回路装置４０より
も遠い部分であり且つ中心線５２の他方の側にス
イツチングレギユレータのスイツチング素子とし
てのパワートランジスタチツプ４２が配置され、
この下面のコレクタ電極が融点309℃のPb−Sn−
Ag系ろう材４３即ち融点の高い半田によつて固
着されている。このパワートランジスタチツプ４
２はダイボンデイング法で固着されているために
ろう材４３がチツプ以上に広がつている。半導体
チツプとしてのパワートランジスタチツプ４２及
び回路装置４０の配置を更に詳しく説明すると、
パワートランジスタチツプ４２は支持板３１の第
１の方向に延びる中心線５２と支持板３１の連結
外部リード５５が設けられている側の側面との間
に配置されており、回路装置４０は支持板３１の
パワートランジスタチツプ４２が配置されている
領域と支持板３１の一端側との間の領域及び中心
線５２を横切る領域を含む部分に配置されてい
る。 A power transistor chip 42 as a switching element of a switching regulator is disposed at a part farther from the circuit device 40 when viewed from one end of the support plate 31 and on the other side of the center line 52.
This lower collector electrode is Pb−Sn− with a melting point of 309℃.
It is fixed by Ag-based brazing material 43, that is, solder with a high melting point. This power transistor chip 4
2 is fixed by the die bonding method, so that the brazing material 43 has spread beyond the chip. The arrangement of the power transistor chip 42 as a semiconductor chip and the circuit device 40 will be explained in more detail.
The power transistor chip 42 is disposed between the center line 52 of the support plate 31 extending in the first direction and the side surface of the support plate 31 on which the connecting external leads 55 are provided, and the circuit device 40 is mounted on the support plate 31. It is disposed in a region including a region between the region where the 31 power transistor chips 42 are arranged and one end side of the support plate 31, and a region crossing the center line 52.
Al細線から成る２本の第１の内部リード４４，
４５はパワートランジスタチツプ４２の上面の電
極としてのエミツタボンデイングパツド４２ａ及
びベースボンデイングパツド４２ｂと外部リード
３４，３５との間を回路装置４０を経由して接続
している。残りの４本のAl細線から成る第２の
内部リード４６，４７，４８，４９は回路装置４
０と外部リード３６，３７，３８，３９との間を
接続している。なお、各内部リード４４〜４９は
超音波ウエツジボンデイング法により接続されて
いる。回路装置４０に対する内部リード４４〜４
９の接続はセラミツク基板上の導体になされてい
る。 Two first internal leads 44 made of thin Al wires,
Reference numeral 45 connects the emitter bonding pad 42a and base bonding pad 42b, which serve as electrodes on the upper surface of the power transistor chip 42, to the external leads 34 and 35 via the circuit device 40. The second internal leads 46, 47, 48, 49 consisting of the remaining four thin Al wires are connected to the circuit device 4.
0 and external leads 36, 37, 38, and 39. The internal leads 44 to 49 are connected by ultrasonic wedge bonding. Internal leads 44-4 to circuit device 40
Connections 9 are made to conductors on the ceramic substrate.
第１図で点線で示すエポキシ樹脂から成る絶縁
封止体５０は、平面サイズ横25×縦22mmを有し
て、回路装置４０、パワートランジスタチツプ４
２、外部リード３３〜３９の一部を覆うように形
成されている。この絶縁封止体５０は、支持体３
１の上面のみでなく、下面側も薄く覆つている。
絶縁封止体５０には、支持板３１の孔３２に対応
して取付孔５１が設けられ、更に沿面距離増大用
凹部５３が外部リード３６と３７との間に設けら
れている。 The insulating sealing body 50 made of epoxy resin shown by the dotted line in FIG.
2. It is formed to partially cover the external leads 33 to 39. This insulating sealing body 50 is
Not only the upper surface of 1 but also the lower surface side is thinly covered.
The insulating seal 50 is provided with a mounting hole 51 corresponding to the hole 32 of the support plate 31, and furthermore, a recess 53 for increasing the creepage distance is provided between the external leads 36 and 37.
支持板３１に一体化されている連結外部リード
３３は、リードフレーム状態の時に支持板３１を
支えるため及びリード折り曲げ時の応力緩衝効果
を得るための幅広部５４とここに連続する幅狭部
５５とから成る。非連結外部リード３４〜３９も
同様に幅広部５６と幅狭部５７とから成る。な
お、幅狭部５５，５７はリードフレーム状態にお
いて相互に連結されているので、支持板３１及び
その他の部分を支えることができる。 The connecting external lead 33 integrated with the support plate 31 has a wide part 54 for supporting the support plate 31 when in a lead frame state and for obtaining a stress buffering effect when bending the lead, and a narrow part 55 continuous thereto. It consists of The unconnected external leads 34 to 39 similarly consist of a wide portion 56 and a narrow portion 57. Note that since the narrow parts 55 and 57 are connected to each other in the lead frame state, they can support the support plate 31 and other parts.
第１図において第５図の従来例と明らかに相違
している点は、連結外部リード３３が外部リード
配列の最も左端に配置され、且つこの幅広部５４
が非対称に形成されていることである。 What is clearly different from the conventional example shown in FIG. 5 in FIG.
is formed asymmetrically.
第２図は連結外部リード３３とこれに隣接する
非連結外部リード３４，３５を詳しく示すもので
ある。連結外部リード３３の幅広部５４の右側突
出部の幅ａは左側突出部の幅ｂよりも小さい。即
ち、幅狭部５５の右端延長線５８と幅広部５４の
右端との間に位置する突出部の幅ａは幅狭部５５
の左端延長線５９と幅広部５４の左端との間に位
置する突出部の幅ｂよりも大幅に小さい。連結外
部リード３３の幅広部５４の幅W1は2.2mmであ
り、非連結外部リード３４〜３９の幅広部５６の
幅W2は1.2mmである。なお、連結外部リード３３
と支持板３１との間には支持板３１を安定的に支
えるために幅広部５４の幅W1よりも更に広い幅
W3を有する部分６０が設けられている。この部
分６０は絶縁封止体５０の中に埋設されるので、
絶縁耐力には実質的に無関係な部分である。 FIG. 2 shows in detail the connected external lead 33 and the unconnected external leads 34 and 35 adjacent thereto. The width a of the right side protrusion of the wide portion 54 of the connecting external lead 33 is smaller than the width b of the left side protrusion. That is, the width a of the protrusion located between the right end extension line 58 of the narrow part 55 and the right end of the wide part 54 is equal to the width a of the narrow part 55.
The width b of the protrusion located between the left end extension line 59 and the left end of the wide portion 54 is significantly smaller than the width b of the protrusion. The width W 1 of the wide portion 54 of the connected external lead 33 is 2.2 mm, and the width W 2 of the wide portion 56 of the unconnected external leads 34 to 39 is 1.2 mm. In addition, the connecting external lead 33
and the support plate 31 has a width wider than the width W 1 of the wide part 54 in order to stably support the support plate 31.
A portion 60 having W 3 is provided. Since this portion 60 is buried within the insulating sealing body 50,
This is a part that is substantially unrelated to dielectric strength.
非連結外部リード３４の幅広部５６は対称に形
成され、左右の突出幅ｃ，ｄはそれぞれ0.2mmで
ある。連結外部リード３３の右側突出幅ａは0.2
mm、左側突出幅ｂは1.2mmである。絶縁封止体５
０から露出する部分における連結外部リード３３
と非連結外部リード３４との最小相互間隔l1、及
び非連結外部リード３４，３５の最小相互間隔l2
は共に1.34mmである。 The wide portion 56 of the unconnected external lead 34 is formed symmetrically, and the left and right protruding widths c and d are each 0.2 mm. The right side protrusion width a of the connecting external lead 33 is 0.2
mm, and the left protrusion width b is 1.2 mm. Insulating sealing body 5
Connection external lead 33 in the part exposed from 0
and the unconnected external lead 34, and the minimum mutual interval l 2 between the unconnected external leads 34 and 35 .
Both are 1.34mm.
この実施例のハイブリツドICは次の利点を有
する。 The hybrid IC of this embodiment has the following advantages.
(1) 連結外部リード３３の幅広部５４の幅W1を
十分に大きくしても、隣接する非連結外部リー
ド３４との相互間隔l1即ち絶縁封止体５０にお
ける相互間の沿面距離が小さくならない。従つ
て、連結外部リード３３の支持板３１を支える
作用及びリード折り曲げ時の応力緩衝作用と、
非連結外部リード３４〜３９のリード折り曲げ
時の応力緩衝作用を犠牲にしないで高耐圧化を
図ることができる。(1) Even if the width W 1 of the wide portion 54 of the connected external lead 33 is sufficiently large, the mutual distance l 1 between the adjacent unconnected external leads 34, that is, the creepage distance between them in the insulating seal 50 is small. No. Therefore, the effect of supporting the support plate 31 of the connecting external lead 33 and the stress buffering effect when bending the lead,
High voltage resistance can be achieved without sacrificing the stress buffering effect of the unconnected external leads 34 to 39 when the leads are bent.
(2) パワートランジスタチツプ４２を支持板３１
の中心線５２よりも左側領域に配置したので、
内部リード４４，４５によるエミツタ及びベー
スと非連結外部リード３４及び３５との接続を
ワイヤボンダーによつて容易に達成することが
できる。即ち、もしパワートランジスタチツプ
４２が中心線５２上に位置すれば、内部リード
４４，４５を中心線５２に対して大きな角度を
有するように引き回さなければならず、ワイヤ
ボンデイング作業が煩雑化し、生産性が低下す
るが、本実施例ではこの種の問題が生じない。(2) Support plate 31 for power transistor chip 42
Since it is placed in the area to the left of the center line 52 of
Connection between the emitter and base via the internal leads 44 and 45 and the uncoupled external leads 34 and 35 can be easily achieved using a wire bonder. That is, if the power transistor chip 42 is located on the center line 52, the internal leads 44 and 45 must be routed at a large angle with respect to the center line 52, which complicates the wire bonding work. Although productivity decreases, this type of problem does not occur in this embodiment.
本考案は上述くの実施例に限定されるものでな
く、例えば次の変形が可能なものである。
The present invention is not limited to the above-described embodiments, but can be modified as follows, for example.
(1) 第３図に示す如く、連結外部リード３３の幅
広部５４の右側に突出部を設けずに、左側のみ
に突出部を設けてもよく、また、非連結外部リ
ード３４の幅広部５６に左側突出部を設けない
ようにしてもよい。第３図は第２図に於ける突
出幅ａ及びｃを零になし、幅W1及びW2は第２
図と同一にした構造であるので、絶縁封止体５
０から導出される部分における外部リード３
３，３４の最小相互間隔l1は1.74mm、外部リー
ド３４，３５の最小相互間隔l2は1.14mmである。
従つて、コレクタが接続される連結外部リード
３３とエミツタが接続される非連結外部リード
３４との間の絶縁耐圧を大幅に高めることがで
きる。なお、非連結リード３４と３５との間隔
l2が狭くなるが、ベース・エミツタ間の耐圧は
数十ボルト以下で十分であるから、不都合が生
じない。(1) As shown in FIG. 3, the protrusion may not be provided on the right side of the wide portion 54 of the connected external lead 33, and the protrusion may be provided only on the left side. The left side protrusion may not be provided. In Fig. 3, the protrusion widths a and c in Fig. 2 are set to zero, and the widths W 1 and W 2 are
Since the structure is the same as that shown in the figure, the insulation sealing body 5
External lead 3 in the part derived from 0
The minimum mutual distance l 1 between the external leads 34 and 34 is 1.74 mm, and the minimum mutual distance l 2 between the external leads 34 and 35 is 1.14 mm.
Therefore, the dielectric strength between the connected external lead 33 to which the collector is connected and the unconnected external lead 34 to which the emitter is connected can be greatly increased. In addition, the distance between the unconnected leads 34 and 35
l 2 becomes narrower, but since the withstand voltage between the base and emitter is sufficient to be several tens of volts or less, no inconvenience occurs.
(2) 第２図において、ａ＝ｃとせずに、ａ＜ｃと
してもよい。また、ｃ＝ｄとせずにｃ＜ｄとし
てもよい。(2) In FIG. 2, instead of a=c, a<c may be used. Furthermore, instead of setting c=d, it is also possible to set c<d.
(3) 第４図に示す如く、連結外部リード３３の幅
広部５４の右端を、幅狭部５５の右端の延長線
よりも距離ａだけ左側に位置させてもよい。第
４図では非連結リード３４が左側突出部を有さ
ないので、連結外部リード３３と非連結外部リ
ード３４との沿面距離が1.94mmになる。なお、
第４図のW1，W2は第２図と同一値に設定され
ている。(3) As shown in FIG. 4, the right end of the wide portion 54 of the connecting external lead 33 may be located to the left of the extension line of the right end of the narrow portion 55 by a distance a. In FIG. 4, since the unconnected lead 34 does not have a left side protrusion, the creepage distance between the connected external lead 33 and the unconnected external lead 34 is 1.94 mm. In addition,
W 1 and W 2 in FIG. 4 are set to the same values as in FIG. 2.
(4) 非連結外部リード３４をベースリード、非連
結外部リードをエミツタリードとする場合にも
適用可能である。(4) It is also applicable when the unconnected external lead 34 is a base lead and the unconnected external lead is an emitter lead.
(5) 回路装置４０の代りにモノリシツクIC又は
個別半導体素子を装着する場合にも適用可能で
ある。パワートランジスタチツプ４２の代りに
サイリスタ、FET等の半導体素子を装着する
場合にも適用可能である。(5) It is also applicable to the case where a monolithic IC or an individual semiconductor element is installed in place of the circuit device 40. It is also applicable to cases where a semiconductor element such as a thyristor or FET is installed in place of the power transistor chip 42.
(6) 連結外部リード３３を支持板３１の右端側に
移し、パワートランジスタチツプ４２も支持板
３１の右側に移してもよい。(6) The connecting external lead 33 may be moved to the right end side of the support plate 31, and the power transistor chip 42 may also be moved to the right side of the support plate 31.
(7) 回路装置４０の基板を支持板３１と外部リー
ド３４〜３９とにまたがるように配置し、内部
リードを使用しないで外部リード３４〜３９に
対する接続を行つてもよい。(7) The substrate of the circuit device 40 may be arranged so as to straddle the support plate 31 and the external leads 34 to 39, and connections to the external leads 34 to 39 may be made without using the internal leads.
本考案の効果を図面の符号を参照して説明する
と次の通りである。
The effects of the present invention will be explained below with reference to the symbols in the drawings.
(イ) 半導体チツプ４２が支持板３１の中心線５２
と連結外部リード３３側の側面との間に配置さ
れ、半導体チツプ４２の上面の電極４２ａ，４
２ｂは回路装置４０を介して連結外部リード３
３の隣りの非連結外部リード３４，３５に第１
の内部リード４４，４５によつて接続されてい
るので、支持板３１の中心線５２に対する第１
の内部リード４４，４５の傾きを小さくするこ
とができ、この接続が容易になる。また、第１
の内部リード４４，４５による短絡事故が発生
しにくくなる。(a) The semiconductor chip 42 is aligned with the center line 52 of the support plate 31.
electrodes 42a, 4 on the upper surface of the semiconductor chip 42.
2b is connected to the external lead 3 via the circuit device 40.
The first unconnected external leads 34 and 35 adjacent to
are connected by internal leads 44 and 45, so that the first
The inclination of the internal leads 44 and 45 can be reduced, making this connection easier. Also, the first
Short circuit accidents due to the internal leads 44 and 45 are less likely to occur.
(ロ) 半導体チツプ４２を支持板３１の連結外部リ
ード３３寄りに配置したので、半導体チツプ４
２に接続された外部リード３３，３４，３５を
一方の端側に集中させることができる。これに
より、外部回路への接続が容易になる。(b) Since the semiconductor chip 42 is placed closer to the connecting external lead 33 of the support plate 31, the semiconductor chip 42
The external leads 33, 34, 35 connected to 2 can be concentrated on one end side. This facilitates connection to external circuits.
(ハ) 連結外部リード３３の幅広部５４は非連結外
部リード３４が配置されていない側に突出する
部分を形成することによつて拡大されているの
で、幅広部５４を十分に広くしても沿面距離の
低下即ち耐圧の低下を伴なわない。特に半導体
チツプ４２に高い電圧が印加される場合には、
半導体チツプ４２の上面側の電極４２ａが接続
される非連結外部リード３４と半導体チツプ４
２の下面側の電極が接続される連結外部リード
３３との間の耐圧を十分に確保することが必要
になるが、本考案のように構成することによ
り、大型化を抑制して必要な耐圧を得ることが
可能になる。(c) The wide portion 54 of the connected external lead 33 is enlarged by forming a portion that protrudes toward the side where the unconnected external lead 34 is not disposed, so even if the wide portion 54 is made sufficiently wide, No reduction in creepage distance or withstand voltage. Especially when a high voltage is applied to the semiconductor chip 42,
The uncoupled external lead 34 to which the electrode 42a on the upper surface side of the semiconductor chip 42 is connected and the semiconductor chip 4
It is necessary to ensure sufficient withstand voltage between the electrode on the lower surface side of 2 and the connecting external lead 33 to which it is connected, but by configuring it as in the present invention, the required withstand voltage can be suppressed while suppressing the increase in size. It becomes possible to obtain.
(ニ) 回路装置４０は支持板３１の中心線５２を横
切るように延びているので、非連結外部リード
３６〜３９に対する第２の内部リード４６〜４
９による接続を容易に達成することができる。(d) Since the circuit device 40 extends across the center line 52 of the support plate 31, the second internal leads 46-4 are connected to the unconnected external leads 36-39.
9 connection can be easily achieved.
第１図は本考案の実施例に係わる樹脂封止型ハ
イブリツドICを示す平面図、第２図は第１図の
一部拡大平面図、第３図は変形例の外部リード部
分を示す平面図、第４図は別の変形例の外部リー
ド部分を示す平面図、第５図は従来の樹脂封止型
ハイブリツドICを示す平面図である。
３１……支持板、３３……連結外部リード、３
４〜３９……非連結外部リード、４０……回路装
置、４２……パワートランジスタチツプ、５４…
…幅広部、５５……幅狭部。
Fig. 1 is a plan view showing a resin-sealed hybrid IC according to an embodiment of the present invention, Fig. 2 is a partially enlarged plan view of Fig. 1, and Fig. 3 is a plan view showing an external lead portion of a modified example. , FIG. 4 is a plan view showing an external lead portion of another modification, and FIG. 5 is a plan view showing a conventional resin-sealed hybrid IC. 31...Support plate, 33...Connection external lead, 3
4-39...Unconnected external lead, 40...Circuit device, 42...Power transistor chip, 54...
...Wide part, 55...Narrow part.
Claims (1)
沿つて伸び、かつ前記第１の方向に直交する第２
の方向に沿つて互いに並置され、かつ前記連結外
部リード３３に対しても並置されている複数の非
連結外部リード３４〜３９と、 前記支持板３１に固着された半導体チツプ４２
及び回路装置４０と、 前記半導体チツプ４２の上面側の電極を前記複
数の非連結外部リード３４〜３９から選択された
ものに接続するための第１の内部リード４４，４
５と、 前記回路装置４０を前記複数の非連結外部リー
ド３４〜３９から選択されたものに接続するため
の第２の内部リード４６〜４９と、 前記支持板３１、前記連結外部リード３３及び
前記非連結外部リード３４〜３９の一部、前記半
導体チツプ４２、前記回路装置４０、及び前記第
１及び第２の内部リード４４，４５，４６〜４９
を封止する絶縁封止体５０と から成り、前記連結外部リード３３及び前記非連
結外部リード３４〜３９が幅広部５４，５６と幅
狭部５５，５７とをそれぞれ有し、前記幅広部５
４，５６は前記支持板３１に近い方に配設され、
前記絶縁封止体５０が前記幅広部５４，５６の一
部を覆うが、前記幅広部５４，５６の残部と前記
幅狭部５５，５７とを覆わないように形成されて
いる絶縁物封止型回路装置において、 前記連結外部リード３３と前記非連結外部リー
ド３４〜３９とから成る外部リード配列の一方の
端に前記連結外部リード３３が配置されており、 前記連結外部リード３３の前記幅広部５４の前
記非連結外部リード３４〜３９側の端が、前記連
結外部リード３３の幅狭部５５の前記非連結外部
リード３４〜３９側の端の延長線５８から突出し
ないように、又は前記連結外部リード３３の前記
幅広部５４の前記非連結外部リード３４〜３９側
の端が前記幅狭部５５の端の前記延長線５８から
突出する幅ａを、前記連結外部リード３３の前記
幅広部５４の反対側の端が前記連結外部リード３
３の前記幅狭部５５の反対側の端の延長線５９か
ら突出する幅ｂよりも小さくなるように前記連結
外部リード３３の幅広部５４が形成されており、 前記半導体チツプ４２は前記支持板３１の前記
第１の方向に延びる中心線５２と前記支持板３１
の前記連結外部リード５５が設けられている側の
側面との間に配置されており、 前記回路装置４０は前記支持板３１の前記半導
体チツプ４２が配置されている領域と前記支持板
３１の前記一端側との間の領域及び前記中心線５
２を横切る領域を含む部分に配置されており、 前記半導体チツプ４２の下面の電極は前記支持
板３１に電気的に接続されており、 前記半導体チツプ４２の上面の電極４２ａ，４
２ｂは前記回路装置４０を経由して前記連結外部
リード３３の隣りの前記非連結外部リード３４，
３５に前記第１の内部リード４４，４５によつて
接続されていることを特徴とする絶縁物封止型回
路装置。[Claims for Utility Model Registration] A support plate 31 having a connecting external lead 33; a second support plate 31 extending along a first direction from near one end of the support plate 31 and perpendicular to the first direction;
a plurality of uncoupled external leads 34 to 39 arranged in parallel with each other along the direction of the coupling external leads 33; and a semiconductor chip 42 fixed to the support plate 31.
and a circuit device 40, and first internal leads 44, 4 for connecting an electrode on the upper surface side of the semiconductor chip 42 to one selected from the plurality of unconnected external leads 34 to 39.
5, second internal leads 46 to 49 for connecting the circuit device 40 to one selected from the plurality of unconnected external leads 34 to 39; the support plate 31, the connected external leads 33, and the second internal leads 46 to 49; A portion of the unconnected external leads 34 to 39, the semiconductor chip 42, the circuit device 40, and the first and second internal leads 44, 45, 46 to 49
The connected external lead 33 and the unconnected external leads 34 to 39 have wide parts 54 and 56 and narrow parts 55 and 57, respectively, and the wide part 5
4 and 56 are arranged closer to the support plate 31,
The insulation sealing body 50 covers a part of the wide parts 54, 56, but does not cover the remaining parts of the wide parts 54, 56 and the narrow parts 55, 57. In the type circuit device, the connected external lead 33 is arranged at one end of an external lead array consisting of the connected external lead 33 and the unconnected external leads 34 to 39, and the wide part of the connected external lead 33 54 on the side of the unconnected external leads 34 to 39 does not protrude from the extension line 58 of the end of the narrow part 55 of the connected external lead 33 on the side of the unconnected external leads 34 to 39, or The width a of the wide portion 54 of the external lead 33 on the side of the uncoupled external leads 34 to 39 protrudes from the extension line 58 of the end of the narrow width portion 55 is defined as the width a of the wide portion 54 of the coupled external lead 33. The opposite end of the connecting external lead 3
The wide portion 54 of the connecting external lead 33 is formed so as to be smaller than the width b protruding from the extension line 59 of the opposite end of the narrow portion 55 of No. 3, and the semiconductor chip 42 is connected to the supporting plate. 31 extending in the first direction and the support plate 31
The circuit device 40 is disposed between the side surface of the support plate 31 on which the semiconductor chip 42 is disposed and the side surface of the support plate 31 on which the semiconductor chip 42 is disposed. the area between the one end side and the center line 5
The electrodes on the lower surface of the semiconductor chip 42 are electrically connected to the support plate 31, and the electrodes 42a and 4 on the upper surface of the semiconductor chip 42
2b is the uncoupled external lead 34 adjacent to the coupled external lead 33 via the circuit device 40;
35 through the first internal leads 44, 45.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987049712U JPH0451489Y2 (en) | 1987-03-31 | 1987-03-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987049712U JPH0451489Y2 (en) | 1987-03-31 | 1987-03-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63155650U JPS63155650U (en) | 1988-10-12 |
| JPH0451489Y2 true JPH0451489Y2 (en) | 1992-12-03 |
Family
ID=30872419
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987049712U Expired JPH0451489Y2 (en) | 1987-03-31 | 1987-03-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0451489Y2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2515406B2 (en) * | 1989-09-05 | 1996-07-10 | 株式会社東芝 | Resin-sealed semiconductor device |
| JP4651652B2 (en) * | 2001-05-18 | 2011-03-16 | 三洋電機株式会社 | Power circuit equipment |
| JP2010016289A (en) * | 2008-07-07 | 2010-01-21 | Mitsubishi Electric Corp | Semiconductor package and semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57155757A (en) * | 1981-03-23 | 1982-09-25 | Hitachi Ltd | Semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59115653U (en) * | 1983-01-25 | 1984-08-04 | サンケン電気株式会社 | Insulator-encapsulated semiconductor device |
-
1987
- 1987-03-31 JP JP1987049712U patent/JPH0451489Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57155757A (en) * | 1981-03-23 | 1982-09-25 | Hitachi Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63155650U (en) | 1988-10-12 |
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